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| 2549k?avr?01/07 features ? high performance, low power avr ? 8-bit microcontroller ? advanced risc architecture ? 135 powerful instructions ? most single clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? up to 16 mips throughput at 16 mhz ? on-chip 2-cycle multiplier ? non-volatile progra m and data memories ? 64k/128k/256k bytes of in-system self-programmable flash endurance: 10,000 write/erase cycles ? optional boot code section with independent lock bits in-system programming by on-chip boot program true read-while-w rite operation ? 4k bytes eeprom endurance: 100,000 write/erase cycles ? 8k bytes internal sram ? up to 64k bytes optional external memory space ? programming lock for software security ? jtag (ieee std. 1149.1 compliant) interface ? boundary-scan capabilities a ccording to the jtag standard ? extensive on-chip debug support ? programming of flash, eeprom, fuses, an d lock bits through the jtag interface ? peripheral features ? two 8-bit timer/counters with se parate prescaler and compare mode ? four 16-bit timer/counter with separate prescaler, compare- and capture mode ? real time counter with separate oscillator ? four 8-bit pwm channels ? six/twelve pwm channels with programma ble resolution from 2 to 16 bits (atmega1281/2561, atmega640/1280/2560) ? output compare modulator ? 8/16-channel, 10-bit adc (atmega1281/2561, atmega640/1280/2560) ? two/four programmable serial usart (atmega1281/2561,atmega640/1280/2560) ? master/slave spi serial interface ? byte oriented 2-wire serial interface ? programmable watchdog timer with separate on-chip oscillator ? on-chip analog comparator ? interrupt and wake-up on pin change ? special microcontroller features ? power-on reset and programmable brown-out detection ? internal calibrated oscillator ? external and internal interrupt sources ? six sleep modes: idle, adc noise reduction, power-save, power-down, standby, and extended standby ? i/o and packages ? 54/86 programmable i/o lines (atmega1281/2561, atmega640/1280/2560) ? 64-pad qfn/mlf, 64-lead tqfp (atmega1281/2561) ? 100-lead tqfp, 100-ball cbga (atmega640/1280/2560) ? rohs/fully green ? temperature range: ?-40 c to 85 c industrial ? ultra-low power consumption ? active mode: 1 mhz, 1.8v: 510 a ? power-down mode: 0.1 a at 1.8v ? speed grade (see ?maximum sp eed vs. vcc? on page 377): ? atmega640v/atmega1280v/atmega1281v: 0 - 4 mhz @ 1.8 - 5.5v, 0 - 8 mhz @ 2.7 - 5.5v ? atmega2560v/atmega2561v: 0 - 2 mhz @ 1.8 - 5.5v, 0 - 8 mhz @ 2.7 - 5.5v ? atmega640/atmega1280/atmega1281: 0 - 8 mhz @ 2.7 - 5.5v, 0 - 16 mhz @ 4.5 - 5.5v ? atmega2560/atmega2561: 0 - 16 mhz @ 4.5 - 5.5v 8-bit microcontroller with 64k/128k/256k bytes in-system programmable flash atmega640/v atmega1280/v atmega1281/v atmega2560/v atmega2561/v preliminary
2 atmega640/1280/1281/2560/2561 2549k?avr?01/07 pin configurations figure 1. tqfp-pinout atmega640/1280/2560 gnd v cc pa0 (ad0) pa1 (ad1) pa2 (ad2) pa3 (ad3) pa4 (ad4) pa5 (ad5) pa6 (ad6) pa7 (ad7) pg2 (ale) a v c c gnd aref pf0 (adc0) pf1 (adc1) pf2 (adc2) pf3 (adc3) pf4 (adc4/tck) pf5 (adc5/tms) pf6 (adc6/tdo) pf7 (adc7/tdi) atme g a640/12 8 0/2560 100 99 9 8 97 96 95 94 93 92 91 90 8 9 88 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0797 8 77 76 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 8 19 20 21 22 23 24 25 75 74 73 72 71 70 69 6 8 67 66 65 64 63 62 61 60 59 5 8 57 56 55 54 53 52 51 26 2 8 29 31 27 36 30 32 35 37 33 34 3 8 39 40 41 42 43 44 45 46 47 4 8 49 50 pk0 (adc 8 /pcint16) pk1 (adc9/pcint17) pk2 (adc10/pcint1 8 ) pk3 (adc11/pcint19) pk4 (adc12/pcint20) pk5 (adc13/pcint21) pk6 (adc14/pc int22) pk7 (adc15/pc int23) (oc2b) ph6 (tosc2) pg3 (tosc1) pg4 reset (t4) ph7 (icp4) pl0 v cc gnd xtal2 xtal1 pl6 pl7 gnd v cc (oc0b) pg5 v cc gnd (rxd2) ph0 (txd2) ph1 (xck2) ph2 (oc4a) ph3 (oc4b) ph4 (oc4c) ph5 (rxd0/pcint 8 ) pe0 (txd0) pe1 (xck0/ain0) pe2 (oc3a/ain1) pe3 (oc3b/int4) pe4 (oc3c/int5) pe5 (t3/int6) pe6 (clko/icp3/int7) pe7 (ss/pcint0) pb0 (sck/pcint1) pb1 (mosi/pcint2) pb2 (miso/pcint3) pb3 (oc2a/pcint4) pb4 (oc1a/pcint5) pb5 (oc1b/pcint6) pb6 (oc0a/oc1c/pcint7) pb7 pc7 (a15) pc6 (a14) pc5 (a13) pc4 (a12) pc3 (a11) pc2 (a10) pc1 (a9) pc0 (a 8 ) pg1 (rd) pg0 (wr) (txd1/int3) pd3 (icp1) pd4 (xck1) pd5 (t1) pd6 (t0) pd7 (scl/int0) pd0 (sda/int1) pd 1 (rxd1/int2) pd2 (icp5) pl1 (t5) pl2 (oc5a) pl3 (oc5b) pl4 pj6 (pcint15) pj5 (pcint14) pj4 (pcint13) pj3 (pcint12) pj2 (xck3/pcint11) pj1 (txd3/pcint10) pj0 (rxd3/pcint9) pj7 (oc5c) pl5 index corner 3 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 2. cbga-pinout atmega640/1280/2560 table 1. cbga-pinout atmega640/1280/2560. 12 345678910 a g n d aref pf0 pf2 pf5 pk0 pk3 pk6 g n dvcc b avcc pg5 pf1 pf3 pf6 pk1 pk4 pk7 pa0 pa2 c pe2 pe0 pe1 pf4 pf7 pk2 pk5 pj7 pa1 pa3 d pe3 pe4 pe5 pe6 ph2 pa4 pa5 pa6 pa7 pg2 e pe7 ph0 ph1 ph3 ph5 pj6 pj5 pj4 pj3 pj2 f vcc ph4 ph6 pb0 pl4 pd1 pj1 pj0 pc7 g n d g g n d pb1 pb2 pb5 pl2 pd0 pd5 pc5 pc6 vcc h pb3 pb4 reset pl1 pl3 pl7 pd4 pc4 pc3 pc2 j ph7 pg3 pb6 pl0 xtal2 pl6 pd3 pc1 pc0 pg1 k pb7 pg4 vcc g n d xtal1 pl5 pd2 pd6 pd7 pg0 a b c d e f g h j k 1 2345678910 a b c d e f g h j k 1098765432 1 top view bottom view 4 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 3. pinout atmega1281/2561 n ote: the large center pad underneath the qf n /mlf package is made of metal and internally connected to g n d. it should be soldered or glued to the board to ensure good mechani- cal stability. if the center pad is left uncon nected, the package might loosen from the board. disclaimer typical values contained in this datasheet are based on simulations and characteriza- tion of other avr microcontrollers manufactured on the same process technology. min. and max values will be available afte r the device is characterized. atmega12 8 1/2561 (rxd0/pcint8/pdi) pe0 (txd0/pdo) pe1 (xck0/ain0) pe2 (oc3a/ain1) pe3 (oc3b/int4) pe4 (oc3c/int5) pe5 (t3/int6) pe6 (icp3/clko/int7) pe7 (ss/pcint0) pb0 (oc0b) pg5 (sck/ pcint1) pb1 (mosi/ pcint2) pb2 (miso/ pcint3) pb3 (oc2a/ pcint4) pb4 (oc1a/pcint5) pb5 (oc1b/pcint6) pb6 (oc0a/oc1c/ pcint7 ) pb7 (tosc2) pg3 (tosc1) pg4 reset vcc gnd xtal2 xtal1 (scl/int0) pd0 (sda/int1 ) pd1 (rxd1/int2) pd2 (txd1/int3) pd3 (icp1) pd4 (xck1) pd5 pa3 (ad3) pa4 (ad4) pa5 (ad5) pa6 (ad6) pa7 (ad7) pg2 (ale) pc7 (a15) pc6 (a14) pc5 (a13) pc4 (a12) pc3 (a11) pc2 (a10) pc1 (a9) pc0 (a8) pg1 (rd) pg0 (wr) avcc gnd aref pf0 (adc0) pf1 (adc1) pf2 (adc2) pf3 (adc3) pf4 (adc4/tck) pf5 (adc5/tms ) pf6 (adc6/tdo) pf7 (adc7/tdi) gnd vcc pa0 (ad0) pa 1 (ad1) pa 2 (ad2) (t1) pd6 (t0) pd7 index corner 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 5 atmega640/1280/1281/2560/2561 2549k?avr?01/07 overview the atmega640/1280/1281/2560/2561 is a low-power cmos 8-bit microcontroller based on the avr enhanced risc architecture. by executing powerful instructions in a single clock cycle, the atmega640/1280/1281/2560/2561 achieves throughputs appr oaching 1 mips per mhz allowing th e system designer to optimize po wer consumption versus processing speed. block diagram figure 4. block diagram cpu g n d vcc reset power supervision por / bod & reset w atchdog oscillator w atchdog timer oscillator circuits / clock generation xtal1 xtal2 pc7..0 port c (8) pa7..0 port a (8) port d (8) pd7..0 port b (8) pb7..0 port e (8) pe7..0 port f (8) pf7..0 port j (8) pj7..0 pg5..0 port g (6) port h (8) ph7..0 port k (8) pk7..0 port l (8) pl7..0 xram t w i spi eeprom jtag 8bit t/c 0 8bit t/c 2 16bit t/c 1 16bit t/c 3 sram flash 16bit t/c 4 16bit t/c 5 usart 2 usart 1 usart 0 internal bandgap reference analog comparator a/d converter usart 3 note: shaded parts only available in the 100-pin version. complete functionality for the adc, t/c4, and t/c5 only available in the 100-pin version. 6 atmega640/1280/1281/2560/2561 2549k?avr?01/07 the avr core combines a rich instruction se t with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional cisc microcontrollers. the atmega640/1280/1281/2560/2561 provides the following features: 64k/128k/256k bytes of in-system programmable flash with read- w hile- w rite capabilities, 4k bytes eeprom, 8k bytes sram, 54/86 general purpose i/o lines, 32 general purpose work- ing registers, real time counter (rtc), six flexible timer/counters with compare modes and p w m, 4 usarts, a byte oriented 2-wire serial interface, a 16-channel, 10- bit adc with optional differential input st age with programmable gain, programmable w atchdog timer with internal oscillator, an spi serial port, ieee std. 1149.1 compliant jtag test interface, also used for accessing the on-chip debug system and program- ming and six software selectable power saving modes. the idle mode stops the cpu while allowing the sram, time r/counters, spi port, and interrupt system to continue functioning. the power-down mode saves the register contents bu t freezes the oscilla- tor, disabling all other chip functions unt il the next interrupt or hardware reset. in power-save mode, the asynchronous timer continues to run, allowing the user to main- tain a timer base while the rest of the device is sleeping. the adc n oise reduction mode stops the cpu and all i/o modules except asynchronous timer and adc, to min- imize switching noise during adc conversions. in standby mode, the crystal/resonator oscillator is running while the re st of the device is sleeping. this allows very fast start-up combined with low power consumption. in extended standby mode, both the main oscillator and the a synchronous timer continue to run. the device is manufactured using atmel?s hi gh-density nonvolatile memory technology. the on-chip isp flash allows the program memory to be reprogrammed in-system through an spi serial interface, by a conventional nonvolatile memory programmer, or by an on-chip boot program running on the avr core. the boot program can use any interface to download the application program in the application flash memory. soft- ware in the boot flas h section will continue to run while the application flash section is updated, providing true read- w hile- w rite operation. by combining an 8-bit risc cpu with in-system self-programmable fl ash on a monolithic chip, the atmel atmega640/1280/1281/2560/2561 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. the atmega640/1280/1281/2560/2561 avr is supported with a full suite of program and system development tools including: c compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. 7 atmega640/1280/1281/2560/2561 2549k?avr?01/07 comparison between atme ga1281/2561 and at mega640/1280/2560 each device in the atmega640/1280/1281/2560/2561 family differs only in memory size and number of pins. table 2 summarizes the different configurations for the six devices. pin descriptions vcc digital supply voltage. gnd ground. port a (pa7..pa0) port a is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port a output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port a pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port a pins are tri-stated when a reset condition becomes active, even if the clock is not running. port a also serves the functions of various special features of the atmega640/1280/1281/2560/2561 as listed on page 91. port b (pb7..pb0) port b is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port b output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port b pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b has better driving ca pabilities than th e other ports. port b also serves the functions of various special features of the atmega640/1280/1281/2560/2561 as listed on page 92. port c (pc7..pc0) port c is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port c output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port c pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port c pins are tri-stated when a reset condition becomes active, even if the clock is not running. port c also serves the functions of special features of the atmega640/1280/1281/2560/2561 as listed on page 95. port d (pd7..pd0) port d is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port d output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port d pi ns that are externally pulled low will source table 2. configuration summary device flash eeprom ram general purpose i/o pins 16 bits resolution pwm channels serial usarts adc channels atmega640 64kb 4kb 8kb 86 12 4 16 atmega1280 128kb 4kb 8kb 86 12 4 16 atmega1281 128kb 4kb 8kb 54 6 2 8 atmega2560 256kb 4kb 8kb 86 12 4 16 atmega2561 256kb 4kb 8kb 54 6 2 8 8 atmega640/1280/1281/2560/2561 2549k?avr?01/07 current if the pull-up resistors are activated. the port d pins are tri-stated when a reset condition becomes active, even if the clock is not running. port d also serves the functions of various special features of the atmega640/1280/1281/2560/2561 as listed on page 97. port e (pe7..pe0) port e is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port e output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port e pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port e pins are tri-stated when a reset condition becomes active, even if the clock is not running. port e also serves the functions of various special features of the atmega640/1280/1281/2560/2561 as listed on page 99. port f (pf7..pf0) port f serves as analog inputs to the a/d converter. port f also serves as an 8-bit bi-directional i/o port, if the a/d converter is not used. port pins can provide internal pull-up resistors (selected for each bit). the port f output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port f pins that are externally pulled low will source current if the pull-up resistors are activated. the port f pins are tri-stated when a reset condition becomes active, even if the clock is not running. if th e jtag interface is enabled, the pull-up resis- tors on pins pf7(tdi), pf 5(tms), and pf4(tck) will be activated even if a reset occurs. port f also serves the functions of the jtag interface. port g (pg5..pg0) port g is a 6-bit i/o port with internal pull-up resistors (selected for each bit). the port g output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port g pins that are ex ternally pulled low will source current if the pull-up resistors are activated. the port g pins are tri-stated when a reset condition becomes active, even if the clock is not running. port g also serves the functions of various special features of the atmega640/1280/1281/2560/2561 as listed on page 105. port h (ph7..ph0) port h is a 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port h output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port h pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port h pins are tri-stated when a reset condition becomes active, even if the clock is not running. port h also serves the functions of various special features of the atmega640/1280/2560 as listed on page 107. port j (pj7..pj0) port j is a 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port j output buffers have symmetric al drive characteristics with both high sink and source capability. as inpu ts, port j pins that are externally pulled low will source current if the pull-up resistors are activated. the port j pins are tri-stated when a reset condition becomes active, even if the clock is not running. port j also serves the functions of various special features of the atmega640/1280/2560 as listed on page 109. port k (pk7..pk0) port k serves as analog inputs to the a/d converter. 9 atmega640/1280/1281/2560/2561 2549k?avr?01/07 port k is a 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port k output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port k pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port k pins are tri-stated when a reset condition becomes active, even if the clock is not running. port k also serves the functions of various special features of the atmega640/1280/2560 as listed on page 111. port l (pl7..pl0) port l is a 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port l output buffers have symmetri cal drive characteristics with both high sink and source capability. as inputs, port l pins that are externally pulled low will source current if the pull-up resistors are activated. the port l pins are tri-stated when a reset condition becomes active, even if the clock is not running. port l also serves the functions of various special features of the atmega640/1280/2560 as listed on page 113. reset reset input. a low level on this pin for longer than the minimu m pulse length will gener- ate a reset, even if the clock is not running. the minimum pulse length is given in table 26 on page 58. shorter pulses are not guaranteed to generate a reset. xtal1 input to the inverting oscillato r amplifier and input to the in ternal clock operating circuit. xtal2 output from the invert ing oscillator amplifier. avcc avcc is the supply voltage pin for port f and the a/d converter. it should be externally connected to v cc , even if the adc is not used. if the adc is used, it should be con- nected to v cc through a low-pass filter. aref this is the analog reference pin for the a/d converter. resources a comprehensive set of development tools and application notes, and datasheets are available for download on http://www.atmel.com/avr. about code examples this documentation contains simple code examples that briefly show how to use various parts of the device. be aware that not all c compiler vendors include bit definitions in the header files and interrupt handling in c is compiler dependent. please confirm with the c compiler documentatio n for more details. these code examples assume that the part specific header file is included before com- pilation. for i/o registers located in extended i/o map, "i n ", "out", "sbis", "sbic", "cbi", and "sbi" instructions must be replaced with instructions that allow access to extended i/o. typically "lds" and "sts" combined with "sbrs", "sbrc", "sbr", and "cbr". 10 atmega640/1280/1281/2560/2561 2549k?avr?01/07 avr cpu core introduction this section discusses the avr core archit ecture in general. the main function of the cpu core is to ensure correct program execution. the cpu must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. architectural overview figure 5. block diagram of the avr architecture in order to maximize performance and para llelism, the avr uses a harvard architecture ? with separate memories and buses for program and data. instructions in the program memory are executed with a single level pipelining. w hile one instruction is being exe- cuted, the next instruction is pre-fetched from the program memory. this concept enables instructions to be executed in every clock cycle. the program memory is in- system reprogrammable flash memory. the fast-access register file contains 32 x 8-bit general purpose working registers with a single clock cycle access time. this allows single-cycle arithmetic logic unit (alu) operation. in a typical alu operation, two operands are output from the register file, flash program memory instruction register instruction decoder program counter control lines 32 x 8 general purpose registrers alu status and control i/o lines eeprom data bus 8-bit data sram direct addressing indirect addressing interrupt unit spi unit w atchdog timer analog comparator i/o module 2 i/o module1 i/o module n 11 atmega640/1280/1281/2560/2561 2549k?avr?01/07 the operation is executed, and the result is stored back in the register file ? in one clock cycle. six of the 32 registers can be used as three 16-bit indirect address register pointers for data space addressing ? enabling efficient address calculations. one of the these address pointers can also be used as an addr ess pointer for look up tables in flash pro- gram memory. these added function registers are the 16-bit x-, y-, and z-register, described later in this section. the alu supports arithmetic and logic operations between registers or between a con- stant and a register. single register operations can also be executed in the alu. after an arithmetic operation, the status register is updated to reflect information about the result of the operation. program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address s pace. most avr instructions have a single 16-bit word format. every program memory address contains a 16- or 32-bit instruction. program flash memory space is divided in two sections, the boot program section and the application program section. both sections have dedicated lock bits for write and read/write protection. the spm instruction that writes into the application flash memory section must reside in the boot program section. during interrupts and subroutine calls, the return address program counter (pc) is stored on the stack. the stack is effectively allocated in the general data sram, and consequently the stack size is only limited by the total sram size and the usage of the sram. all user programs must initialize the sp in the reset routine (before subroutines or interrupts are executed). the stack pointer (sp) is read/write accessible in the i/o space. the data sram can easily be accessed through the five different addressing modes supported in the avr architecture. the memory spaces in the avr architecture are all linear and regular memory maps. a flexible interrupt module has its control registers in the i/o space with an additional global interrupt enable bit in the status register. all interrupts have a separate interrupt vector in the interrupt vector table. the interrupts have priority in accordance with their interrupt vector position. the lower the interrupt vector address, the higher the priority. the i/o memory space contains 64 addresse s for cpu peripheral functions as control registers, spi, and other i/o functions. the i/o memory can be accessed directly, or as the data space locations following those of the register file, 0x20 - 0x5f. in addition, the atmega640/1280/1281/2560/2561 has extended i/o space from 0x60 - 0x1ff in sram where only the st/sts/std and ld /lds/ldd instructions can be used. alu ? arithmetic logic unit the high-performance avr alu operates in direct connection with all the 32 general purpose working registers. w ithin a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. the alu operations are divided into three main categories ? arithmetic, logical, and bit-func- tions. some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. see the ?instruc- tion set? section for a detailed description. status register the status register contains information about the result of the most recently executed arithmetic instruction. this information can be used for altering program flow in order to perform conditional operations. n ote that the status register is updated after all alu operations, as specified in the instructio n set reference. this will in many cases 12 atmega640/1280/1281/2560/2561 2549k?avr?01/07 remove the need for using the dedicated compare instructions, resulting in faster and more compact code. the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. this must be handled by software. sreg ? avr status register the avr status register ? sreg ? is defined as: ? bit 7 ? i: global interrupt enable the global interrupt enable bit must be set for the interrupts to be enabled. the individ- ual interrupt enable control is then performed in separate control registers. if the global interrupt enable register is cleared, n one of the interrupts are enabled independent of the individual interrupt enable settings. the i-bit is cleared by hardware after an interrupt has occurred, and is set by the reti instruction to enable subsequent interrupts. the i- bit can also be set and cleared by the application with the sei and cli instructions, as described in the instruction set reference. ? bit 6 ? t: bit copy storage the bit copy instructions bld (bit load) and bst (bit store) use the t-bit as source or destination for the operated bit. a bit from a register in the register file can be copied into t by the bst instruction, and a bit in t can be copied into a bit in a register in the register file by the bld instruction. ? bit 5 ? h: half carry flag the half carry flag h indicates a half carry in some arithmetic operations. half carry is useful in bcd arithmetic. see the ?instruction set description? for detailed information. ? bit 4 ? s: sign bit, s = n v the s-bit is always an exclusive or between the n egative flag n and the two?s comple- ment overflow flag v. see the ?instruction set description? for detailed information. ? bit 3 ? v: two?s complement overflow flag the two?s complement overflow flag v supports two?s complement arithmetics. see the ?instruction set description? for detailed information. ? bit 2 ? n: negative flag the n egative flag n indicates a negative result in an arithmetic or logic operation. see the ?instruction set description? for detailed information. ? bit 1 ? z: zero flag the zero flag z indicates a zero result in an arithmetic or logic operation. see the ?instruction set description? for detailed information. ? bit 0 ? c: carry flag the carry flag c indicates a carry in an arit hmetic or logic operation. see the ?instruc- tion set description? for detailed information. bit 76543210 0x3f (0x5f) i t h s v n z c sreg read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 13 atmega640/1280/1281/2560/2561 2549k?avr?01/07 general purpose register file the register file is optimized for the avr enhanced risc instruction set. in order to achieve the required performance and flexib ility, the following inpu t/output schemes are supported by the register file: ? one 8-bit output operand and one 8-bit result input ? two 8-bit output operands and one 8-bit result input ? two 8-bit output operands and one 16-bit result input ? one 16-bit output operand and one 16-bit result input figure 6 shows the structure of the 32 general purpose working registers in the cpu. figure 6. avr cpu general purpose w orking registers most of the instructions operating on the register file have direct access to all registers, and most of them are single cycle instructions. as shown in figure 6 on page 13, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user data space. although not being physically implemented as sram locations, this memory organiza- tion provides great flexibility in access of the registers, as the x-, y- and z-pointer registers can be set to index any register in the file. 7 0 addr. r0 0x00 r1 0x01 r2 0x02 ? r13 0x0d general r14 0x0e purpose r15 0x0f w orking r16 0x10 registers r17 0x11 ? r26 0x1a x-register low byte r27 0x1b x-register high byte r28 0x1c y-register low byte r29 0x1d y-register high byte r30 0x1e z-register low byte r31 0x1f z-register high byte 14 atmega640/1280/1281/2560/2561 2549k?avr?01/07 the x-register, y-register, and z-register the registers r26..r31 have some added f unctions to their general purpose usage. these registers are 16-bit address pointers for indirect addressing of the data space. the three indirect address registers x, y, and z are defined as described in figure 7. figure 7. the x-, y-, and z-registers in the different addressing modes these addres s registers have functions as fixed dis- placement, automatic increment, and automatic decrement (see the instruction set reference for details). stack pointer the stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. the stack pointer regis- ter always points to the top of the stack. n ote that the stack is implemented as growing from higher memory locations to lower memory locations. this implies that a stack push command decreases the stack pointer. the stack pointer points to the data sram stack area where the subroutine and inter- rupt stacks are located. this stack space in the data sram must be defined by the program before any subroutine calls are executed or interrupts are enabled. the stack pointer must be set to point above 0x0200. the initial value of the stack pointer is the last address of the internal sram. the stack pointer is decremented by one when data is pushed onto the stack with the push instruction, and it is decremented by two for atmega640/1280/1281 and three for atmega2560/2561 when the return address is pushed onto the stack with subroutine call or interrupt. the stack pointer is incre- mented by one when data is popped from the stack with the pop instruction, and it is incremented by two for atmega640/1280/1281 and three for atmega2560/2561 when data is popped from the stack with return from subroutine ret or return from interrupt reti. the avr stack pointer is implemented as two 8-bit registers in the i/o space. the num- ber of bits actually used is implementation dependent. n ote that the data space in some implementations of the avr architecture is so small that only spl is needed. in this case, the sph register will not be present. 15 xh xl 0 x-register 707 0 r27 (0x1b) r26 (0x1a) 15 yh yl 0 y-register 707 0 r29 (0x1d) r28 (0x1c) 15 zh zl 0 z-register 70 7 0 r31 (0x1f) r30 (0x1e) bit 151413121110 9 8 0x3e (0x5e) sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sph 0x3d (0x5d) sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 spl 76543210 read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 1 0 0 0 0 1 11111111 15 atmega640/1280/1281/2560/2561 2549k?avr?01/07 rampz ? extended z-pointer register for elpm/spm for elpm/spm instructions, the z-pointer is a concatenation of rampz, zh, and zl, as shown in figure 8. n ote that lpm is not affected by the rampz setting. figure 8. the z-pointer used by elpm and spm the actual number of bits is implementation dependent. unused bits in an implementa- tion will always read as zero. for compatibility wit h future devices, be sure to write these bits to zero. eind ? extended indirect register for eicall/eijmp instructions, the indirect-pointer to the subroutine/routine is a con- catenation of ei n d, zh, and zl, as shown in figure 9. n ote that icall and ijmp are not affected by the ei n d setting. figure 9. the indirect-pointer used by eicall and eijmp the actual number of bits is implementation dependent. unused bits in an implementa- tion will always read as zero. for compatibility wit h future devices, be sure to write these bits to zero. bit 765432 1 0 0x3b (0x5b) rampz7 rampz6 rampz5 rampz4 rampz3 rampz2 rampz1 rampz0 rampz read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value000000 0 0 bit ( individually) 707070 rampz zh zl bit (z-pointer) 23 16 15 8 7 0 bit 765432 1 0 0x3c (0x5c) eind7 eind6 eind5 eind4 ei nd3 eind2 eind1 eind0 eind read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value000000 0 0 bit (individual- ly) 707070 eind zh zl bit (indirect- pointer) 23 16 15 8 7 0 16 atmega640/1280/1281/2560/2561 2549k?avr?01/07 instruction execution timing this section describes the general access timing concepts for instruction execution. the avr cpu is driven by the cpu clock clk cpu , directly generated from the selected clock source for the chip. n o internal clock division is used. figure 10 shows the parallel instruction fetches and instruction executions enabled by the harvard architecture and the fast-access register file concept. this is the basic pipelining concept to obtain up to 1 mips per mhz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. figure 10. the parallel instruction fetches and instruction executions figure 11 shows the internal timing concept for the register file. in a single clock cycle an alu operation using two register operands is executed, and the result is stored back to the destination register. figure 11. single cycle alu operation clk 1st instruction fetch 1st instruction execute 2nd instruction fetch 2nd instruction execute 3rd instruction fetch 3rd instruction execute 4th instruction fetch t1 t2 t3 t4 cpu total execution time register operands fetch alu operation execute result write back t1 t2 t3 t4 clk cpu 17 atmega640/1280/1281/2560/2561 2549k?avr?01/07 reset and interrupt handling the avr provides several different interrupt sources. these interrupts and the separate reset vector each have a separate program vector in the program memory space. all interrupts are assigned individual enable bits which must be written logic one together with the global interrupt enable bit in the status register in order to enable the interrupt. depending on the program counter value, in terrupts may be automatically disabled when boot lock bits blb02 or blb12 are programmed. this feature improves software security. see the section ?memory programming? on page 342 for details. the lowest addresses in the program memory space are by default defined as the reset and interrupt vectors. the complete list of vectors is shown in ?interrupts? on page 69. the list also determines the priority levels of the different interrupts. the lower the address the higher is the prio rity level. reset has the hi ghest priority, and next is i n t0 ? the external interrupt request 0. the interrupt vectors can be moved to the start of the boot flash section by setting the ivsel bit in the mcu control register (mcucr). refer to ?interrupts? on page 69 for more information. the reset vector can also be moved to the start of the boot flash section by programming the bootrst fuse, see ?memory programming? on page 342. w hen an interrupt occurs, the global interrupt enable i-bit is cleared and all interrupts are disabled. the user software can write logic one to the i-bit to enable nested inter- rupts. all enabled interrupts can then interrupt the current interrupt routine. the i-bit is automatically set when a return from interrupt instruction ? reti ? is executed. there are basically two types of interrupts. the first type is triggered by an event that sets the interrupt flag. for these interrupts, the program counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt flag. interr upt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. if an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be set and remem- bered until the interrupt is enabled, or the flag is cleared by software. similarly, if one or more interrupt conditions occur while the global interrupt enable bit is cleared, the cor- responding interrupt flag(s) will be set and remembered until the global interrupt enable bit is set, and will then be executed by order of priority. the second type of interrupts will trigger as long as the interrupt condition is present. these interrupts do not necessarily have interrupt flags. if the interrupt condition disap- pears before the interrupt is enabled , the interrupt will not be triggered. w hen the avr exits from an inte rrupt, it will always return to the main pr ogram and exe- cute one more instruction before any pending interrupt is served. n ote that the status register is not automatically stored when entering an interrupt rou- tine, nor restored when returning from an interrupt routine. this must be handled by software. w hen using the cli instruction to disable inte rrupts, the interrupts will be immediately disabled. n o interrupt will be executed after the cli in struction, even if it occurs simulta- 18 atmega640/1280/1281/2560/2561 2549k?avr?01/07 neously with the cli instruction. the following example shows how this can be used to avoid interrupts during the timed eeprom write sequence. w hen using the sei inst ruction to enable inte rrupts, the instruction following sei will be executed before any pending interrupts, as shown in this example. interrupt response time the interrupt execution response for all the enabled avr interrupts is five clock cycles minimum. after five clock cycles the program vector address for the actual interrupt han- dling routine is executed. during these fi ve clock cycle period, the program counter is pushed onto the stack. the vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. if an interr upt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. if an interrupt occurs when the mcu is in sleep mode, the interrupt execution response time is increased by five clock cycles. this increase comes in addition to the start-up time from the selected sleep mode. a return from an interrupt handling routi ne takes five clock cycles. during these five clock cycles, the program counter (three bytes) is popped back from the stack, the stack pointer is incremented by three, and the i-bit in sreg is set. assembly code example in r16, sreg ; store sreg value cli ; disable interrupts during timed sequence sbi eecr, eempe ; start eeprom write sbi eecr, eepe out sreg, r16 ; restore sreg value (i-bit) c code example char csreg; csreg = sreg; /* store sreg value */ /* disable interrupts during timed sequence */ __disable_interrupt(); eecr |= (1< 20 atmega640/1280/1281/2560/2561 2549k?avr?01/07 sram data memory table 4 on page 21 shows how the atmega640/1280/1281/2560/2561 sram memory is organized. the atmega640/1280/1281/2560/2561 is a complex microcontroller with more periph- eral units than can be supported within the 64 location reserved in the opcode for the i n and out instructions. for the extended i/o space from $060 - $1ff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. the first 4,608/8,704 data memory locations address both the register file, the i/o memory, extended i/o memory, and the internal data sram. the first 32 locations address the register file, the next 64 location the standard i/o memory, then 416 loca- tions of extended i/o memory and the next 8,192 locations address the internal data sram. an optional external data sram can be used with the atmega640/1280/128 1/2560/2561. this sram will occu py an area in the remaining address locations in the 64k address space. this area starts at the address following the internal sram. the register file, i/o, extended i/o and internal sram occupies the lowest 4,608/8,704 bytes, so when using 64kb (65,536 bytes) of external memory, 60,478/56,832 bytes of external memory are available. see ?external memory inter- face? on page 26 for details on how to take advantage of the external memory map. w hen the addresses accessing the sram me mory space exceeds the internal data memory locations, the external data sram is accessed using the same instructions as for the internal data memory access. w hen the internal data memories are accessed, the read and write strobe pins (pg0 and pg1) are inactive during the whole access cycle. external sram oper ation is enabled by setting the sre bit in the xmcra register. accessing external sram takes one additional clock cycle per byte compared to access of the internal sram. this means that the commands ld, st, lds, sts, ldd, std, push, and pop take one additional clock cycl e. if the stack is placed in external sram, interrupts, subroutine calls and returns take three clock cycles extra because the three-byte program counter is pushed and popped, and external memory access does not take advantage of the internal pipe-line memory access. w hen external sram inter- face is used with wait-state, one-byte external access takes two, three, or four additional clock cycles for one, two, and three wait-states respectively. interrupts, subroutine calls and returns will need five, seven, or nine clock cycles more than specified in the instruc- tion set manual for one, two, and three wait-states. the five different addressing modes for the data memory cover: direct, indirect with dis- placement, indirect, indirect with pre-decrement, and indirect with post-increment. in the register file, registers r26 to r31 feature the indirect addressing pointer registers. the direct addressing reaches the entire data space. the indirect with displacement mode reaches 63 address locations from the base address given by the y- or z-register. w hen using register indirect addressing modes with automatic pre-decrement and post- increment, the address registers x, y, and z are decremented or incremented. the 32 general purpose working registers, 64 i/o registers, and the 4,196/8,192 bytes of internal data sram in the atmega640/1280/1281/2560/2561 are all accessible through 21 atmega640/1280/1281/2560/2561 2549k?avr?01/07 all these addressing modes. the register file is described in ?general purpose regis- ter file? on page 13. data memory access times this section describes the general access ti ming concepts for internal memory access. the internal data sram access is performed in two clk cpu cycles as described in figure 12. figure 12. on-chip data sram access cycles table 4. data memory map address (hex) 0 - 1f 32 registers 20 - 5f 64 i/o registers 60 - 1ff 416 external i/o registers 200 internal sram (8192 x 8) 21ff 2200 external sram (0 - 64k x 8) ffff clk wr rd data data address address valid t1 t2 t3 compute address read write cpu memory access instruction next instruction 22 atmega640/1280/1281/2560/2561 2549k?avr?01/07 eeprom data memory the atmega640/1280/1281/2560/2561 contains 4k bytes of data eeprom memory. it is organized as a separate data space, in which single bytes can be read and written. the eeprom has an e ndurance of at least 100,000 write/erase cycles. the access between the eeprom and the cpu is descri bed in the following, specifying the eeprom address registers, the eeprom data register, and the eeprom control register. for a detailed description of spi, jtag and parallel data downloading to the eeprom, see ?serial downloading? on page 356, ?programming via the jtag interface? on page 361, and ?programmi ng the eeprom? on pa ge 350 resp ectively. eeprom read/write access the eeprom access registers are accessible in the i/o space, see ?register descrip- tion? on page 32. the write access time for the eeprom is given in table 5 on page 22. a self-timing function, however, lets the user software detect when the next byte can be written. if the user code contains instruct ions that write the eeprom, some precautions must be taken. in heavily filtered power supplies, v cc is likely to rise or fall slowly on power- up/down. this causes the device for some period of time to run at a voltage lower than specified as minimum for the clock freque ncy used. see ?preventing eeprom corrup- tion? on page 24. for details on how to avoid problems in these situations. in order to prevent unintentional eeprom writes, a specific write procedure must be fol- lowed. see the description of the eeprom control register for details on this, ?register description? on page 32. w hen the eeprom is read, the cpu is halt ed for four clock cycles before the next instruction is executed. w hen the eeprom is written, the cpu is halted for two clock cycles before the next instruction is executed. the calibrated oscillator is us ed to time the eeprom access es. table 5 lists the typical programming time for eeprom access from the cpu. the following code examples show one assembly and one c function for writing to the eeprom. the examples assume that interrupts are controlled (e.g. by disabling inter- rupts globally) so that no inte rrupts will occur during execut ion of these functions. the examples also assume that no flash boot loader is present in the software. if such code is present, the eeprom write function must also wait for any ongoing spm com- mand to finish. table 5. eeprom programming time symbol number of calibrated rc oscillator cycles typ programming time eeprom write (from cpu) 26,368 3.3 ms 23 atmega640/1280/1281/2560/2561 2549k?avr?01/07 n ote: 1. see ?about code examples? on page 9. assembly code example () eeprom_write: ; wait for completion of previous write sbic eecr,eepe rjmp eeprom_write ; set up address (r18:r17) in address register out eearh, r18 out eearl, r17 ; write data (r16) to data register out eedr,r16 ; write logical one to eempe sbi eecr,eempe ; start eeprom write by setting eepe sbi eecr,eepe ret c code example (1) void eeprom_write( unsigned int uiaddress, unsigned char ucdata) { /* wait for completion of previous write */ while(eecr & (1< 26 atmega640/1280/1281/2560/2561 2549k?avr?01/07 external memory interface w ith all the features the external memory inte rface provides, it is well suited to operate as an interface to memory devices such as external sram and flash, and peripherals such as lcd-display, a/d, and d/a. the main features are: ? four different wait-state settin gs (including no wait-state). ? independent wait-state setting for different external memory sectors (configurable sector size) ? the number of bits dedicated to address high byte is selectable ? bus keepers on data lines to mini mize current consumption (optional) overview w hen the external memory (xmem) is enabl ed, address space outside the internal sram becomes available using the dedicated external memory pins (see figure 3 on page 4, table 39 on page 91, table 45 on page 95, and table 57 on page 105). the memory configuration is shown in figure 13. figure 13. external memory with sector select using the external memory interface the interface consists of: ? ad7:0: multiplexed low-order address bus and data bus. ? a15:8: high-order address bus (configurable number of bits). ? ale: address latch enable. ?rd : read strobe. ? w r : w rite strobe. the control bits for the external memory inte rface are located in two registers, the exter- nal memory control register a ? xmcra, and the external memory control register b ? xmcrb. w hen the xmem interface is enabled, the xm em interface will override the setting in the data direction registers that corresponds to the ports dedicated to the xmem interface. memory configuration a 0x0000 0x21ff external memory (0-60k x 8) 0xffff internal memory srl[2..0] srw11 srw10 srw01 srw00 lower sector upper sector 0x2200 27 atmega640/1280/1281/2560/2561 2549k?avr?01/07 for details about the port override, see the alternate functions in section ?i/o-ports? on page 83. the xmem inte rface will auto-detect whether an a ccess is internal or external. if the access is external, the xmem interface will output address, data, and the control signals on the ports according to figure 15 (this figure shows the wave forms without wait-states). w hen ale goes from high-to-low, there is a valid address on ad7:0. ale is low during a data transfer. w hen the xmem interface is enabled, also an internal access will cause activity on address, data and ale ports, but the rd and w r strobes will not toggle during internal access. w hen the external memory interface is disabled, the nor- mal pin and data direction settings are used. n ote that when the xmem interface is disabled, the address space above the internal sram boundary is not mapped into the internal sram. figure 14 illust rates how to connect an extern al sram to the avr using an octal latch (typically ?74 x 573? or equivalent) which is transparent when g is high. address latch requirements due to the high-speed operation of the xram interface, the address latch must be selected with care for system frequencies above 8 mhz @ 4v and 4 mhz @ 2.7v. w hen operating at conditions above these frequencies, the typical old style 74hc series latch becomes inadequate. the external memory interface is designed in compliance to the 74ahc series latch. however, most latches can be used as long they comply with the main timing parameters. the main parameters for the address latch are: ? d to q propagation delay (t pd ). ? data setup time before g low (t su ). ? data (address) hold time after g low ( th ). the external memory interface is des igned to guaranty minimum address hold time after g is asserted low of t h = 5 ns. refer to t laxx_ld /t llaxx_st in ?external data memory timing? tables 173 through tables 180 on pages 385 - 387. the d-to-q propagation delay (t pd ) must be taken into consideration when calculating the access time require- ment of the external component. the data setup time before g low (t su ) must not exceed address valid to ale low (t avllc ) minus pcb wiring delay (dependent on the capacitive load). figure 14. external sram connected to the avr d[7:0] a[7:0] a[15:8] rd wr sram dq g ad7:0 ale a15:8 rd wr avr 28 atmega640/1280/1281/2560/2561 2549k?avr?01/07 pull-up and bus-keeper the pull-ups on the ad7:0 ports may be activated if the corresponding port register is written to one. to reduce power consumptio n in sleep mode, it is recommended to dis- able the pull-ups by writing the port register to zero before entering sleep. the xmem interface also provides a bus -keeper on the ad7:0 lines. the bus-keeper can be disabled and enabled in software as described in ?xmcrb ? external memory control register b? on page 36. w hen enabled, the bus-keeper will keep the previous value on the ad7:0 bus while these lines are tri-stated by the xmem interface. timing external memory devices hav e different timing requirements. to meet these require- ments, the xmem interface provides four different wait-states as shown in table 8. it is important to consider the timing specification of the external memory device before selecting the wait-state. the most important parameters are the access time for the external memory compared to the set-up requirement. the access time for the external memory is defined to be the time from receiving the chip select/address until the data of this address actually is driven on the bus. the access time cannot exceed the time from the ale pulse must be asserted low until data is stable during a read sequence (see t llrl + t rlrh - t dvrh in tables 173 through tables 180 on pages 385 - 387). the different wait-states are set up in software. as an additional feature, it is possible to divide the external memory space in two sectors with individual wait-state settings. this makes it possible to connect two different memory devices with different timing requirements to the same xmem interface. for xmem interface timing details, please refer to table 173 to table 180 and figure 163 to figure 166 in the ?external data memory timing? on page 385. n ote that the xmem interface is asynchronous and that the waveforms in the following figures are related to the internal system clock. the skew between the internal and external clock (xtal1) is not guarantied (v aries between devices temperature, and sup- ply voltage). consequently, the xmem interface is not suited for synchronous operation. figure 15. external data memory cycles without w ait-state (sr w n1=0 and sr w n0=0) n ote: 1. sr w n1 = sr w 11 (upper sector) or sr w 01 (lower sector), sr w n0 = sr w 10 (upper sector) or sr w 00 (lower sector). the ale pulse in period t4 is only present if the next instruction accesses the ram (internal or external). ale t1 t2 t3 w rite read w r t4 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data prev. data address data prev. data address da7:0 (xmbk = 1) system clock (clk cpu ) xxxxx xxxxxxxx 29 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 16. external data memory cycles with sr w n1 = 0 and sr w n0 = 1 (1) n ote: 1. sr w n1 = sr w 11 (upper sector) or sr w 01 (lower sector), sr w n0 = sr w 10 (upper sector) or sr w 00 (lower sector). the ale pulse in period t5 is only present if the next instruction accesses the ram (internal or external). figure 17. external data memory cycles with sr w n1 = 1 and sr w n0 = 0 (1) n ote: 1. sr w n1 = sr w 11 (upper sector) or sr w 01 (lower sector), sr w n0 = sr w 10 (upper sector) or sr w 00 (lower sector). the ale pulse in period t6 is only present if the next instruction accesses the ram (internal or external). ale t1 t2 t3 w rite read w r t5 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data prev. data address data prev. data address da7:0 (xmbk = 1) system clock (clk cpu ) t4 ale t1 t2 t3 w rite read w r t6 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data prev. data address data prev. data address da7:0 (xmbk = 1) system clock (clk cpu ) t4 t5 30 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 18. external data memory cycles with sr w n1 = 1 and sr w n0 = 1 (1) n ote: 1. sr w n1 = sr w 11 (upper sector) or sr w 01 (lower sector), sr w n0 = sr w 10 (upper sector) or sr w 00 (lower sector). the ale pulse in period t7 is only present if the next instruction accesses the ram (internal or external). using all locations of external memory smaller than 64 kb since the external memory is mapped after the internal memory as shown in figure 13, the external memory is not addressed when addressing the first 8,704 bytes of data space. it may appear that the first 8,704 byte s of the external memory are inaccessible (external memory addresses 0x0000 to 0x21ff). however, when connecting an exter- nal memory smaller than 64 kb, for example 32 kb, these locations are easily accessed simply by addressing from address 0x8000 to 0xa1ff. since the external memory address bit a15 is not connected to the external memory, addresses 0x8000 to 0xa1ff will appear as addresses 0x0000 to 0x21ff fo r the external memory. addressing above address 0xa1ff is not recommended, since this will address an external memory loca- tion that is already accessed by another (low er) address. to the application software, the external 32 kb memory will appear as one linear 32 kb address space from 0x2200 to 0xa1ff. this is illu strated in figure 19. figure 19. address map with 32 kb external memory ale t1 t2 t3 write read wr t7 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data prev. data address data prev. data address da7:0 (xmbk = 1) system clock (clk cpu ) t4 t5 t6 0x0000 0x21ff 0x2200 0x7fff 0x8000 0x90ff 0x9100 0x0000 0x7fff internal memory avr memory map external 32k sram external memory 31 atmega640/1280/1281/2560/2561 2549k?avr?01/07 using all 64kb locations of external memory since the external memory is mapped after th e internal memory as shown in figure 13, only 56kb of external memory is available by default (address space 0x0000 to 0x21ff is reserved for internal memory). however, it is possible to take advantage of the entire external memory by masking the higher address bits to zero. this can be done by using the xmmn bits and control by software the most significant bits of the address. by set- ting port c to output 0x00, and releasing the most significant bits for normal port pin operation, the memory interface will address 0x0000 - 0x2fff. see the following code examples. care must be exercised using this option as most of the memory is masked away. n ote: 1. see ?about code examples? on page 9. assembly code example (1) ; offset is defined to 0x4000 to ensure ; external memory access ; configure port c (address high byte) to ; output 0x00 when the pins are released ; for normal port pin operation ldi r16, 0xff out ddrc, r16 ldi r16, 0x00 out portc, r16 ; release pc7:6 ldi r16, (1< 33 atmega640/1280/1281/2560/2561 2549k?avr?01/07 ? bit 3 ? eerie: eeprom ready interrupt enable w riting eerie to one enables the eeprom ready interrupt if the i bit in sreg is set. w riting eerie to zero disables the interrupt. the eeprom ready interrupt generates a constant interrupt when eepe is cleared. ? bit 2 ? eempe: eeprom master programming enable the eempe bit determines whether setti ng eepe to one causes the eeprom to be written. w hen eempe is set, setting eepe within fo ur clock cycles will write data to the eeprom at the selected address if eempe is zero, setting eepe will have no effect. w hen eempe has been written to one by software, hardware clears the bit to zero after four clock cycles. see the description of the eepe bit for an eeprom write procedure. ? bit 1 ? eepe: eeprom programming enable the eeprom w rite enable signal eepe is the write strobe to the eeprom. w hen address and data are correctly set up, the eepe bit must be written to one to write the value into the eeprom. the eempe bit must be written to one before a logical one is written to eepe, otherwise no eeprom wr ite takes place. the following procedure should be followed when writing the eeprom (the order of steps 3 and 4 is not essential): 1. w ait until eepe becomes zero. 2. w ait until spme n in spmcsr becomes zero. 3. w rite new eeprom address to eear (optional). 4. w rite new eeprom data to eedr (optional). 5. w rite a logical one to the eempe bit wh ile writing a zero to eepe in eecr. 6. w ithin four clock cycles after setting eempe, write a logical one to eepe. the eeprom can not be programmed during a cpu write to the flash memory. the software must check that the flash programming is completed before initiating a new eeprom write. step 2 is only relevant if the software contains a boot loader allowing the cpu to program the flash. if the flash is never being updated by the cpu, step 2 can be omitted. see ?memory programming? on page 342 for details about boot programming. caution: an interrupt be tween step 5 and step 6 will make the write cycle fail, since the eeprom master w rite enable will time-out. if an interrupt routine accessing the eeprom is interrupting an other eeprom access , the eear or eedr register will be modified, causing the interrupted eeprom ac cess to fail. it is recommended to have the global interrupt flag cleared during all the steps to avoid these problems. w hen the write access time has elapsed, the eepe bit is cleared by hardware. the user software can poll this bit and wait for a zero before writing the next byte. w hen eepe has been set, the cpu is halted for two cycles before the next instruction is executed. table 6. eeprom mode bits eepm1 eepm0 programming time operation 0 0 3.4 ms erase and w rite in one operation (atomic operation) 0 1 1.8 ms erase only 1 0 1.8 ms w rite only 1 1 ? reserved for future use 34 atmega640/1280/1281/2560/2561 2549k?avr?01/07 ? bit 0 ? eere: eeprom read enable the eeprom read enable si gnal eere is the read strobe to the eeprom. w hen the correct address is set up in the eear regist er, the eere bit must be written to a logic one to trigger the eeprom re ad. the eeprom read access takes one instruction, and the requested data is av ailable immediately. w hen the eeprom is read, the cpu is halted for four cycles before the next instruction is executed. the user should poll the eepe bi t before starting the read operation. if a write operation is in progress, it is neither possible to read the eeprom, nor to change the eear register. general purpose registers gpior2 ? general purpose i/o register 2 gpior1 ? general purpose i/o register 1 gpior0 ? general purpose i/o register 0 external memory registers xmcra ? external memory control register a ? bit 7 ? sre: extern al sram/xmem enable w riting sre to one enables the external memory interface.the pin functions ad7:0, a15:8, ale, w r , and rd are activated as the alternate pin functions. the sre bit over- rides any pin direction settings in the respective data direction registers. w riting sre to zero, disables the external memory interface and the normal pin and data direction set- tings are used. ? bit 6:4 ? srl2:0: wait-state sector limit it is possible to configure different wait-s tates for different external memory addresses. the external memory address space can be divided in two sectors that have separate wait-state bits. the srl2, srl1, and srl0 bits select the split of the sectors, see table 7 and figure 13. by default, the srl2, srl1, and srl0 bits are set to zero and the entire external memory address space is treated as one sector. w hen the entire sram bit 76543210 0x2b (0x4b) msb lsb gpior2 read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 0x2a (0x4a) msb lsb gpior1 read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 0x1e (0x3e) msb lsb gpior0 read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 ?(0x74)? sre srl2 srl1 srl0 srw11 srw10 srw01 srw00 xmcra read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 35 atmega640/1280/1281/2560/2561 2549k?avr?01/07 address space is configured as one sector , the wait-states are configured by the sr w 11 and sr w 10 bits. ? bit 3:2 ? srw11, srw10: wait-state select bits for upper sector the sr w 11 and sr w 10 bits control the number of wait-states for the upper sector of the external memory address space, see table 8. ? bit 1:0 ? srw01, srw00: wait-state select bits for lower sector the sr w 01 and sr w 00 bits control the number of wait-states for the lower sector of the external memory address space, see table 8. n ote: 1. n = 0 or 1 (lower/upper sector). for further details of the timing and wait-states of the external memory interface, see figures 15 through figures 18 for how the setting of the sr w bits affects the timing. table 7. sector limits with different settings of srl2:0 srl2 srl1 srl0 sector limits 00x lower sector = n /a upper sector = 0x2200 - 0xffff 010 lower sector = 0x2200 - 0x3fff upper sector = 0x4000 - 0xffff 011 lower sector = 0x2200 - 0x5fff upper sector = 0x6000 - 0xffff 100 lower sector = 0x2200 - 0x7fff upper sector = 0x8000 - 0xffff 101 lower sector = 0x2200 - 0x9fff upper sector = 0xa000 - 0xffff 110 lower sector = 0x2200 - 0xbfff upper sector = 0xc000 - 0xffff 111 lower sector = 0x2200 - 0xdfff upper sector = 0xe000 - 0xffff table 8. w ait states (1) srwn1 srwn0 wait states 00 n o wait-states 01 w ait one cycle during read/write strobe 10 w ait two cycles during read/write strobe 11 w ait two cycles during read/write and wait one cycle before driving out new address 36 atmega640/1280/1281/2560/2561 2549k?avr?01/07 xmcrb ? external memory control register b ? bit 7? xmbk: external memory bus-keeper enable w riting xmbk to one enables the bus keeper on the ad7:0 lines. w hen the bus keeper is enabled, ad7:0 will keep the last driven val ue on the lines even if the xmem interface has tri-stated the lines. w riting xmbk to zero disables the bus keeper. xmbk is not qualified with sre, so even if the xmem in terface is disabled, the bus keepers are still activated as long as xmbk is one. ? bit 6:3 ? res: reserved bits these bits are reserved and will always read as zero. w hen writing to this address loca- tion, write these bits to zero fo r compatibility with future devices. ? bit 2:0 ? xmm2, xmm1, xmm0: external memory high mask w hen the external memory is enabled, all port c pins are default used for the high address byte. if the full 60kb address space is not required to access the external mem- ory, some, or all, port c pins can be released for normal port pin function as described in table 9. as described in ?using all 64kb locations of external memory? on page 31, it is possible to use the xmmn bits to access all 64kb locations of the external memory. bit 765 4 3 210 (0x75) xmbk ? ? ? ? xmm2 xmm1 xmm0 xmcrb read/ w rite r/ w rr r rr/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 table 9. port c pins released as n ormal port pins when the external memory is enabled xmm2 xmm1 xmm0 # bits for external memory address released port pins 0 0 0 8 (full 56kb space) n one 0017 pc7 0106 pc7 - pc6 0115 pc7 - pc5 1004 pc7 - pc4 1013 pc7 - pc3 1102 pc7 - pc2 111 n o address high bits full port c 37 atmega640/1280/1281/2560/2561 2549k?avr?01/07 system clock and clock options this section describes the clock options for the avr microcontroller. overview figure 20 presents the principal clock system s in the avr and their distribution. all of the clocks need not be active at a given time. in order to reduce power consumption, the clocks to modules not being used can be halted by using differ ent sleep modes, as described in ?power management and sleep modes? on page 50. the clock systems are detailed below. figure 20. clock distribution general i/o modules asynchronous timer/counter cpu core ram clk i/o clk asy avr clock control unit clk cpu flash and eeprom clk flash source clock watchdog timer watchdog oscillator reset logic clock multiplexer watchdog clock calibrated rc oscillator timer/counter oscillator crystal oscillator low-frequency crystal oscillator external clock adc clk adc system clock prescaler 38 atmega640/1280/1281/2560/2561 2549k?avr?01/07 clock systems and their distribution cpu clock ? clk cpu the cpu clock is routed to parts of the system concerned with operation of the avr core. examples of such modules are the general purpose register file, the status reg- ister and the data memory holding the stack pointer. halting the cpu clock inhibits the core from performing general operations and calculations. i/o clock ? clk i/o the i/o clock is used by the majority of t he i/o modules, like timer/counters, spi, and usart. the i/o clock is also used by the external interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the i/o clock is halted. also note that start condition detection in the usi module is carried out asynchronously when clk i/o is halted, t w i address recognition in all sleep modes. flash clock ? clk flash the flash clock controls operation of the fl ash interface. the flash clock is usually active simultaneously with the cpu clock. asynchronous timer clock ? clk asy the asynchronous timer clock allows the asynchronous timer/counter to be clocked directly from an external clock or an exter nal 32 khz clock crysta l. the dedicated clock domain allows using this timer/counter as a real-time counter even when the device is in sleep mode. adc clock ? clk adc the adc is provided with a dedicated clock domain. this allows halting the cpu and i/o clocks in order to reduce noise generated by digital circuitry. this gives more accu- rate adc conversion results. 39 atmega640/1280/1281/2560/2561 2549k?avr?01/07 clock sources the device has the following clock source options, selectable by flash fuse bits as shown below. the clock from the selected source is input to the avr clock generator, and routed to the appropriate modules. n ote: 1. for all fuses ?1? means unprogrammed while ?0? means programmed. default clock source the device is shipped with internal rc os cillator at 8.0 mhz and with the fuse ckdiv8 programmed, resulting in 1.0 mhz system clock. the startup time is set to maximum and time-out peri od enabled. (cksel = "0 010", sut = "10", ckdiv8 = "0"). the default setting ensures that all users can make t heir desired clock source setting using any available programming interface. clock start-up sequence any clock source needs a sufficient v cc to start oscillating and a minimum number of oscillating cycles before it can be considered stable. to ensure sufficient v cc , the device issues an internal reset with a time-out delay (t tout ) after the device reset is released by all other reset sources. ?on-chip debug system? on page 53 describes the start conditions for the internal reset. the delay (t tout ) is timed from the w atchdog oscillator and the number of cycles in the delay is set by the sutx and ckselx fuse bits. the selectable delay s are shown in table 11. the frequency of the w atchdog oscillator is voltage dependent as shown in ?typical characteristics? on page 390. main purpose of the delay is to keep the avr in reset until it is supplied with minimum vcc. the delay will not monitor th e actual voltage and it will be required to select a delay longer than the vcc rise time. if this is not possible, an internal or external brown-out detection circuit should be used. a bod circuit will ensure sufficient vcc before it releases the reset, and the time-out delay can be disabled. disabling the time-out delay without utilizing a brown-out detect ion circuit is not recommended. the oscillator is required to oscillate for a minimum number of cycles before the clock is considered stable. an internal ripple counte r monitors the oscilla tor output clock, and keeps the internal reset active for a give n number of clock cycles. the reset is then released and the device will start to execut e. the recommended osc illator start-up time table 10. device clocking options select (1) device clocking option cksel3:0 low power crystal oscillator 1111 - 1000 full swing crystal oscillator 0111 - 0110 low frequency crystal oscillator 0101 - 0100 internal 128 khz rc oscillator 0011 calibrated internal rc oscillator 0010 external clock 0000 reserved 0001 table 11. n umber of w atchdog oscillator cycles typ time-out (v cc = 5.0v) typ time-out (v cc = 3.0v) number of cycles 0 ms 0 ms 0 4.1 ms 4.3 ms 512 65 ms 69 ms 8k (8,192) 40 atmega640/1280/1281/2560/2561 2549k?avr?01/07 is dependent on the clock type, and varies fr om 6 cycles for an externally applied clock to 32k cycles for a low frequency crystal. the start-up sequence for the clock includes both the time-out delay and the start-up time when the device starts up from reset. w hen starting up from power-save or power- down mode, vcc is assumed to be at a sufficient level and only the start-up time is included. low power crystal oscillator pins xtal1 and xtal2 are input and output, respectively, of an inverting amplifier which can be configured for use as an on-c hip oscillator, as shown in figure 21. either a quartz crystal or a ceramic resonator may be used. this crystal oscillator is a low power oscillator, with reduced voltage swing on the xtal2 output. it gives the lowest power consumption, but is not capable of driving other clock inputs, and may be more susceptible to noise in noisy environments. in these cases, refer to the ?f ull swing crystal osc illator? on page 42. c1 and c2 should always be equal for both crystals and resonators. the optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capac- itance, and the electromagnetic noise of the environment. some initial guidelines for choosing capacitors for use with crystals are given in table 12. for ceramic resonators, the capacitor values given by the manufacturer should be used. figure 21. crystal oscillator connections the low power oscillator can operate in three different modes, each optimized for a specific frequency range. the operating mode is selected by the fuses cksel3:1 as shown in table 12. n otes: 1. the frequency ranges are preliminary values. actual values are tbd. 2. this option should not be used with crystals, only with ceramic resonators. 3. if 8 mhz frequency exceeds the specification of the device (depends on v cc ), the ckdiv8 fuse can be programmed in order to divide the internal frequency by 8. it must be ensured that the resulting divided clock meets the freq uency specification of the device. table 12. low power crystal osc illator operating modes (3) frequency range (1) (mhz) cksel3:1 recommended range for capacitors c1 and c2 (pf) 0.4 - 0.9 100 (2) ? 0.9 - 3.0 101 12 - 22 3.0 - 8.0 110 12 - 22 8.0 - 16.0 (4) 111 12 - 22 xtal2 xtal1 gnd c2 c1 41 atmega640/1280/1281/2560/2561 2549k?avr?01/07 4. max frequency when using ceramic oscillator is 10 mhz. the cksel0 fuse together with the sut1:0 fuses select the start-up times as shown in table 13. n otes: 1. these options should only be used wh en not operating close to the maximum fre- quency of the device, and only if frequency stabili ty at start-up is not important for the application. these options ar e not suitable for crystals. 2. these options are intended for use with ceramic resonators and will ensure fre- quency stability at start-up. they can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application. table 13. start-up times for the low power crystal oscillator clock selection oscillator source / power conditions start-up time from power-down and power-save additional delay from reset (v cc = 5.0v) cksel0 sut1:0 ceramic resonator, fast rising power 258 ck 14ck + 4.1 ms (1) 000 ceramic resonator, slowly rising power 258 ck 14ck + 65 ms (1) 001 ceramic resonator, bod enabled 1k ck 14ck (2) 010 ceramic resonator, fast rising power 1k ck 14ck + 4.1 ms (2) 011 ceramic resonator, slowly rising power 1k ck 14ck + 65 ms (2) 100 crystal oscillator, bod enabled 16k ck 14ck 1 01 crystal oscillator, fast rising power 16k ck 14ck + 4.1 ms 1 10 crystal oscillator, slowly rising power 16k ck 14ck + 65 ms 1 11 42 atmega640/1280/1281/2560/2561 2549k?avr?01/07 full swing crystal oscillator pins xtal1 and xtal2 are input and output, respectively, of an inverting amplifier which can be configured for use as an on-c hip oscillator, as shown in figure 21. either a quartz crystal or a ceramic resonator may be used. this crystal oscillator is a full swing osc illator, with rail-to-rail swing on the xtal2 out- put. this is useful for driving other clock inputs and in noisy environments. the current consumption is higher than the ?low po wer crystal oscillator? on page 40. n ote that the full swing crystal oscillator will only operate for vcc = 2.7 - 5.5 volts. c1 and c2 should always be equal for both crystals and resonators. the optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capac- itance, and the electromagnetic noise of the environment. some initial guidelines for choosing capacitors for use with crystals are given in table 15. for ceramic resonators, the capacitor values given by the manufacturer should be used. the operating mode is selected by th e fuses cksel3:1 as shown in table 14. n otes: 1. the frequency ranges are preliminary values. actual values are tbd. 2. if 8 mhz frequency exceeds the specification of the device (depends on v cc ), the ckdiv8 fuse can be programmed in order to divide the internal frequency by 8. it must be ensured that the resulting divided clock meets the freq uency specification of the device. figure 22. crystal oscillator connections table 14. full swing crystal osc illator oper ating modes (2) frequency range (1) (mhz) cksel3:1 recommended range for capacitors c1 and c2 (pf) 0.4 - 16 011 12 - 22 xtal2 xtal1 gnd c2 c1 43 atmega640/1280/1281/2560/2561 2549k?avr?01/07 n otes: 1. these options should only be used wh en not operating close to the maximum fre- quency of the device, and only if frequency stabili ty at start-up is not important for the application. these options ar e not suitable for crystals. 2. these options are intended for use with ceramic resonators and will ensure fre- quency stability at start-up. they can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application. table 15. start-up times for the full swing crystal oscillator clock selection oscillator source / power conditions start-up time from power-down and power-save additional delay from reset (v cc = 5.0v) cksel0 sut1:0 ceramic resonator, fast rising power 258 ck 14ck + 4.1 ms (1) 000 ceramic resonator, slowly rising power 258 ck 14ck + 65 ms (1) 001 ceramic resonator, bod enabled 1k ck 14ck (2) 010 ceramic resonator, fast rising power 1k ck 14ck + 4.1 ms (2) 011 ceramic resonator, slowly rising power 1k ck 14ck + 65 ms (2) 100 crystal oscillator, bod enabled 16k ck 14ck 1 01 crystal oscillator, fast rising power 16k ck 14ck + 4.1 ms 1 10 crystal oscillator, slowly rising power 16k ck 14ck + 65 ms 1 11 44 atmega640/1280/1281/2560/2561 2549k?avr?01/07 low frequency crystal oscillator the device can utilize a 32.768 khz watch cr ystal as clock source by a dedicated low frequency crystal oscillator. the crystal s hould be connected as shown in figure 21. w hen this oscillator is selected, start-up times are determined by the sut fuses and cksel0 as shown in table 16. n ote: 1. these options should only be used if frequ ency stability at start-up is not important for the application. calibrated internal rc oscillator by defaylt, the internal rc oscillator provides an approximate 8 mhz clock. though volt- age and temperature dependent, this clock can be very accurately calibrated by the user. see table 172 on page 384 and ?internal oscillator speed? on page 409 for more details. the device is shipped with the ckdiv8 fuse programmed. see ?system clock prescaler? on page 47 for more details. this clock may be selected as the system clock by programming the cksel fuses as shown in table 17. if selected, it will operate with no external components. during reset, hardware loads the pre-programmed calibration value into the osccal register and thereby automatically calibrates the rc osc illator. the accuracy of this calibration is shown as factory calibration in table 172 on page 384. by changing the osccal register from s w , see ?osccal ? oscillator calibration reg- ister? on page 48, it is possible to get a higher calibration accuracy than by using the factory calibration. the accuracy of this calibration is shown as user calibration in table 172 on page 384. w hen this oscillator is used as the chip clock, the w atchdog oscillator will still be used for the w atchdog timer and for the reset time-out. for more information on the pre- programmed calibration value, see the section ?calibration byte? on page 345. n otes: 1. the device is shipped with this option selected. 2. the frequency ranges are preliminary values. actual values are tbd. 3. if 8 mhz frequency exceeds the specification of the device (depends on v cc ), the ckdiv8 fuse can be programmed in order to divide the internal frequency by 8. w hen this oscillator is selected, start-up times are determined by the sut fuses as shown in table 18 on page 45. table 16. start-up times for the low frequenc y crystal oscillator clock selection power conditions start-up time from power-down and power-save additional delay from reset (v cc = 5.0v) cksel0 sut1:0 bod enabled 1k ck 14ck (1) 000 fast rising power 1k ck 14ck + 4.1 ms (1) 001 slowly rising power 1k ck 14ck + 65 ms (1) 010 reserved 0 11 bod enabled 32k ck 14ck 1 00 fast rising power 32k ck 14ck + 4.1 ms 1 01 slowly rising power 32k ck 14ck + 65 ms 1 10 reserved 1 11 table 17. internal calibrated rc os cillator oper ating modes (1)(3) frequency range (2) (mhz) cksel3:0 7.3 - 8.1 0010 45 atmega640/1280/1281/2560/2561 2549k?avr?01/07 n ote: 1. the device is shipped with this option selected. 128 khz internal oscillator the 128 khz internal oscillato r is a low power oscillator pr oviding a clock of 128 khz. the frequency is nominal at 3v and 25 c. this clock may be select as the system clock by programming the c ksel fuses to ?11? as shown in table 19. n ote: 1. the frequency is preliminary value. actual value is tbd. w hen this clock source is selected, start-up times are determined by the sut fuses as shown in table 20. external clock to drive the device from an external clock source, xtal1 should be driven as shown in figure 23. to run the device on an extern al clock, the cksel fuses must be pro- grammed to ?0000?. figure 23. external clock drive configuration table 18. start-up times for the internal calib rated rc oscillator clock selection power conditions start-up time from power- down and power-save additional delay from reset (v cc = 5.0v) sut1:0 bod enabled 6 ck 14ck 00 fast rising power 6 ck 14ck + 4.1 ms 01 slowly rising power 6 ck 14ck + 65 ms (1) 10 reserved 11 table 19. 128 khz internal oscillator operating modes nominal frequency cksel3:0 128 khz 0011 table 20. start-up times for the 1 28 khz internal oscillator power conditions start-up time from power- down and power-save additional delay from reset sut1:0 bod enabled 6 ck 14ck 00 fast rising power 6 ck 14ck + 4 ms 01 slowly rising power 6 ck 14ck + 64 ms 10 reserved 11 nc external clock signal xtal2 xtal1 gnd 46 atmega640/1280/1281/2560/2561 2549k?avr?01/07 w hen this clock source is selected, start-up times are determined by the sut fuses as shown in table 23. w hen applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the mcu. a variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. if changes of more than 2% is required, ensure that the mcu is kept in reset during the changes. n ote that the system clock prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operat ion. refer to ?system clock prescaler? on page 47 for details. clock output buffer the device can output the system clock on the clko pin. to enable the output, the ckout fuse has to be programmed. this mode is suitable when the chip clock is used to drive other circuits on the system. the cl ock also will be output during reset, and the normal operation of i/o pin w ill be overridden when the fuse is programmed. any clock source, including the internal rc oscillator, can be selected when the clock is output on clko. if the system clock prescaler is us ed, it is the divided system clock that is output. timer/counter oscillator the device can operate its timer/counter2 from an external 32.768 khz watch crystal or a external clock source. see figure 21 on page 40 for crystal connection. applying an external clock source to tosc1 requires exclk in the assr register writ- ten to logic one. see ?asynchronous operation of timer/counter2? on page 188 for further description on selecting external clock as input instead of a 32 khz crystal. table 21. crystal oscillator clock frequency nominal frequency cksel3:0 0 - 16 mhz 0000 table 22. start-up times for the external clock selection power conditions start-up time from power- down and power-save additional delay from reset (v cc = 5.0v) sut1:0 bod enabled 6 ck 14ck 00 fast rising power 6 ck 14ck + 4.1 ms 01 slowly rising power 6 ck 14ck + 65 ms 10 reserved 11 47 atmega640/1280/1281/2560/2561 2549k?avr?01/07 system clock prescaler the atmega640/1280/1281/2560/2561 has a system clock prescaler, and the system clock can be divided by setting the ?clkpr ? clock prescale register? on page 48. this feature can be used to de crease the system clock fre quency and the power consump- tion when the requirement for processing power is low. this can be used with all clock source options, and it will affect the clock frequency of the cpu and all synchronous peripherals. clk i/o , clk adc , clk cpu , and clk flash are divided by a factor as shown in table 23. w hen switching between prescaler settings, t he system clock prescaler ensures that no glitches occurs in the clock system. it also ensures that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting, nor the clock frequency corresponding to the new setting. the ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the cpu's cl ock frequency. hence, it is not possible to determine the state of the prescaler - even if it were readable, and the exact time it takes to switch from one clock division to the other cannot be exactly predicted. from the time the clkps values are written, it takes between t1 + t2 and t1 + 2 * t2 before the new clock frequency is active. in this interval, 2 active clock edges are produced. here, t1 is the previous clock period, and t2 is t he period corresponding to the new prescaler setting. to avoid unintentional changes of clock frequency, a special write procedure must be followed to chang e the clkps bits: 1. w rite the clock prescaler change enable (clkpce) bit to one and all other bits in clkpr to zero. 2. w ithin four cycles, write the desired value to clkps while writing a zero to clkpce. interrupts must be disabled when changing prescaler setting to make sure the write pro- cedure is not interrupted. 48 atmega640/1280/1281/2560/2561 2549k?avr?01/07 register description osccal ? oscillator calibration register ? bits 7:0 ? cal7:0: oscillator calibration value the oscillator calibration register is used to trim the calibrated internal rc oscillator to remove process variations from the oscillator frequency. a pre-programmed calibra- tion value is automatically written to this register during chip reset, giving the factory calibrated frequency as specified in table 172 on page 384. the application software can write this register to ch ange the oscillator frequency. the oscillator can be calibrated to frequencies as specified in table 172 on page 384. calibration outside that range is not guaranteed. n ote that this oscillator is used to time eeprom and flash write ac cesses, and these write times will be affect ed accordingly. if the eeprom or flash are written, do not cali- brate to more than 8.8 mhz. otherwise, the eeprom or flash write may fail. the cal7 bit determines the range of o peration for the oscillator. setting this bit to 0 gives the lowest frequency range, setting this bit to 1 gives the highest frequency range. the two frequency ranges are overlapping, in other words a setting of osccal = 0x7f gives a higher frequency than osccal = 0x80. the cal6..0 bits are used to tune the frequency within the selected range. a setting of 0x00 gives the lowest frequency in that range, and a setting of 0x7f gives the highest frequency in the range. clkpr ? clock prescale register ? bit 7 ? clkpce: clock prescaler change enable the clkpce bit must be written to logic one to enable change of the clkps bits. the clkpce bit is only updated when the other bi ts in clkpr are simu ltaneously written to zero. clkpce is cleared by hardware four cycl es after it is written or when clkps bits are written. rewriting the clkpce bit within th is time-out period does neither extend the time-out period, nor clear the clkpce bit. ? bits 3:0 ? clkps3:0: clock prescaler select bits 3 - 0 these bits define the division factor between the selected clock source and the internal system clock. these bits can be written run- time to vary the clock frequency to suit the application requirements. as t he divider divides the master clock input to the mcu, the speed of all synchronous peripherals is reduce d when a division factor is used. the divi- sion factors are given in table 23. the ckdiv8 fuse determines the initial value of the clkps bits. if ckdiv8 is unpro- grammed, the clkps bits will be reset to ?0000?. if ckdiv8 is programmed, clkps bits are reset to ?0011?, giving a division factor of 8 at start up. this feature should be used if the selected clock source has a higher frequency than the maximum frequency of the bit 76543210 (0x66) cal7 cal6 cal5 cal4 cal3 cal2 cal1 cal0 osccal read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value device spec ific calibration value bit 76543210 (0x61) clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 clkpr read/ w rite r/ w rrrr/ w r/ w r/ w r/ w initial value 0 0 0 0 see bit description 49 atmega640/1280/1281/2560/2561 2549k?avr?01/07 device at the present operating conditions. n ote that any value can be written to the clkps bits regardless of the ckdiv8 fuse setting. the application software must ensure that a sufficient division factor is ch osen if the selected clock source has a higher frequency than the maximum frequency of th e device at the present operating condi- tions. the device is shipped with the ckdiv8 fuse programmed. table 23. clock prescaler select clkps3 clkps2 clkps1 clkps0 clock division factor 0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved 50 atmega640/1280/1281/2560/2561 2549k?avr?01/07 power management and sleep modes sleep modes enable the application to shut down unused modules in the mcu, thereby saving power. the avr provides various sleep modes allowing the user to tailor the power consumption to the application?s requirements. sleep modes figure 20 on page 37 presents the different clock systems in the atmega640/1280/1281/2560/2561, and their distribution. the figure is helpful in select- ing an appropriate sleep mode. table 24 show s the different sleep modes and their wake-up sources. n otes: 1. only recommended with external crystal or resonator selected as clock source. 2. if timer/counter2 is running in asynchronous mode. 3. for i n t7:4, only level interrupt. to enter any of the sleep modes, the se bit in ?smcr ? sleep mode control register? on page 54 must be written to logic one and a sleep instruction must be executed. the sm2, sm1, and sm0 bits in the smcr register select which sleep mode will be acti- vated by the sleep instru ction. see table 25 on page 54 for a summary. if an enabled interrupt occurs while the m cu is in a sleep mode, the mcu wakes up. the mcu is then halted for four cycles in add ition to the start-up time, executes the interrupt routine, and resume s execution from the instruct ion following sleep. the con- tents of the register file and sram are unaltered when the device wakes up from sleep. if a reset occurs during sleep mode, the mcu wakes up and executes from the reset vector. table 24. active clock domains and w ake-up sources in the different sleep modes. active clock domains oscillators wake-up sources sleep mode clk cpu clk flash clk io clk adc clk asy main clock source enabled timer osc enabled int7:0 and pin change twi address match timer2 spm/ eeprom ready adc wdt interrupt other i/o idle x x x x x (2) xxxxxxx adc n rm x x x x (2) x (3) xx (2) xxx power-down x (3) xx power-save x x (2) x (3) xx x standby (1) xx (3) xx extended standby x (2) xx (2) x (3) xx x 51 atmega640/1280/1281/2560/2561 2549k?avr?01/07 idle mode w hen the sm2:0 bits are written to 000, the sleep instruction makes the mcu enter idle mode, stopping the cpu but allowing the spi, usart, analog comparator, adc, 2-wire serial interface, timer/counters, w atchdog, and the interrupt system to continue operating. this sleep mode basically halts clk cpu and clk flash , while allowing the other clocks to run. idle mode enables the mcu to wake up fr om external triggered interrupts as well as internal ones like the timer overflow and usart transmit complete interrupts. if wake-up from the analog comparator interrupt is not required, the analog comparator can be powered down by setting the acd bit in the analog comparator control and sta- tus register ? acsr. this will reduce power consumption in idle mode. if the adc is enabled, a conversion starts automatically when this mode is entered. adc noise reduction mode w hen the sm2:0 bits are written to 001, the sleep instruction makes the mcu enter adc n oise reduction mode, stopping the cpu but allowing the adc, the external inter- rupts, 2-wire serial interface address match, timer/counter2 and the w atchdog to continue operating (if enabled). this sleep mo de basically halts clki/o, clkcpu, and clk- flash, while allowing the other clocks to run. this improves the noise environment for the adc, enabling higher resolution measure- ments. if the adc is enabled, a conversion starts automatically when this mode is entered. apart form the adc conversion complete interrupt, only an external reset, a w atchdog system reset, a w atchdog interrupt, a brown-out reset, a 2-wire serial inter- face interrupt, a timer/counter2 interrupt, an spm/eeprom ready interrupt, an external level interrupt on i n t7:4 or a pin change interrupt can wakeup the mcu from adc n oise reduction mode. power-down mode w hen the sm2:0 bits are written to 010, the sleep instruction makes the mcu enter power-down mode. in this mode, the external oscillator is stopped, while the external interrupts, the 2-wire serial interface, and the w atchdog continue operating (if enabled). only an external reset, a w atchdog reset, a brown-out reset, 2-wire serial interface address match, an external level interrupt on i n t7:4, an external interrupt on i n t3:0, or a pin change interrupt can wake up the mcu. this sleep mode basically halts all gener- ated clocks, allowing operation of asynchronous modules only. n ote that if a level triggered interrupt is used for wake-up from power-down mode, the changed level must be held for some time to wake up the mcu. refer to ?external inter- rupts? on page 77 for details. w hen waking up from power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. this allows the clock to restart and become stable after having been stopped. the wake-up period is defined by the same cksel fuses that define the reset time-out period, as described in ?clock sources? on page 39. power-save mode w hen the sm2:0 bits are written to 011, the sleep instruction makes the mcu enter power-save mode. this mode is identica l to power-down, with one exception: if timer/counter2 is enabled, it will keep running during sl eep. the device can wake up from either timer overflow or output com pare event from timer/counter2 if the corre- sponding timer/counter2 interrupt enable bits are set in timsk2, and the global interrupt enable bit in sreg is set. if timer/counter2 is not running, power-down mode is recommended instead of power- save mode. 52 atmega640/1280/1281/2560/2561 2549k?avr?01/07 the timer/counter2 can be clocked both synchronously and asynchronously in power- save mode. if the timer/counter2 is not using the asynchronous clock, the timer/counter oscillator is st opped during sleep. if the time r/counter2 is not using the synchronous clock, the clock source is stopped during sleep. n ote that even if the syn- chronous clock is running in power-save , this clock is only available for the timer/counter2. standby mode w hen the sm2:0 bits are 110 and an external crystal/resonator clock option is selected, the sleep instruction makes the mcu enter standby mode. this mode is identical to power-down with the exception that the oscillator is kept running. from standby mode, the device wakes up in six clock cycles. extended standby mode w hen the sm2:0 bits are 111 and an external crystal/resonator clock option is selected, the sleep instruction makes the mcu enter extended standby mode. this mode is identical to power-save mode with the exception that the oscillator is kept running. from extended standby mode, the device wakes up in six clo ck cycles.power reduc- tion register the power reduction register (prr), see ?prr0 ? power reduction register 0? on page 55 and ?prr1 ? power reduction register 1? on page 56, provides a method to stop the clock to individual peripherals to reduce power consumption. the current state of the peripheral is frozen and the i/o regist ers can not be read or written. resources used by the peripheral when stopping the clock will remain occupi ed, hence the periph- eral should in most cases be disabled before stopping the clock. w aking up a module, which is done by clearing the bit in prr, puts the module in the same state as before shutdown. module shutdown can be used in idle mode and active mode to significantly reduce the overall power consumption. see ?supply current of io modules? on page 395 for exam- ples. in all other sleep modes, the clock is already stopped. minimizing power consumption there are several issues to consider when trying to minimize the power consumption in an avr controlled system. in general, sleep modes should be used as much as possi- ble, and the sleep mode should be selected so that as few as pos sible of the device?s functions are operating. all functions not needed should be disabled. in particular, the following modules may need special consider ation when trying to achieve the lowest possible power consumption. analog to digital converter if enabled, the adc will be enabled in all sleep modes. to save power, the adc should be disabled before entering any sleep mode. w hen the adc is turned off and on again, the next conversion will be an ex tended conversion. refer to ?adc ? analog to digital converter? on page 279 for details on adc operation. analog comparator w hen entering idle mode, the analog comparator should be disabled if not used. w hen entering adc n oise reduction mode, the analog comparator should be disabled. in other sleep modes, the analog comparator is automatically disabled. however, if the analog comparator is set up to use the internal voltage reference as input, the analog comparator should be disabled in all sleep modes. otherwise, the internal voltage ref- erence will be enabled, indepe ndent of sleep mode. refer to ?ac ? analog comparator? on page 275 for details on how to configure the analog comparator. 53 atmega640/1280/1281/2560/2561 2549k?avr?01/07 brown-out detector if the brown-out detector is not needed by the application, this module should be turned off. if the brown-out detector is enabled by the bodlevel fuses, it will be enabled in all sleep modes, and hence, always consume power. in the deeper sleep modes, this will contribute significantly to the total curr ent consumption. refer to ?brown-out detec- tion? on page 60 for details on how to configure the brown-out detector. internal voltage reference the internal voltage reference will be enabled when needed by the brown-out detec- tion, the analog comparator or the adc. if these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will not be con- suming power. w hen turned on again, the user must allow the reference to start up before the output is used. if the reference is kept on in sleep mode, the output can be used immediately. refer to ?internal voltage reference? on page 61 for details on the start-up time. watchdog timer if the w atchdog timer is not needed in the application, the module should be turned off. if the w atchdog timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. in the deeper sleep modes, this will contribute significantly to the total current consumption. refer to ?interrupts? on page 69 for details on how to con- figure the w atchdog timer. port pins w hen entering a sleep mode, all port pins should be configured to use minimum power. the most important is then to ensure that no pins drive resistive loads. in sleep modes where both the i/o clock (clk i/o ) and the adc clock (clk adc ) are stopped, the input buff- ers of the device will be disabled. this ensures that no power is consumed by the input logic when not needed. in some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. refer to the section ?digital input enable and sleep modes? on page 87 for details on which pins are enabled. if the input buffer is enabled and the input signal is left floating or have an analog signal level close to v cc /2, the input buffer will use excessive power. for analog input pins, the digital input buffe r should be disabled at all times. an analog signal level close to v cc /2 on an input pin can cause signi ficant current even in active mode. digital input buffers can be disabled by writing to the digital input disable regis- ters (didr2, didr1 and didr0). refer to ?didr2 ? digital input disable register 2? on page 300, ?didr1 ? digital input disable register 1? on page 278 and ?didr0 ? digital input disable register 0? on page 300 for details. on-chip debug system if the on-chip debug system is enabled by the ocde n fuse and the chip enters sleep mode, the main clock source is enabled, a nd hence, always consumes power. in the deeper sleep modes, this will contribute significantly to the total current consumption. there are three alternative ways to disable the ocd system: ? disable the ocde n fuse. ? disable the jtage n fuse. ? w rite one to the jtd bit in mcucr. 54 atmega640/1280/1281/2560/2561 2549k?avr?01/07 register description smcr ? sleep mode control register the sleep mode control register contains control bits for power management. ? bits 3, 2, 1 ? sm2:0: sleep mode select bits 2, 1, and 0 these bits select between the five available sleep modes as shown in table 25. n ote: 1. standby modes are only recommended for use with external crystals or resonators. ? bit 1 ? se: sleep enable the se bit must be written to logic one to make the mcu enter the sleep mode when the sleep instruction is executed. to avoid the mcu entering the sleep mode unless it is the programmer?s purpose, it is recommended to write the sleep enable (se) bit to one just before the execution of the sleep instruction and to cl ear it immediately after wak- ing up. bit 76543210 0x33 (0x53) ????sm2sm1sm0sesmcr read/ w riterrrrr/ w r/ w r/ w r/ w initial value00000000 table 25. sleep mode select sm2 sm1 sm0 sleep mode 000idle 0 0 1 adc n oise reduction 0 1 0 power-down 011power-save 1 0 0 reserved 1 0 1 reserved 1 1 0 standby (1) 1 1 1 extended standby (1) 55 atmega640/1280/1281/2560/2561 2549k?avr?01/07 prr0 ? power reduction register 0 ? bit 7 - prtwi: power reduction twi w riting a logic one to this bit shuts down the t w i by stopping the clock to the module. w hen waking up the t w i again, the t w i should be re initialized to ensure proper operation. ? bit 6 - prtim2: power reduction timer/counter2 w riting a logic one to this bit shuts dow n the timer/counter2 module in synchronous mode (as2 is 0). w hen the timer/counter2 is enabled, operation will continue like before the shutdown. ? bit 5 - prtim0: power reduction timer/counter0 w riting a logic one to this bit shuts down the timer/counter0 module. w hen the timer/counter0 is enabl ed, operation will continue like before the shutdown. ? bit 4 - res: reserved bit this bit is reserved bit and will always read as zero. ? bit 3 - prtim1: power reduction timer/counter1 w riting a logic one to this bit shuts down the timer/counter1 module. w hen the timer/counter1 is enabl ed, operation will continue like before the shutdown. ? bit 2 - prspi: power reduction serial peripheral interface w riting a logic one to this bit shuts down the serial peripheral interface by stopping the clock to the module. w hen waking up the spi again, the spi should be re initialized to ensure proper operation. ? bit 1 - prusart0: power reduction usart0 w riting a logic one to this bit shuts down the usart0 by stopping the clock to the mod- ule. w hen waking up the usart0 again, the usart0 should be re initialized to ensure proper operation. ? bit 0 - pradc: power reduction adc w riting a logic one to this bit shuts down th e adc. the adc must be disabled before shut down. the analog comparator cannot use the adc input mux when the adc is shut down. bit 7 6 543 2 1 0 (0x64) prtwi prtim2 prtim0 ? prtim1 prspi prusart0 pradc prr0 read/ w rite r/ w r/ w r/ w rr/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 56 atmega640/1280/1281/2560/2561 2549k?avr?01/07 prr1 ? power reduction register 1 ? bit 7:6 - res: reserved bits these bits are reserved and will always read as zero. ? bit 5 - prtim5: power reduction timer/counter5 w riting a logic one to this bit shuts down the timer/counter5 module. w hen the timer/counter5 is enabl ed, operation will continue like before the shutdown. ? bit 4 - prtim4: power reduction timer/counter4 w riting a logic one to this bit shuts down the timer/counter4 module. w hen the timer/counter4 is enabl ed, operation will continue like before the shutdown. ? bit 3 - prtim3: power reduction timer/counter3 w riting a logic one to this bit shuts down the timer/counter3 module. w hen the timer/counter3 is enabl ed, operation will continue like before the shutdown. ? bit 2 - prusart3: power reduction usart3 w riting a logic one to this bit shuts down the usart3 by stopping the clock to the mod- ule. w hen waking up the usart3 again, the usart3 should be re initialized to ensure proper operation. ? bit 1 - prusart2: power reduction usart2 w riting a logic one to this bit shuts down the usart2 by stopping the clock to the mod- ule. w hen waking up the usart2 again, the usart2 should be re initialized to ensure proper operation. ? bit 0 - prusart1: power reduction usart1 w riting a logic one to this bit shuts down the usart1 by stopping the clock to the mod- ule. w hen waking up the usart1 again, the usart1 should be re initialized to ensure proper operation. bit 76543 2 1 0 (0x65) ? ? prtim5 prtim4 prtim3 prusart3 prusart2 prusart1 prr1 read/ w rite r r r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 57 atmega640/1280/1281/2560/2561 2549k?avr?01/07 system control and reset resetting the avr during reset, all i/o registers are set to their initial values, and the program starts exe- cution from the reset vector. the instruction placed at the reset vector must be a jmp ? absolute jump ? instruction to the reset handling routine. if the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. this is also the case if the reset vector is in the application section while the interrupt vectors are in the boot section or vice versa. the circuit diagram in figure 24 shows the reset l ogic. table 26 defines the electrical param- eters of the reset circuitry. the i/o ports of the avr are immediately reset to their initial state when a reset source goes active. this does not require any clock source to be running. after all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. this allows the power to reach a stable level before normal operation starts. the time-out period of the delay count er is defined by the user through the sut and cksel fuses. the different selections for the delay period are presented in ?clock sources? on page 39. reset sources the atmega640/1280/1281/2560/2561 has five sources of reset: ? power-on reset. the mcu is reset when the supply voltage is below the power-on reset threshold (v pot ). ? external reset. the mcu is reset when a low level is present on the reset pin for longer than the minimum pulse length. ? w atchdog reset. the mcu is reset when the w atchdog timer period expires and the w atchdog is enabled. ? brown-out reset. the mcu is reset when the supply voltage v cc is below the brown-out reset threshold (v bot ) and the brown-out detector is enabled. ? jtag avr reset. the mcu is reset as long as there is a logic one in the reset register, one of the scan chains of t he jtag system. refer to the section ?ieee 1149.1 (jtag) boundary-scan? on page 308 for details. 58 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 24. reset logic n otes: 1. values are guidelines only. actual values are tbd. 2. the power-on reset will not work unless the supply voltage has been below v pot (falling) power-on reset a power-on reset (por) pulse is generated by an on-chip detection circuit. the detec- tion level is defined in table 26. the por is activated whenever v cc is below the detection level. the por circuit can be used to trigger the start-up reset, as well as to detect a failure in supply voltage. a power-on reset (por) circuit ensures that the device is reset from power-on. reach- ing the power-on reset threshold voltage invokes the delay counter, which determines how long the device is kept in reset after v cc rise. the reset signal is activated again, without any delay, when v cc decreases below t he detection level. table 26. reset characteristics (1) symbol parameter condi tion min typ max units v pot power-on reset threshold voltage (rising) tbd tbd tbd v power-on reset threshold voltage (falling) (2) tbd tbd tbd v v rst reset pin threshold voltage tbd tbd tbd v t rst minimum pulse width on reset pin tbd tbd tbd ns mcu status register (mcusr) brown-out reset circuit bodlevel [2..0] delay counters cksel[3:0] ck timeout wdrf borf extrf porf data b u s clock generator spike filter pull-up resistor jtrf jtag reset register watchdog oscillator sut[1:0] power-on reset circuit 59 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 25. mcu start-up, reset tied to v cc figure 26. mcu start-up, reset extended externally external reset an external reset is generated by a low level on the reset pin. reset pulses longer than the minimum pulse width (see table 26) will generate a reset, even if the clock is not running. shorter pulses are not guaranteed to generate a reset. w hen the applied signal reaches the reset threshold voltage ? v rst ? on its positive edge, the delay counter starts the mcu after the time-out period ? t tout ? has expired. figure 27. external reset during operation v reset time-out internal reset t tout v pot v rst cc reset time-out internal reset t tout v pot v rst v cc cc 60 atmega640/1280/1281/2560/2561 2549k?avr?01/07 brown-out detection atmega640/1280/1281/2560/2561 has an on-chip brown-out detection (bod) circuit for monitoring the v cc level during operation by comparing it to a fixed trigger level. the trigger level for the bod can be selected by the bodlevel fuses. the trigger level has a hysteresis to ensure spike free brown- out detection. the hysteresis on the detec- tion level should be interpreted as v bot+ = v bot + v hyst /2 and v bot- = v bot - v hyst /2. n ote: 1. v bot may be below nominal minimum operating voltage for some devices. for devices where this is the case, t he device is tested down to v cc = v bot during the production test. this guar antees that a brown-out reset will occur before v cc drops to a voltage where correct operation of the microcontroller is no longer guaranteed. the test is performed using bodlevel = 110 for 4 mhz operation of atmega640v/1280v/12 81v/2560v/2561v, bo dlevel = 101 for 8 mhz operation of atmega640v/1280v/1281v/2560v/2561 v and atmega640/1280/1281, and bodlevel = 100 for 16 mhz operation of atmega640/1280/1281/2560/2561. w hen the bod is enabled, and v cc decreases to a value below the trigger level (v bot- in figure 28), the brown-out reset is immediately activated. w hen v cc increases above the trigger level (v bot+ in figure 28), the delay counter starts the mcu after the time- out period t tout has expired. the bod circuit will only detect a drop in v cc if the voltage stays below the trigger level for longer than t bod given in table 26. figure 28. brown-out reset during operation table 27. bodlevel fuse coding (1) bodlevel 2:0 fuses min v bot typ v bot max v bot units 111 bod disabled 110 1.7 1.8 2.0 v 101 2.5 2.7 2.9 100 4.1 4.3 4.5 011 reserved 010 001 000 table 28. brown-out characteristics symbol parameter min typ max units v hyst brown-out detector hysteresis 50 mv t bod min pulse w idth on brown-out reset ns v cc reset time-out internal reset v bot- v bot+ t tout 61 atmega640/1280/1281/2560/2561 2549k?avr?01/07 watchdog reset w hen the w atchdog times out, it will generate a s hort reset pulse of one ck cycle dura- tion. on the falling edge of this pulse, the delay timer starts counting the time-out period t tout . see ? w atchdog timer? on page 53. for details on operation of the w atchdog timer. figure 29. w atchdog reset during operation internal voltage reference atmega640/1280/1281/2560/2561 features an internal bandgap reference. this refer- ence is used for brown-out detection, and it can be used as an input to the analog comparator or the adc. voltage reference enable signals and start-up time the voltage reference has a start-up time that may influence the way it should be used. the start-up time is given in table 29. to save power, the reference is not always turned on. the reference is on during the following situations: 1. w hen the bod is enabled (by prog ramming the bodlevel [2:0] fuse). 2. w hen the bandgap reference is connected to the analog comparator (by setting the acbg bit in acsr). 3. w hen the adc is enabled. thus, when the bod is not enabled, after setting the acbg bit or enabling the adc, the user must always allow the reference to start up before the output from the analog com- parator or adc is used. to reduce power consumption in power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering power-down mode. n ote: 1. values are guidelines only. actual values are tbd. ck cc table 29. internal voltage reference characteristics (1) symbol parameter condi tion min typ max units v bg bandgap reference voltage tbd tbd 1.1 tbd v t bg bandgap reference start-up time tbd 40 70 s i bg bandgap reference current consumption tbd 10 tbd a 62 atmega640/1280/1281/2560/2561 2549k?avr?01/07 watchdog timer atmega640/1280/1281/2560/2561 has an enhanced w atchdog timer ( w dt). the main features are: ? clocked from separate on-chip oscillator ? 3 operating modes ? interrupt ? system reset ? interrupt and system reset ? selectable time-out pe riod from 16ms to 8s ? possible hardware fuse watchdog al ways on (wdton) for fail-safe mode figure 30. w atchdog timer the w atchdog timer ( w dt) is a timer counting cycles of a separate on-chip 128 khz oscillator. the w dt gives an interrupt or a system reset when the counter reaches a given time-out value. in normal operation mo de, it is required that the system uses the w dr - w atchdog timer reset - instruction to restart the counter before the time-out value is reached. if the system doesn't restart the counter, an interrupt or system reset will be issued. in interrupt mode, the w dt gives an interrupt when the timer expires. this interrupt can be used to wake the device from sleep-modes, and also as a general system timer. one example is to limit the maximum time allow ed for certain operations, giving an interrupt when the operation has run longer than expected. in system reset mode, the w dt gives a reset when the timer expires. this is typically used to prevent system hang-up in case of runaway code. the third mode, interrupt and system reset mode, combines the other two modes by first giving an interrupt and then switch to system reset mode. this mode will for instance allow a safe shutdown by saving critical para meters before a sys- tem reset. the w atchdog always on ( w dto n ) fuse, if programmed, will force the w atchdog timer to system reset mode. w ith the fuse programmed the system reset mode bit ( w de) and interrupt mode bit ( w die) are locked to 1 and 0 respectively. to further ensure pro- gram security, alterations to the w atchdog set-up must follow timed sequences. the sequence for clearing w de and changing time-out configuration is as follows: 128khz oscillator osc/2k osc/4k osc/8k osc/16k osc/32k osc/64k osc/128k osc/256k osc/512k osc/1024k wdp0 wdp1 wdp2 wdp3 watchdog reset wde wdif wdie mcu reset interrupt 63 atmega640/1280/1281/2560/2561 2549k?avr?01/07 1. in the same operation, write a logic one to the w atchdog change enable bit ( w dce) and w de. a logic one must be written to w de regardless of the previ- ous value of the w de bit. 2. w ithin the next four clock cycles, write the w de and w atchdog prescaler bits ( w dp) as desired, but with the w dce bit cleared. this must be done in one operation. the following code example shows one assembly and one c function for turning off the w atchdog timer. the example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts wi ll occur during the execution of these functions. 64 atmega640/1280/1281/2560/2561 2549k?avr?01/07 n ote: 1. the example code assumes that the pa rt specific header file is included. n ote: if the w atchdog is accidentally enabled, for example by a runaway pointer or brown-out condition , the device will be reset and the w atchdog timer will stay enabled. if the code is not set up to handle the w atchdog, this might lead to an eternal loop of time-out resets. to avoid this situation, th e application software should always clear the w atchdog system reset flag ( w drf) and the w de control bit in the initialisation rou- tine, even if the w atchdog is not in use. assembly code example (1) wdt_off: ; turn off global interrupt cli ; reset watchdog timer wdr ; clear wdrf in mcusr in r16, mcusr andi r16, (0xff & (0< 67 atmega640/1280/1281/2560/2561 2549k?avr?01/07 timer is in interrupt mode, and the corresponding interrupt is executed if time-out in the w atchdog timer occurs. if w de is set, the w atchdog timer is in interrupt and system reset mode. the first time-out in the w atchdog timer will set w dif. executing the corresponding interrupt vector will clear w die and w dif automatically by hardware (the w atchdog goes to sys- tem reset mode). this is useful for keeping the w atchdog timer security while using the interrupt. to stay in interrupt and system reset mode, w die must be set after each interrupt. this should however not be done within the interrupt service routine itself, as this might compromise the safety-function of the w atchdog system reset mode. if the interrupt is not executed be fore the next time-out, a system reset will be applied. n ote: 1. w dto n fuse set to ?0? means programmed and ?1? means unprogrammed. ? bit 4 - wdce: watchdog change enable this bit is used in timed sequences for changing w de and prescaler bits. to clear the w de bit, and/or change the prescaler bits, w dce must be set. once written to one, hardware will clear w dce after four clock cycles. ? bit 3 - wde: watchdog system reset enable w de is overridden by w drf in mcusr. this means that w de is always set when w drf is set. to clear w de, w drf must be cleared first. this feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure. ? bit 5, 2:0 - wdp3:0: watchdog timer prescaler 3, 2, 1 and 0 the w dp3:0 bits determine the w atchdog timer prescaling when the w atchdog timer is running. the different prescaling values and their corresponding time-out periods are shown in table 31 on page 68. table 30. w atchdog timer configuration wdton (1) wde wdie mode action on time-out 1 0 0 stopped n one 1 0 1 interrupt mode interrupt 1 1 0 system reset mode reset 111 interrupt and system reset mode interrupt, then go to system reset mode 0 x x system reset mode reset 68 atmega640/1280/1281/2560/2561 2549k?avr?01/07 . table 31. w atchdog timer prescale select wdp3 wdp2 wdp1 wdp0 number of wdt oscillator cycles typical time-out at v cc = 5.0v 0 0 0 0 2k (2048) cycles 16 ms 0 0 0 1 4k (4096) cycles 32 ms 0 0 1 0 8k (8192) cycles 64 ms 0 0 1 1 16k (16384) cycles 0.125 s 0 1 0 0 32k (32768) cycles 0.25 s 0 1 0 1 64k (65536) cycles 0.5 s 0 1 1 0 128k (131072) cycles 1.0 s 0 1 1 1 256k (262144) cycles 2.0 s 1 0 0 0 512k (524288) cycles 4.0 s 1 0 0 1 1024k (1048576) cycles 8.0 s 1010 reserved 1011 1100 1101 1110 1111 69 atmega640/1280/1281/2560/2561 2549k?avr?01/07 interrupts this section describes the specifics of the interrupt handling as performed in atmega640/1280/1281/2560/2561. for a general explanation of the avr interrupt han- dling, refer to ?reset and interrupt handling? on page 17. interrupt vectors in atmega640/1280/128 1/2560/2561 table 32. reset and interrupt vectors vector no. program address (2) source interrupt definition 1 $0000 (1) reset external pin, power-on reset, brown-out reset, w atchdog reset, and jtag avr reset 2 $0002 i n t0 external interrupt request 0 3 $0004 i n t1 external interrupt request 1 4 $0006 i n t2 external interrupt request 2 5 $0008 i n t3 external interrupt request 3 6 $000a i n t4 external interrupt request 4 7 $000c i n t5 external interrupt request 5 8 $000e i n t6 external interrupt request 6 9 $0010 i n t7 external interrupt request 7 10 $0012 pci n t0 pin change interrupt request 0 11 $0014 pci n t1 pin change interrupt request 1 12 $0016 (3) pci n t2 pin change interrupt request 2 13 $0018 w dt w atchdog time-out interrupt 14 $001a timer2 compa timer/counter2 compare match a 15 $001c timer2 compb timer/counter2 compare match b 16 $001e timer2 ovf timer/counter2 overflow 17 $0020 timer1 capt timer/counter1 capture event 18 $0022 timer1 compa timer/counter1 compare match a 19 $0024 timer1 compb timer/counter1 compare match b 20 $0026 timer1 compc timer/counter1 compare match c 21 $0028 timer1 ovf timer/counter1 overflow 22 $002a timer0 compa timer/counter0 compare match a 23 $002c timer0 compb timer/counter0 compare match b 24 $002e timer0 ovf timer/counter0 overflow 25 $0030 spi, stc spi serial transfer complete 26 $0032 usart0 rx usart0 rx complete 27 $0034 usart0 udre usart0 data register empty 28 $0036 usart0 tx usart0 tx complete 29 $0038 a n alog comp analog comparator 30 $003a adc adc conversion complete 31 $003c ee ready eeprom ready 70 atmega640/1280/1281/2560/2561 2549k?avr?01/07 n otes: 1. w hen the bootrst fuse is programmed, the device will jump to the boot loader address at reset, see ?memory programming? on page 342. 2. w hen the ivsel bit in mcucr is set, interr upt vectors will be moved to the start of the boot flash section. the address of ea ch interrupt vector will then be the address in this table added to the start address of the boot flash section. 3. only available in atmega640/1280/2560 32 $003e timer3 capt timer/counter3 capture event 33 $0040 timer3 compa timer/counter3 compare match a 34 $0042 timer3 compb timer/counter3 compare match b 35 $0044 timer3 compc timer/counter3 compare match c 36 $0046 timer3 ovf timer/counter3 overflow 37 $0048 usart1 rx usart1 rx complete 38 $004a usart1 udre usart1 data register empty 39 $004c usart1 tx usart1 tx complete 40 $004e t w i 2-wire serial interface 41 $0050 spm ready store program memory ready 42 $0052 (3) timer4 capt timer/counter4 capture event 43 $0054 timer4 compa timer/counter4 compare match a 44 $0056 timer4 compb timer/counter4 compare match b 45 $0058 timer4 compc timer/counter4 compare match c 46 $005a timer4 ovf timer/counter4 overflow 47 $005c (3) timer5 capt timer/counter5 capture event 48 $005e timer5 compa timer/counter5 compare match a 49 $0060 timer5 compb timer/counter5 compare match b 50 $0062 timer5 compc timer/counter5 compare match c 51 $0064 timer5 ovf timer/counter5 overflow 52 $0066 (3) usart2 rx usart2 rx complete 53 $0068 (3) usart2 udre usart2 data register empty 54 $006a (3) usart2 tx usart2 tx complete 55 $006c (3) usart3 rx usart3 rx complete 56 $006e (3)) usart3 udre usart3 data register empty 57 $0070 (3) usart3 tx usart3 tx complete table 32. reset and interrupt vectors (continued) vector no. program address (2) source interrupt definition 71 atmega640/1280/1281/2560/2561 2549k?avr?01/07 reset and interrupt vector placement table 33 on page 71 shows reset and interrupt vectors placement for the various com- binations of bootrst and ivsel settings. if the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. this is also the case if the reset vector is in the application section while the interrupt vectors are in the boot section or vice versa. n ote: 1. the boot reset address is shown in table 140 on page 335 through table 148 on page 339. for the bootrst fuse ?1? means unprogrammed while ?0? means programmed. the most typical and general program setup for the reset and interrupt vector addresses in atmega640/1280/1281/2560/2561 is: table 33. reset and interrupt vectors placement (1) bootrst ivsel reset address interr upt vectors start address 1 0 0x0000 0x0002 1 1 0x0000 boot reset address + 0x0002 0 0 boot reset address 0x0002 0 1 boot reset address boot reset address + 0x0002 address labels code comments 0x0000 jmp reset ; reset handler 0x0002 jmp int0 ; irq0 handler 0x0004 jmp int1 ; irq1 handler 0x0006 jmp int2 ; irq2 handler 0x0008 jmp int3 ; irq3 handler 0x000a jmp int4 ; irq4 handler 0x000c jmp int5 ; irq5 handler 0x000e jmp int6 ; irq6 handler 0x0010 jmp int7 ; irq7 handler 0x0012 jmp pcint0 ; pcint0 handler 0x0014 jmp pcint1 ; pcint1 handler 0x0016 jmp pcint2 ; pcint2 handler 0x0018 jmp wdt ; watchdog timeout handler 0x001a jmp tim2_compa ; timer2 comparea handler 0x001c jmp tim2_compb ; timer2 compareb handler 0x001e jmp tim2_ovf ; timer2 overflow handler 0x0020 jmp tim1_capt ; timer1 capture handler 0x0022 jmp tim1_compa ; timer1 comparea handler 0x0024 jmp tim1_compb ; timer1 compareb handler 0x0026 jmp tim1_compc ; timer1 comparec handler 0x0028 jmp tim1_ovf ; timer1 overflow handler 0x002a jmp tim0_compa ; timer0 comparea handler 0x002c jmp tim0_compb ; timer0 compareb handler 0x002e jmp tim0_ovf ; timer0 overflow handler 0x0030 jmp spi_stc ; spi transfer complete handler 0x0032 jmp usart0_rxc ; usart0 rx complete handler 0x0034 jmp usart0_udre ; usart0,udr empty handler 0x0036 jmp usart0_txc ; usart0 tx complete handler 0x0038 jmp ana_comp ; analog comparator handler 0x003a jmp adc ; adc conversion complete handler 0x003c jmp ee_rdy ; eeprom ready handler 0x003e jmp tim3_capt ; timer3 capture handler 72 atmega640/1280/1281/2560/2561 2549k?avr?01/07 0x0040 jmp tim3_compa ; timer3 comparea handler 0x0042 jmp tim3_compb ; timer3 compareb handler 0x0044 jmp tim3_compc ; timer3 comparec handler 0x0046 jmp tim3_ovf ; timer3 overflow handler 0x0048 jmp usart1_rxc ; usart1 rx complete handler 0x004a jmp usart1_udre ; usart1,udr empty handler 0x004c jmp usart1_txc ; usart1 tx complete handler 0x004e jmp twi ; 2-wire serial handler 0x0050 jmp spm_rdy ; spm ready handler 0x0052 jmp tim4_capt ; timer4 capture handler 0x0054 jmp tim4_compa ; timer4 comparea handler 0x0056 jmp tim4_compb ; timer4 compareb handler 0x0058 jmp tim4_compc ; timer4 comparec handler 0x005a jmp tim4_ovf ; timer4 overflow handler 0x005c jmp tim5_capt ; timer5 capture handler 0x005e jmp tim5_compa ; timer5 comparea handler 0x0060 jmp tim5_compb ; timer5 compareb handler 0x0062 jmp tim5_compc ; timer5 comparec handler 0x0064 jmp tim5_ovf ; timer5 overflow handler 0x0066 jmp usart2_rxc ; usart2 rx complete handler 0x0068 jmp usart2_udre ; usart2,udr empty handler 0x006a jmp usart2_txc ; usart2 tx complete handler 0x006c jmp usart3_rxc ; usart3 rx complete handler 0x006e jmp usart3_udre ; usart3,udr empty handler 0x0070 jmp usart3_txc ; usart3 tx complete handler ; 0x0072 reset: ldi r16, high(ramend) ; main program start 0x0073 out sph,r16 ; set stack pointer to top of ram 0x0074 ldi r16, low(ramend) 0x0075 out spl,r16 0x0076 sei ; enable interrupts 0x0077 73 atmega640/1280/1281/2560/2561 2549k?avr?01/07 w hen the bootrst fuse is unprogrammed, the boot section size set to 8k bytes and the ivsel bit in the mcucr register is set before any inte rrupts are enabled, the most typical and general program setup for the reset and interrupt vector addresses is: address labels code comments 0x00000 reset: ldi r16,high(ramend) ; main program start 0x00001 out sph,r16 ; set stack pointer to top of ram 0x00002 ldi r16,low(ramend) 0x00003 out spl,r16 0x00004 sei ; enable interrupts 0x00005 74 atmega640/1280/1281/2560/2561 2549k?avr?01/07 w hen the bootrst fuse is programmed, the boot section size set to 8k bytes and the ivsel bit in the mcucr register is set befo re any interrupts are enabled, the most typ- ical and general program setup for the reset and interrupt vector addresses is: address labels code comments ; .org 0x1f000 0x1f000 jmp reset ; reset handler 0x1f002 jmp ext_int0 ; irq0 handler 0x1f004 jmp ext_int1 ; irq1 handler ... ... ... ; 0x1f070 jmp usart3_txc ; usart3 tx complete handler ; 0x1f072 reset: ldi r16,high(ramend) ; main program start 0x1f073 out sph,r16 ; set stack pointer to top of ram 0x1f074 ldi r16,low(ramend) 0x1f075 out spl,r16 0x1f076 sei ; enable interrupts 0x1fo77 76 atmega640/1280/1281/2560/2561 2549k?avr?01/07 register description mcucr ? mcu control register ? bit 1 ? ivsel: interrupt vector select w hen the ivsel bit is cleared (z ero), the interrupt ve ctors are placed at the start of the flash memory. w hen this bit is set (one), the interrupt vectors are moved to the begin- ning of the boot loader section of the flash. the actual address of the start of the boot flash section is determined by the bootsz fuses. refer to the section ?memory pro- gramming? on page 342 for details. to avoid unintentional changes of interrupt vector tables, a special write procedure must be followed to ch ange the ivsel bit (see ?moving interrupts between application and boot section? on page 74): 1. w rite the interrupt vector change enable (ivce) bit to one. 2. w ithin four cycles, write the desired va lue to ivsel while writing a zero to ivce. interrupts will automatically be disabled while this sequence is executed. interrupts are disabled in the cycle ivce is set, and they remain disabled until after the instruction fol- lowing the write to ivsel. if ivsel is not written, interrupts remain disabled for four cycles. the i-bit in the status register is unaffected by the automatic disabling. n ote: if interrupt vectors are placed in the boot loader section and boot lock bit blb02 is pro- grammed, interrupts are disabled while executing from the application section. if interrupt vectors are placed in the applicat ion section and boot lock bit blb12 is pro- gramed, interrupts are disabled while executin g from the boot loader section. refer to the section ?memory programming? on page 342 for details on boot lock bits. ? bit 0 ? ivce: interrupt vector change enable the ivce bit must be written to logic one to enable change of the ivsel bit. ivce is cleared by hardware four cycles after it is written or when ivsel is written. setting the ivce bit will disable interrupts, as explained in the ivsel description. bit 76543210 0x35 (0x55) jtd ? ? pud ? ? ivsel ivce mcucr read/ w rite r/ w rrr/ w rrr/ w r/ w initial value 0 0 0 0 0 0 0 0 77 atmega640/1280/1281/2560/2561 2549k?avr?01/07 external interrupts the external interrupts are triggered by the i n t7:0 pin or any of the pci n t23:0 pins. observe that, if enabled, the inte rrupts will trigger even if the i n t7:0 or pci n t23:0 pins are configured as outputs. this feature provides a way of generating a software interrupt. the pin change interrupt pci2 will trigger if any enabled pci n t23:16 pin toggles, pin change interrupt pci1 if any enabled pci n t15:8 toggles and pin change interrupts pci0 will trigger if any enabled pci n t7:0 pin toggles. pcmsk2, pcmsk1 and pcmsk0 registers control which pins contribute to the pin change interrupts. pin change inter- rupts on pci n t23 :0 are detected asynchronously. this implies that these interrupts can be used for waking the part also from sleep modes other than idle mode. the external interrupts can be triggered by a falling or rising edge or a low level. this is set up as indicated in the specification for the external interrupt control registers ? eicra (i n t3:0) and eicrb (i n t7:4). w hen the external interrupt is enabled and is con- figured as level triggered, the interrupt will trigger as long as the pin is held low. n ote that recognition of falling or rising edge inte rrupts on i n t7:4 requires the presence of an i/o clock, described in ?overview? on page 37. low level interrupts and the edge inter- rupt on i n t3:0 are detected asynchronously. this implies that these interrupts can be used for waking the part also from sleep modes other than idle mode. the i/o clock is halted in all sleep modes except idle mode. n ote that if a level triggered interrupt is used for wake-up from power-down, the required level must be held long enough for the mcu to co mplete the wake-up to trigger the level interrupt. if the level disappears before the end of the start-up time, the mcu will still wake up, but no interrupt will be generated. the start-up time is defined by the sut and cksel fuses as descr ibed in ?system clock and clock options? on page 37. pin change interrupt timing an example of timing of a pin change interrupt is shown in figure 31. figure 31. n ormal pin change interrupt. clk pcint(n) pin_lat pin_sync pcint_in_(n) pcint_syn pcint_setflag pcif pcint(0) pin_sync pcint_syn pin_lat d q le pcint_setflag pcif clk clk pcint(0) in pcmsk(x) pcint_in_(0) 0 x 78 atmega640/1280/1281/2560/2561 2549k?avr?01/07 register description eicra ? external interrupt control register a the external interrupt control register a contains control bits for interrupt sense control. ? bits 7:0 ? isc31, isc30 ? isc00, isc00: external interrupt 3 - 0 sense control bits the external interrupts 3 - 0 are activated by the external pins i n t3:0 if the sreg i-flag and the corresponding interrupt mask in the eimsk is set. the level and edges on the external pins that activate the interrupts are defined in table 34. edges on i n t3:0 are registered asynchronously. pulses on i n t3:0 pins wider than the minimum pulse width given in table 35 will ge nerate an interrupt. shorter pulses are not guaranteed to gener- ate an interrupt. if low level in terrupt is selected, the low le vel must be held until the completion of the currently executing instruction to generate an interrupt. if enabled, a level triggered interrupt will gen erate an interrupt request as long as the pin is held low. w hen changing the iscn bit, an interrupt can occur. therefore, it is recommended to first disable i n tn by clearing its interrupt enable bit in the eimsk register. then, the iscn bit can be changed. finally, the i n tn interrupt flag should be cleared by writing a logical one to its interrupt flag bit (i n tfn) in the eifr register before the interrupt is re- enabled. n ote: 1. n = 3, 2, 1or 0. w hen changing the iscn1/iscn0 bits, the interrupt must be disabled by clearing its interrupt enable bit in the eimsk register. otherwise an interrupt can occur when the bits are changed. bit 76543210 (0x69) isc31 isc30 isc21 isc20 isc11 isc10 isc01 isc00 eicra read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 table 34. interrupt sense control (1) iscn1 iscn0 description 0 0 the low level of i n tn generates an interrupt request. 0 1 any edge of i n tn generates asynchronously an interrupt request. 1 0 the falling edge of i n tn generates asynchronously an interrupt request. 1 1 the rising edge of i n tn generates asynchronously an interrupt request. table 35. asynchronous external interrupt characteristics symbol parameter condition min typ max units t i n t minimum pulse width for asynchronous external interrupt 50 ns 79 atmega640/1280/1281/2560/2561 2549k?avr?01/07 eicrb ? external interrupt control register b ? bits 7:0 ? isc71, isc70 - isc41, isc40: external interrupt 7 - 4 sense control bits the external interrupts 7 - 4 are activated by the external pins i n t7:4 if the sreg i-flag and the corresponding interrupt mask in the eimsk is set. the level and edges on the external pins that activate the interrupts are defined in table 36. the value on the i n t7:4 pins are sampled before detecting edges. if edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. shorter pulses are not guaranteed to generate an interrupt. observe that cpu clock frequency can be lower than the xtal frequency if the xtal divider is enabled. if low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an in terrupt. if enabled, a level trig gered interrupt will generate an interrupt request as long as the pin is held low. n ote: 1. n = 7, 6, 5 or 4. w hen changing the iscn1/iscn0 bits, the interrupt must be disabled by clearing its interrupt enable bit in the eimsk register. otherwise an interrupt can occur when the bits are changed. eimsk ? external interrupt mask register ? bits 7:0 ? int7:0: external interrupt request 7 - 0 enable w hen an i n t7:0 bit is written to one and the i-bit in the status register (sreg) is set (one), the corresponding external pin interrupt is enabled. the interrupt sense control bits in the external interrupt control registers ? eicra and eicrb ? defines whether the external interrupt is activated on rising or falling edge or level sensed. activity on any of these pins will trigger an in terrupt request even if the pin is enabled as an output. this provides a way of generating a software interrupt. bit 76543210 (0x6a) isc71 isc70 isc61 isc60 isc51 isc50 isc41 isc40 eicrb read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 table 36. interrupt sense control (1) iscn1 iscn0 description 0 0 the low level of i n tn generates an interrupt request. 0 1 any logical change on i n tn generates an interrupt request 10 the falling edge between two samples of i n tn generates an interrupt request. 11 the rising edge between two samples of i n tn generates an interrupt request. bit 76543210 0x1d (0x3d) int7 int6 int5 int4 int3 int2 int1 int0 eimsk read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 80 atmega640/1280/1281/2560/2561 2549k?avr?01/07 eifr ? external interrupt flag register ? bits 7:0 ? intf7:0: external interrupt flags 7 - 0 w hen an edge or logic change on the i n t7:0 pin triggers an interrupt request, i n tf7:0 becomes set (one). if the i-bit in sreg and the corresponding interrupt enable bit, i n t7:0 in eimsk, are set (one), the mcu will jump to the interrup t vector. the flag is cleared when the interrupt routine is execut ed. alternatively, the flag can be cleared by writing a logical one to it. these flags are always cleared when i n t7:0 are configured as level interrupt. n ote that when entering sleep mode with the i n t3:0 interrupts disabled, the input buffers on these pins will be disabled. this may ca use a logic ch ange in inter- nal signals which will set the i n tf3:0 flags. see ?digital input enable and sleep modes? on page 87 for more information. pcicr ? pin change interrupt control register ? bit 2 ? pcie2: pin change interrupt enable 1 w hen the pcie2 bit is set (one) and the i-bit in the status register (sreg) is set (one), pin change interrupt 2 is enabled. any change on any enabled pci n t23:16 pin will cause an interrupt. the corresponding interr upt of pin change interrupt request is exe- cuted from the pci2 interrupt vector. pci n t23:16 pins are enabled individually by the pcmsk2 register. ? bit 1 ? pcie1: pin change interrupt enable 1 w hen the pcie1 bit is set (one) and the i-bit in the status register (sreg) is set (one), pin change interrupt 1 is enabled. any change on any enabled pci n t15:8 pin will cause an interrupt. the corresponding interrupt of pin change interrupt request is executed from the pci1 interrupt vector. pci n t15:8 pins are enabled individually by the pcmsk1 register. ? bit 0 ? pcie0: pin change interrupt enable 0 w hen the pcie0 bit is set (one) and the i-bit in the status register (sreg) is set (one), pin change interrupt 0 is enabled. any change on any enabled pci n t7:0 pin will cause an interrupt. the corresponding interrupt of pin change interrupt request is executed from the pci0 interrupt vector. pci n t7:0 pins are enabled individually by the pcmsk0 register. bit 76543210 0x1c (0x3c) intf7 intf6 intf5 intf4 intf3 intf2 intf1 iintf0 eifr read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 (0x68) ? ? ? ? ? pcie2 pcie1 pcie0 pcicr read/ w riterrrrrr/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 81 atmega640/1280/1281/2560/2561 2549k?avr?01/07 pcifr ? pin change interrupt flag register ? bit 2 ? pcif2: pin change interrupt flag 1 w hen a logic change on any pci n t23:16 pin triggers an interrupt request, pcif2 becomes set (one). if the i-bit in sreg and the pcie2 bit in pcicr are set (one), the mcu will jump to the correspondi ng interrupt vector. the flag is cleared when the inter- rupt routine is executed. alternatively, the fl ag can be cleared by writing a logical one to it. ? bit 1 ? pcif1: pin change interrupt flag 1 w hen a logic change on any pci n t15:8 pin triggers an interrupt request, pcif1 becomes set (one). if the i-bit in sreg and the pcie1 bit in pcicr are set (one), the mcu will jump to the correspondi ng interrupt vector. the flag is cleared when the inter- rupt routine is executed. alternatively, the fl ag can be cleared by writing a logical one to it. ? bit 0 ? pcif0: pin change interrupt flag 0 w hen a logic change on any pci n t7:0 pin triggers an interrupt request, pcif0 becomes set (one). if the i-bit in sreg and the pcie0 bit in pcicr are set (one), the mcu will jump to the correspondi ng interrupt vector. the flag is cleared when the inter- rupt routine is executed. alternatively, the fl ag can be cleared by writing a logical one to it. pcmsk2 ? pin change mask register 2 ? bit 7:0 ? pcint23:16: pin change enable mask 23:16 each pci n t23:16-bit selects whether pin change interrupt is enabled on the corre- sponding i/o pin. if pci n t23:16 is set and the pcie2 bit in pcicr is set, pin change interrupt is enabled on the corresponding i/o pin. if pci n t23:16 is cleared, pin change interrupt on the corresponding i/o pin is disabled. pcmsk1 ? pin change mask register 1 ? bit 7:0 ? pcint15:8: pin change enable mask 15:8 each pci n t15:8-bit selects whether pin change interrupt is enabled on the correspond- ing i/o pin. if pci n t15:8 is set and the pcie1 bit in eimsk is set, pin change interrupt is enabled on the corresponding i/o pin. if pci n t15:8 is cleared, pin change interrupt on the corresponding i/o pin is disabled. bit 76543210 0x1b (0x3b) ? ? ? ? ? pcif2 pcif1 pcif0 pcifr read/ w riterrrrrr/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 (0x6d) pcint23 pcint22 pcint21 pcint20 pcint19 pcint18 pcint17 pcint16 pcmsk2 read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 (0x6c) pcint15 pcint14 pcint13 pcint12 pcint11 pcint10 pcint9 pcint8 pcmsk1 read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 82 atmega640/1280/1281/2560/2561 2549k?avr?01/07 pcmsk0 ? pin change mask register 0 ? bit 7:0 ? pcint7:0: pin change enable mask 7:0 each pci n t7:0 bit selects whether pin change interrupt is enabled on the correspond- ing i/o pin. if pci n t7:0 is set and the pcie0 bit in pcicr is set, pin change interrupt is enabled on the corresponding i/o pin. if pci n t7:0 is cleared, pin change interrupt on the corresponding i/o pin is disabled. bit 76543210 (0x6b) pcint7 pcint6 pcint5 pcint4 pcint3 pcint2 pcint1 pcint0 pcmsk0 read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 83 atmega640/1280/1281/2560/2561 2549k?avr?01/07 i/o-ports introduction all avr ports have true read-modify- w rite functionality when used as general digital i/o ports. this means that the direction of one port pin can be changed without uninten- tionally changing the direction of any other pin with the sbi and cbi instructions. the same applies when changing drive value (if c onfigured as output) or enabling/disabling of pull-up resistors (if configured as input). each output buffer has symmetrical drive characteristics with both high sink and source capability. the pin dr iver is strong enough to drive led displays directly. all port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. all i/o pins have protection diodes to both v cc and ground as indicated in figure 32. refer to ?electrical characteristics? on page 374 for a complete list of parameters. figure 32. i/o pin equivalent schematic all registers and bit references in this section are written in general form. a lower case ?x? represents the numbering letter for the port, and a lower case ?n? represents the bit number. however, when using the register or bit defines in a program, the precise form must be used. for example, portb3 for bit no. 3 in port b, here documented generally as portxn. the physical i/o registers and bit locations are listed in ?table 70 and table 71 relates the alternate functions of port l to the overriding signals shown in fig- ure 36 on page 89.? on page 114. three i/o memory address locations are allocated for each port, one each for the data register ? portx, data direction regist er ? ddrx, and the port input pins ? pi n x. the port input pins i/o location is read only, while the data register and the data direction register are read/write. however, writing a logic one to a bit in the pi n x register, will result in a toggle in the corresponding bit in the data register. in addition, the pull-up disable ? pud bit in mcucr disables the pull- up function for all pins in all ports when set. using the i/o port as general dig ital i/o is described in ?ports as general digital i/o? on page 84. most port pins are multiplexed with alternate functions for the peripheral fea- tures on the device. how each alternate function interferes with the port pin is described in ?alternate port functions? on page 89. refer to the individual module sections for a full description of the alternate functions. c pin logic r pu see figure "general digital i/o" for details pxn 84 atmega640/1280/1281/2560/2561 2549k?avr?01/07 n ote that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital i/o. ports as general digital i/o the ports are bi-directional i/o ports with optional internal pull-ups. figure 33 shows a functional description of one i/o-port pin, here generically called pxn. figure 33. general digital i/o (1) n ote: 1. w rx, w px, w dx, rrx, rpx, and rdx are common to all pins within the same port. clk i/o , sleep, and pud are common to all ports. configuring the pin each port pin consists of three register bits: ddxn, portxn, and pi n xn. as shown in ?table 70 and table 71 relates the alternate f unctions of port l to the overriding signals shown in figure 36 on page 89.? on page 114, the ddxn bits are accessed at the ddrx i/o address, the portxn bits at the portx i/o address, and the pi n xn bits at the pi n x i/o address. the ddxn bit in the ddrx register selects the direction of this pin. if ddxn is written logic one, pxn is configured as an output pin. if ddxn is written logic zero, pxn is config- ured as an input pin. if portxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. to switch the pull-up resistor off, portxn has to be written logic zero or the pin has to be configured as an output pin. the port pins are tri-stated when reset condition becomes active, even if no clocks are running. if portxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). if portxn is written logic zero when the pin is configured as an out- put pin, the port pin is driven low (zero). clk rpx rrx rdx wdx pud synchronizer wdx: write ddrx wrx: write portx rrx: read portx register rpx: read portx pin pud: pullup disable clk i/o : i/o clock rdx: read ddrx d l q q reset reset q q d q q d clr portxn q q d clr ddxn pinxn data bus sleep sleep: sleep control pxn i/o wpx 0 1 wrx wpx: write pinx register 85 atmega640/1280/1281/2560/2561 2549k?avr?01/07 toggling the pin w riting a logic one to pi n xn toggles the value of portxn, independent on the value of ddrxn. n ote that the sbi instruction can be used to toggle one single bit in a port. switching between input and output w hen switching between tri-state ({ddxn, portxn} = 0b00) and output high ({ddxn, portxn} = 0b11), an intermed iate state with either pull-up enabled {ddx n, portxn} = 0b01) or output low ({ddxn, portxn} = 0b10) must occur. n ormally, the pull-up enabled state is fully acceptable, as a high -impedant environment will not notice the dif- ference between a strong high driver and a pull-up. if this is not the case, the pud bit in the mcucr register can be set to di sable all pull-ups in all ports. switching between input with pull-up and output low generates the same problem. the user must use either the tri-state ({ddxn, portxn} = 0b00) or the output high state ({ddxn, portxn} = 0b11) as an intermediate step. table 37 summarizes the control signals for the pin value. reading the pin value independent of the setting of data direction bit ddxn, the port pin can be read through the pi n xn register bit. as shown in figure 33, the pi n xn register bit and the preceding latch constitute a synchronizer. this is needed to avoid metastability if the physical pin changes value near the edge of the internal cl ock, but it also introduces a delay. figure 34 shows a timing diagram of the synchroni zation when reading an externally applied pin value. the maximum and minimum propagation delays are denoted t pd,max and t pd,min respectively. table 37. port pin configurations ddxn portxn pud (in mcucr) i/o pull-up comment 0 0 x input n o tri-state (hi-z) 0 1 0 input yes pxn will source current if ext. pulled low. 011 input n o tri-state (hi-z) 1 0 x output n o output low (sink) 1 1 x output n o output high (source) 86 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 34. synchronization when reading an externally applied pin value consider the clock period starting shortly afte r the first falling edge of the system clock. the latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the ?sy n c latch? signal. the signal value is latched when the system clock goes low. it is clocked into the pi n xn register at the suc- ceeding positive clock edge. as indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between ? and 1? system clock period depending upon the time of assertion. w hen reading back a software assigned pin value, a nop instruction must be inserted as indicated in figure 35. the out instruction sets the ?sy n c latch? signal at the positive edge of the clock. in this case, the delay tpd through the synchronizer is 1 system clock period. figure 35. synchronization when reading a software assigned pin value the following code example shows how to set port b pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. the xxx in r17, pinx 0x00 0xff instructions sync latch pinxn r17 xxx system clk t pd, max t pd, min out portx, r16 nop in r17, pinx 0xff 0x00 0xff system clk r16 instructions sync latch pinxn r17 t pd 87 atmega640/1280/1281/2560/2561 2549k?avr?01/07 resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. n ote: 1. for the assembly program, two temporar y registers are used to minimize the time from pull-ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefini ng bits 0 and 1 as strong high drivers. digital input enable and sleep modes as shown in figure 33, the digital input si gnal can be clamped to ground at the input of the schmitt-trigger. the signal denoted sleep in the figure, is set by the mcu sleep controller in power-down mode, power-save mode, and standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to v cc /2. sleep is overridden for port pins enabled as external interrup t pins. if the external inter- rupt request is not enabled, sleep is active also for these pins. sleep is also overridden by various other alternate functions as described in ?alternate port func- tions? on page 89. if a logic high level (?one?) is present on an asynchronous external interrupt pin config- ured as ?interrupt on rising edge, falling edge, or any logic change on pin? while the external interrupt is not enabled, the corresponding exte rnal interrupt flag will be set when resuming from the above mentioned sle ep mode, as the clamping in these sleep mode produces the requested logic change. assembly code example (1) ... ; define pull-ups and set outputs high ; define directions for port pins ldi r16,(1< 89 atmega640/1280/1281/2560/2561 2549k?avr?01/07 alternate port functions most port pins have alternate functions in addition to being general digital i/os. figure 36 shows how the port pin control signals fr om the simplified figure 33 can be overrid- den by alternate functions. the overriding signals may not be present in all port pins, but the figure serves as a generic description app licable to all port pins in the avr micro- controller family. figure 36. alternate port functions (1) n ote: 1. w rx, w px, w dx, rrx, rpx, and rdx are common to all pins within the same port. clk i/o , sleep, and pud are common to all ports. all other signals are unique for each pin. clk rpx rrx wrx rdx wdx pud synchronizer wdx: write ddrx wrx: write portx rrx: read portx register rpx: read portx pin pud: pullup disable clk i/o : i/o clock rdx: read ddrx d l q q set clr 0 1 0 1 0 1 dixn aioxn dieoexn pvovxn pvoexn ddovxn ddoexn puoexn puovxn puoexn: pxn pull-up override enable puovxn: pxn pull-up override value ddoexn: pxn data direction override enable ddovxn: pxn data direction override value pvoexn: pxn port value override enable pvovxn: pxn port value override value dixn: digital input pin n on portx aioxn: analog input/output pin n on portx reset reset q q d clr q q d clr q q d clr pinxn portxn ddxn data b u s 0 1 dieovxn sleep dieoexn: pxn digital input-enable override enable dieovxn: pxn digital input-enable override value sleep: sleep control pxn i/o 0 1 ptoexn ptoexn: pxn, port toggle override enable wpx: write pinx wpx 90 atmega640/1280/1281/2560/2561 2549k?avr?01/07 table 38 summarizes the function of the overriding signals. the pin and port indexes from figure 36 are not shown in the succeed ing tables. the overriding signals are gen- erated internally in the modules having the alternate function. the following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternat e function. refer to the alternate function description for further details. table 38. generic description of overriding signals for alternate functions signal name full name description puoe pull-up override enable if this signal is set, the pull-up enable is controlled by the puov signal. if this signal is cleared, the pull-up is enabled when {ddxn, portxn, pud} = 0b010. puov pull-up override value if puoe is set, the pull-up is enabled/disabled when puov is set/cleared, regardless of the setting of the ddxn, portxn, and pud register bits. ddoe data direction override enable if this signal is set, the output driver enable is controlled by the ddov signal. if this signal is cleared, the output driver is enabled by the ddxn register bit. ddov data direction override value if ddoe is set, the output driver is enabled/disabled when ddov is set/cleared, regardless of the setting of the ddxn register bit. pvoe port value override enable if this signal is set and the output driver is enabled, the port value is controlled by the pvov signal. if pvoe is cleared, and the output driver is enabled, the port value is controlled by the portxn register bit. pvov port value override value if pvoe is set, the port value is set to pvov, regardless of the setting of the portxn register bit. ptoe port toggle override enable if ptoe is set, the portxn register bit is inverted. dieoe digital input enable override enable if this bit is set, the digital input enable is controlled by the dieov signal. if this signal is cleared, the digital input enable is determined by mcu state ( n ormal mode, sleep mode). dieov digital input enable override value if dieoe is set, the digital input is enabled/disabled when dieov is set/cleared, regardless of the mcu state ( n ormal mode, sleep mode). di digital input this is the digital input to alternate functions. in the figure, the signal is connected to the output of the schmitt trigger but before the synchronizer. unless the digital input is used as a clock source, the module with the alternate function will use its own synchronizer. aio analog input/output this is the analog input/output to/from alternate functions. the signal is connected directly to the pad, and can be used bi-directionally. 91 atmega640/1280/1281/2560/2561 2549k?avr?01/07 alternate functions of port a the port a has an alternate function as the address low byte and data lines for the external memory interface. table 40 and table 41 relates the alternate functions of port a to the overriding signals shown in figure 36 on page 89. n ote: 1. ada is short for address active and represents the time when address is output. see ?external memory interface? on page 26 for details. table 39. port a pins alternate functions port pin alternate function pa7 ad7 (external memory interface address and data bit 7) pa6 ad6 (external memory interface address and data bit 6) pa5 ad5 (external memory interface address and data bit 5) pa4 ad4 (external memory interface address and data bit 4) pa3 ad3 (external memory interface address and data bit 3) pa2 ad2 (external memory interface address and data bit 2) pa1 ad1 (external memory interface address and data bit 1) pa0 ad0 (external memory interface address and data bit 0) table 40. overriding signals for alternate functions in pa7:pa4 signal name pa7/ad7 pa6/ad6 pa5/ad5 pa4/ad4 puoe sre sre sre sre puov ~( w r | ada (1) ) ? porta7 ? pud ~( w r | ada) ? porta6 ? pud ~( w r | ada) ? porta5 ? pud ~( w r | ada) ? porta4 ? pud ddoe sre sre sre sre ddov w r | ada w r | ada w r | ada w r | ada pvoe sre sre sre sre pvov a7 ? ada | d7 output ? w r a6 ? ada | d6 output ? w r a5 ? ada | d5 output ? w r a4 ? ada | d4 output ? w r dieoe 0 0 0 0 dieov 0 0 0 0 di d7 i n put d6 i n put d5 i n put d4 i n put aio ? ? ? ? 92 atmega640/1280/1281/2560/2561 2549k?avr?01/07 alternate functions of port b the port b pins with alternate functions are shown in table 42. the alternate pin configuration is as follows: ? oc0a/oc1c/pcint7, bit 7 oc0a, output compare match a output: the pb7 pin can serve as an external output for the timer/counter0 output compare. the pin has to be configured as an output (ddb7 set ?one?) to serve this function. the oc0a pin is also the output pin for the p w m mode timer function. oc1c, output compare match c output: the pb7 pin can serve as an external output for the timer/counter1 output compare c. the pin has to be configured as an output (ddb7 set (one)) to serve this function. the oc1c pin is also the output pin for the p w m mode timer function. table 41. overriding signals for alternate functions in pa3:pa0 signal name pa3/ad3 pa2/ad2 pa1/ad1 pa0/ad0 puoe sre sre sre sre puov ~( w r | ada) ? porta3 ? pud ~( w r | ada) ? porta2 ? pud ~( w r | ada) ? porta1 ? pud ~( w r | ada) ? porta0 ? pud ddoe sre sre sre sre ddov w r | ada w r | ada w r | ada w r | ada pvoe sre sre sre sre pvov a3 ? ada | d3 output ? w r a2? ada | d2 output ? w r a1 ? ada | d1 output ? w r a0 ? ada | d0 output ? w r dieoe 0 0 0 0 dieov 0 0 0 0 di d3 i n put d2 i n put d1 i n put d0 i n put aio ? ? ? ? table 42. port b pins alternate functions port pin alternate functions pb7 oc0a/oc1c/pci n t7 (output compare and p w m output a for timer/counter0, output compare and p w m output c for timer/counter1 or pin change interrupt 7) pb6 oc1b/pci n t6 (output compare and p w m output b for time r/counter1 or pin change interrupt 6) pb5 oc1a/pci n t5 (output compare and p w m output a for time r/counter1 or pin change interrupt 5) pb4 oc2a/pci n t4 (output compare and p w m output a for time r/counter2 or pin change interrupt 4) pb3 miso/pci n t3 (spi bus master input/slave output or pin change interrupt 3) pb2 mosi/pci n t2 (spi bus master output/slave input or pin change interrupt 2) pb1 sck/pci n t1 (spi bus serial clock or pin change interrupt 1) pb0 ss /pci n t0 (spi slave select input or pin change interrupt 0) 93 atmega640/1280/1281/2560/2561 2549k?avr?01/07 pci n t7, pin change interrupt source 7: the pb7 pin can serve as an external interrupt source. ? oc1b/pcint6, bit 6 oc1b, output compare match b output: the pb6 pin can serve as an external output for the timer/counter1 output compare b. the pin has to be configured as an output (ddb6 set (one)) to serve this function. the oc1b pin is also the output pin for the p w m mode timer function. pci n t6, pin change interrupt source 6: the pb6 pin can serve as an external interrupt source. ? oc1a/pcint5, bit 5 oc1a, output compare match a output: the pb5 pin can serve as an external output for the timer/counter1 output compare a. the pin has to be configured as an output (ddb5 set (one)) to serve this function. the oc1a pin is also the output pin for the p w m mode timer function. pci n t5, pin change interrupt source 5: the pb5 pin can serve as an external interrupt source. ? oc2a/pcint4, bit 4 oc2a, output compare match output: the pb4 pin can serve as an external output for the timer/counter2 output compare. the pin has to be configured as an output (ddb4 set (one)) to serve this function. the oc2a pin is also the output pin for the p w m mode timer function. pci n t4, pin change interrupt source 4: the pb4 pin can serve as an external interrupt source. ? miso/pcint3 ? port b, bit 3 miso: master data input, slave data output pin for spi channel. w hen the spi is enabled as a master, this pin is configured as an input regardless of the setting of ddb3. w hen the spi is enabled as a slave, the da ta direction of this pin is controlled by ddb3. w hen the pin is forced to be an input, the pull-up can still be controlled by the portb3 bit. pci n t3, pin change interrupt source 3: the pb3 pin can serve as an external interrupt source. ? mosi/pcint2 ? port b, bit 2 mosi: spi master data output, slave data input for spi channel. w hen the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddb2. w hen the spi is enabled as a master, the da ta direction of this pin is controlled by ddb2. w hen the pin is forced to be an input, the pull-up can still be controlled by the portb2 bit. pci n t2, pin change interrupt source 2: the pb2 pin can serve as an external interrupt source. ? sck/pcint1 ? port b, bit 1 sck: master clock output, slave clock input pin for spi channel. w hen the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddb1. 94 atmega640/1280/1281/2560/2561 2549k?avr?01/07 w hen the spi0 is enabled as a master, the data direction of this pin is controlled by ddb1. w hen the pin is forced to be an input, the pull-up can still be controlled by the portb1 bit. pci n t1, pin change interrupt source 1: the pb1 pin can serve as an external interrupt source. ?ss /pcint0 ? port b, bit 0 ss : slave port select input. w hen the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddb0 . as a slave, the spi is activated when this pin is driven low. w hen the spi is enabled as a master, the data direction of this pin is controlled by ddb0. w hen the pin is forced to be an input, the pull-up can still be con- trolled by the portb0 bit. table 43 and table 44 relate the alternate functions of port b to the overriding signals shown in figure 36 on page 89. spi mstr i n put and spi slave ou tput constitute the miso signal, while mosi is divide d into spi mstr output and spi slave i n put. pci n t0, pin change interrupt source 0: the pb0 pin can serve as an external interrupt source. table 43. overriding signals for alternate functions in pb7:pb4 signal name pb7/oc0a/oc1c pb6/oc1b pb5/oc1a pb4/oc2a puoe 0 0 0 0 puov 0 0 0 0 ddoe 0 0 0 0 ddov 0 0 0 0 pvoe oc0/oc1c e n able oc1b e n able oc1a e n able oc2a e n able pvov oc0/oc1c oc1b oc1a oc2a dieoe pci n t7 ? pcie0 pci n t6 ? pcie0 pci n t5 ? pcie0 pci n t4 ? pcie0 dieov 1 1 1 1 di pci n t7 i n put pci n t6 i n put pci n t5 i n put pci n t4 i n put aio ? ? ? ? 95 atmega640/1280/1281/2560/2561 2549k?avr?01/07 alternate functions of port c the port c alternate function is as follows: table 46 and table 47 relate the alternate functions of port c to the overriding signals shown in figure 36 on page 89. table 44. overriding signals for alternate functions in pb3:pb0 signal name pb3/miso pb2/mosi pb1/sck pb0/ss puoe spe ? mstr spe ? mstr spe ? mstr spe ? mstr puov portb3 ? pud portb2 ? pud portb1 ? pud portb0 ? pud ddoe spe ? mstr spe ? mstr spe ? mstr spe ? mstr ddov 0 0 0 0 pvoe spe ? mstr spe ? mstr spe ? mstr 0 pvov spi slave output spi mstr output sck output 0 dieoe pci n t3 ? pcie0 pci n t2 ? pcie0 pci n t1 ? pcie0 pci n t0 ? pcie0 dieov 1 1 1 1 di spi mstr i n put pci n t3 i n put spi slave i n put pci n t2 i n put sck i n put pci n t1 i n put spi ss pci n t0 i n put aio ? ? ? ? table 45. port c pins alternate functions port pin alternate function pc7 a15(external memory interface address bit 15) pc6 a14(external memory interface address bit 14) pc5 a13(external memory interface address bit 13) pc4 a12(external memory interface address bit 12) pc3 a11(external memory interface address bit 11) pc2 a10(external memory interface address bit 10) pc1 a9(external memory interface address bit 9) pc0 a8(external memory interface address bit 8) 96 atmega640/1280/1281/2560/2561 2549k?avr?01/07 table 46. overriding signals for alternate functions in pc7:pc4 signal name pc7/a15 pc6/a14 pc5/a13 pc4/a12 puoe sre ? (xmm<1) sre ? (xmm<2) sre ? (xmm<3) sre ? (xmm<4) puov 0 0 0 0 ddoe sre ? (xmm<1) sre ? (xmm<2) sre ? (xmm<3) sre ? (xmm<4) ddov 1 1 1 1 pvoe sre ? (xmm<1) sre ? (xmm<2) sre ? (xmm<3) sre ? (xmm<4) pvov a15 a14 a13 a12 dieoe 0 0 0 0 dieov 0 0 0 0 di ? ? ? ? aio ? ? ? ? table 47. overriding signals for alternate functions in pc3:pc0 signal name pc3/a11 pc2/a10 pc1/a9 pc0/a8 puoe sre ? (xmm<5) sre ? (xmm<6) sre ? (xmm<7) sre ? (xmm<7) puov0000 ddoe sre ? (xmm<5) sre ? (xmm<6) sre ? (xmm<7) sre ? (xmm<7) ddov 1 1 1 1 pvoe sre ? (xmm<5) sre ? (xmm<6) sre ? (xmm<7) sre ? (xmm<7) pvov a11 a10 a9 a8 dieoe0000 dieov0000 di???? aio???? 97 atmega640/1280/1281/2560/2561 2549k?avr?01/07 alternate functions of port d the port d pins with alternate functions are shown in table 48. the alternate pin configuration is as follows: ? t0 ? port d, bit 7 t0, timer/counter0 counter source. ? t1 ? port d, bit 6 t1, timer/counter1 counter source. ? xck1 ? port d, bit 5 xck1, usart1 external clock. the data direction register (ddd5) controls whether the clock is output (ddd5 se t) or input (ddd5 cleared). the xck1 pin is active only when the usart1 operates in synchronous mode. ? icp1 ? port d, bit 4 icp1 ? input capture pin 1: the pd4 pin can act as an input capture pin for timer/counter1. ? int3/txd1 ? port d, bit 3 i n t3, external interrupt source 3: the pd3 pi n can serve as an external interrupt source to the mcu. txd1, transmit data (data output pin for the usart1). w hen the usart1 transmitter is enabled, this pin is configured as an output regardless of the value of ddd3. ? int2/rxd1 ? port d, bit 2 i n t2, external interrupt source 2. the pd2 pin can serve as an external interrupt source to the mcu. rxd1, receive data (data input pin for the usart1). w hen the usart1 receiver is enabled this pin is configured as an input regardless of the value of ddd2. w hen the usart forces this pin to be an input, the pull-up can still be controlled by the portd2 bit. table 48. port d pins alternate functions port pin alternate function pd7 t0 (timer/counter0 clock input) pd6 t1 (timer/counter1 clock input) pd5 xck1 (usart1 external clock input/output) pd4 icp1 (timer/counter1 input capture trigger) pd3 i n t3/txd1 (external interrupt3 input or usart1 transmit pin) pd2 i n t2/rxd1 (external interrupt2 input or usart1 receive pin) pd1 i n t1/sda (external interrupt1 input or t w i serial data) pd0 i n t0/scl (external interrupt0 input or t w i serial clock) 98 atmega640/1280/1281/2560/2561 2549k?avr?01/07 ? int1/sda ? port d, bit 1 i n t1, external interrupt source 1. the pd1 pi n can serve as an external interrupt source to the mcu. sda, 2-wire serial interface data: w hen the t w e n bit in t w cr is set (one) to enable the 2-wire serial interface, pin pd1 is disconnected from the port and becomes the serial data i/o pin for the 2-wire serial interf ace. in this mode, there is a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation. ?int0/scl ? port d, bit 0 i n t0, external interrupt source 0. the pd0 pi n can serve as an external interrupt source to the mcu. scl, 2-wire serial interface clock: w hen the t w e n bit in t w cr is set (one) to enable the 2-wire serial interface, pin pd0 is disconnected from the port and becomes the serial clock i/o pin for the 2-wire serial interface. in this mode, there is a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation. table 49 and table 50 relates the alternate fu nctions of port d to the overriding signals shown in figure 36 on page 89. table 49. overriding signals for alternate functions pd7:pd4 signal name pd7/t0 pd 6/t1 pd5/xck1 pd4/icp1 puoe000 0 puov000 0 ddoe 0 0 xck1 output e n able 0 ddov 0 0 1 0 pvoe 0 0 xck1 output e n able 0 pvov 0 0 xck1 output 0 dieoe000 0 dieov000 0 di t0 i n put t1 i n put xck1 i n put icp1 i n put aio??? ? 99 atmega640/1280/1281/2560/2561 2549k?avr?01/07 n ote: 1. w hen enabled, the 2-wire serial interface enables slew-rate controls on the output pins pd0 and pd1. this is not shown in this table. in addition, spike filters are con- nected between the aio outputs shown in the port figure and the digital logic of the t w i module. alternate functions of port e the port e pins with alternate functions are shown in table 51. n ote: 1. only for atmega1281/2561 . for atmega640/1280/2560 these functions are placed on miso/mosi pins. ? int7/icp3/clko ? port e, bit 7 i n t7, external interrupt source 7: the pe7 pin can serve as an external interrupt source. icp3, input capture pin 3: the pe7 pi n can act as an input capture pin for timer/counter3. table 50. overriding signals for alternate functions in pd3:pd0 (1) signal name pd3/int3/txd1 pd2/int 2/rxd1 pd1/int1/sda pd0/int0/scl puoe txe n 1rxe n 1t w e n t w e n puov 0 portd2 ? pud portd1 ? pud portd0 ? pud ddoe txe n 1rxe n 1t w e n t w e n ddov 1 0 sda_out scl_out pvoe txe n 10 t w e n t w e n pvov txd1 0 0 0 dieoe i n t3 e n able i n t2 e n able i n t1 e n able i n t0 e n able dieov 1 1 1 1 di i n t3 i n put i n t2 i n put/rxd1 i n t1 i n put i n t0 i n put aio ? ? sda i n put scl i n put table 51. port e pins alternate functions port pin alternate function pe7 i n t7/icp3/clk0 (external interrupt 7 inpu t, timer/counter3 i nput capture trigger or divided system clock) pe6 i n t6/ t3 (external interrupt 6 inpu t or timer/count er3 clock input) pe5 i n t5/oc3c (external interrupt 5 input or output compare and p w m output c for timer/counter3) pe4 i n t4/oc3b (external interrupt4 input or output compare and p w m output b for timer/counter3) pe3 ai n 1/oc3a (analog comparator n egative input or output compare and p w m output a for timer/counter3) pe2 ai n 0/xck0 (analog comparator positive input or usart0 external clock input/output) pe1 pdo (1) /txd0 (programming data outp ut or usart0 transmit pin) pe0 pdi (1) /rxd0/pci n t8 (programming data input, usart0 receive pin or pin change interrupt 8) 100 atmega640/1280/1281/2560/2561 2549k?avr?01/07 clko - divided system clock: the divided s ystem clock can be output on the pe7 pin. the divided system clock will be output if t he ckout fuse is programmed, regardless of the porte7 and dde7 settings. it will also be output during reset. ? int6/t3 ? port e, bit 6 i n t6, external interrupt source 6: the pe6 pin can serve as an external interrupt source. t3, timer/counter3 counter source. ? int5/oc3c ? port e, bit 5 i n t5, external interrupt source 5: the pe 5 pin can serve as an external interrupt source. oc3c, output compare match c output: the pe5 pin can serve as an external output for the timer/counter3 output compare c. the pin has to be configured as an output (dde5 set ?one?) to serve this function. the oc3c pin is also the output pin for the p w m mode timer function. ? int4/oc3b ? port e, bit 4 i n t4, external interrupt source 4: the pe 4 pin can serve as an external interrupt source. oc3b, output compare match b output: the pe4 pin can serve as an external output for the timer/counter3 output compare b. the pin has to be configured as an output (dde4 set (one)) to serve this function. the oc3b pin is also the output pin for the p w m mode timer function. ? ain1/oc3a ? port e, bit 3 ai n 1 ? analog comparator n egative input. this pin is directly connected to the negative input of the analog comparator. oc3a, output compare match a output: the pe3 pin can serve as an external output for the timer/counter3 output compare a. the pin has to be configured as an output (dde3 set ?one?) to serve this function. the oc3a pin is also the output pin for the p w m mode timer function. ? ain0/xck0 ? port e, bit 2 ai n 0 ? analog comparator positive input. this pin is directly connected to the positive input of the analog comparator. xck0, usart0 external clock. the data di rection register (dde2) controls whether the clock is output (dde2 set) or input (d de2 cleared). the xck0 pin is active only when the usart0 operates in synchronous mode. ? pdo/txd0 ? port e, bit 1 pdo, spi serial programming data output. during serial program downloading, this pin is used as data output line for the atmega1281/2561. for atmega640/1280/2560 this function is placed on miso. txd0, usart0 transmit pin. 101 atmega640/1280/1281/2560/2561 2549k?avr?01/07 ? pdi/rxd0/pcint8 ? port e, bit 0 pdi, spi serial programming data input. duri ng serial program downloading, this pin is used as data input line for the atmega1281/2561. for atmega640/1280/2560 this function is placed on mosi. rxd0, usart0 receive pin. receive da ta (data input pin for the usart0). w hen the usart0 receiver is enabled this pin is conf igured as an input regardless of the value of ddre0. w hen the usart0 forces this pin to be an input, a logical one in porte0 will turn on the internal pull-up. pci n t8, pin change interrupt source 8: the pe0 pin can serve as an external interrupt source. table 52 and table 53 relates the alternate functions of port e to the overriding signals shown in figure 36 on page 89. table 52. overriding signals for alternate functions pe7:pe4 signal name pe7/int7/icp3 pe6 /int6/t3 pe5/int5/oc3c pe4/int4/oc3b puoe 0 0 0 0 puov 0 0 0 0 ddoe 0 0 0 0 ddov 0 0 0 0 pvoe 0 0 oc3c e n able oc3b e n able pvov 0 0 oc3c oc3b dieoe i n t7 e n able i n t6 e n able i n t5 e n able i n t4 e n able dieov 1 1 1 1 di i n t7 i n put/icp3 i n put i n t7 i n put/t3 i n put i n t5 i n put i n t4 i n put aio ? ? ? ? 102 atmega640/1280/1281/2560/2561 2549k?avr?01/07 n ote: 1. pdo/pdi only available at pe1/pe0 for atmega1281/2561 . table 53. overriding signals for alternate functions in pe3:pe0 signal name pe3/ain1/oc3a pe2/ain0/xck0 pe1/pdo (1) / txd0 pe0/pdi (1) / rxd0/pcint8 puoe 0 0 txe n 0rxe n 0 puov 0 0 0 porte0 ? pud ddoe 0 xck0 output e n able txe n 0rxe n 0 ddov 0 1 1 0 pvoe oc3b e n able xck0 output e n able txe n 00 pvov oc3b xck0 output txd0 0 dieoe 0 0 0 pci n t8 ? pcie1 dieov 0 0 0 1 di 0 xck0 i n put ? rxd0 pe0 0 0 0 pci n t8 i n put aio ai n 1 i n put ai n 0 i n put ? ? 103 atmega640/1280/1281/2560/2561 2549k?avr?01/07 alternate functions of port f the port f has an alternate function as analog input for the adc as shown in table 54. if some port f pins are configured as outputs, it is essential that these do not switch when a conversion is in progress. this might corrupt the result of the conversion. if the jtag interface is enabled, the pull-up resistors on pins pf7(tdi), pf5(tms), and pf4(tck) will be activated even if a reset occurs. ? tdi, adc7 ? port f, bit 7 adc7, analog to digital converter, channel 7 . tdi, jtag test data in: serial input data to be shifted in to the instruction register or data register (scan chains). w hen the jtag interface is enabled, this pin can not be used as an i/o pin. ? tdo, adc6 ? port f, bit 6 adc6, analog to digital converter, channel 6 . tdo, jtag test data out: serial output data from instruction register or data regis- ter. w hen the jtag interface is enabled, this pin can not be used as an i/o pin. the tdo pin is tri-stated unless tap states that shift out data are entered. ? tms, adc5 ? port f, bit 5 adc5, analog to digital converter, channel 5 . tms, jtag test mode select: this pin is used for navigating through the tap-controller state machine. w hen the jtag interface is enabled, this pin can not be used as an i/o pin. ? tck, adc4 ? port f, bit 4 adc4, analog to digital converter, channel 4 . tck, jtag test clock: jtag oper ation is synchronous to tck. w hen the jtag inter- face is enabled, this pin can not be used as an i/o pin. table 54. port f pins alternate functions port pin alternate function pf7 adc7/tdi (adc input channel 7 or jtag test data input) pf6 adc6/tdo (adc input channel 6 or jtag test data output) pf5 adc5/tms (adc input channel 5 or jtag test mode select) pf4 adc4/tck (adc input channel 4 or jtag test clock) pf3 adc3 (adc input channel 3) pf2 adc2 (adc input channel 2) pf1 adc1 (adc input channel 1) pf0 adc0 (adc input channel 0) 104 atmega640/1280/1281/2560/2561 2549k?avr?01/07 ? adc3 ? adc0 ? port f, bit 3:0 analog to digital converter, channel 3:0. table 55. overriding signals for alternate functions in pf7:pf4 signal name pf7/adc7/tdi pf6/adc6/td o pf5/adc5/tms pf4/adc4/tck puoe jtage n jtage n jtage n jtage n puov 1 0 1 1 ddoe jtage n jtage n jtage n jtage n ddov 0 shift_ir + shift_dr 00 pvoe 0 jtage n 00 pvov 0 tdo 0 0 dieoe jtage n jtage n jtage n jtage n dieov 0 0 0 0 di ? ? ? ? aio tdi/adc7 i n put adc6 i n put tms/adc5 i n put tck/adc4 i n put table 56. overriding signals for alternate functions in pf3:pf0 signal name pf3/adc3 pf 2/adc2 pf1/adc1 pf0/adc0 puoe0000 puov0000 ddoe0000 ddov0000 pvoe0000 pvov0000 dieoe0000 dieov0000 di???? aio adc3 i n put adc2 i n put adc1 i n put adc0 i n put 105 atmega640/1280/1281/2560/2561 2549k?avr?01/07 alternate functions of port g the port g alternate pin configuration is as follows: ? oc0b ? port g, bit 5 oc0b, output compare match b output: the pg5 pin can serve as an external output for the timer/counter0 output compare. the pin has to be configured as an output (ddg5 set) to serve this function. the oc0b pin is also the output pin for the p w m mode timer function. ? tosc1 ? port g, bit 4 tosc2, timer oscillator pin 1: w hen the as2 bit in assr is set (one) to enable asyn- chronous clocking of timer/counter2, pin pg4 is disconnected from the port, and becomes the input of the invert ing oscillator amplifie r. in this mode, a crystal oscillator is connected to this pin, and the pin can not be used as an i/o pin. ? tosc2 ? port g, bit 3 tosc2, timer oscillator pin 2: w hen the as2 bit in assr is set (one) to enable asyn- chronous clocking of timer/counter2, pin pg3 is disconnected from the port, and becomes the inverting output of the oscillator amplifier. in th is mode, a crystal oscillator is connected to this pin, and the pin can not be used as an i/o pin. ? ale ? port g, bit 2 ale is the external data memory address latch enable signal. ?rd ? port g, bit 1 rd is the external data memory read control strobe. ?wr ? port g, bit 0 w r is the external data memory write control strobe. table 58 and table 59 relates the alternate functions of port g to the overriding signals shown in figure 36 on page 89. table 57. port g pins alternate functions port pin alternate function pg5 oc0b (output compare and p w m output b for timer/counter0) pg4 tosc1 (rtc oscillator timer/counter2) pg3 tosc2 (rtc oscillator timer/counter2) pg2 ale (address latch enable to external memory) pg1 rd (read strobe to external memory) pg0 w r ( w rite strobe to external memory) 106 atmega640/1280/1281/2560/2561 2549k?avr?01/07 table 58. overriding signals for alternate functions in pg5:pg4 signal name ? ? pg5/oc0b pg4/tosc1 puoe ? ? ? as2 puov???0 ddoe ? ? ? as2 ddov???0 pvoe ? ? oc0b enable 0 pvov??oc0b0 ptoe???? dieoe ? ? ? as2 dieov ? ? ? exclk di???? aio???t/c2 osc i n put table 59. overriding signals for alternate functions in pg3:pg0 signal name pg3/tosc2 pg2/ale/a7 pg1/rd pg0/wr puoe as2 ? exclk sre sre sre puov0 000 ddoe as2 ? exclk sre sre sre ddov 0 1 1 1 pvoe 0 sre sre sre pvov 0 ale rd w r ptoe? ??? dieoe as2 ? exclk 000 dieov0 000 di? ??? aio t/c2 osc output ? ? ? 107 atmega640/1280/1281/2560/2561 2549k?avr?01/07 alternate functions of port h the port h alternate pin configuration is as follows: ? t4 ? port h, bit 7 t4, timer/counter4 counter source. ? oc2b ? port h, bit 6 oc2b, output compare match b output: the ph6 pin can serve as an external output for the timer/counter2 output compare b. the pin has to be configured as an output (ddh6 set) to serve this function. the oc2b pin is also the output pin for the p w m mode timer function. ? oc4c ? port h, bit 5 oc4c, output compare match c output: the ph5 pin can serve as an external output for the timer/counter4 output compare c. the pin has to be configured as an output (ddh5 set) to serve this function. the oc4c pin is also the output pin for the p w m mode timer function. ? oc4b ? port h, bit 4 oc4b, output compare match b output: the ph4 pin can serve as an external output for the timer/counter2 output compare b. the pin has to be configured as an output (ddh4 set) to serve this function. the oc4b pin is also the output pin for the p w m mode timer function. ? oc4a ? port h, bit 3 oc4c, output compare match a output: the ph3 pin can serve as an external output for the timer/counter4 output compare a. the pin has to be configured as an output (ddh3 set) to serve this function. the oc4a pin is also the output pin for the p w m mode timer function. ? xck2 ? port h, bit 2 xck2, usart2 external clock: the data directi on register (ddh2) controls whether the clock is output (ddh2 set) or input (ddh2 cleared). the xc2k pin is active only when the usart2 oper- ates in synchronous mode. ? txd2 ? port h, bit 1 txd2, usart2 transmit pin. table 60. port h pins alternate functions port pin alternate function ph7 t4 (timer/counter4 clock input) ph6 oc2b(output compare and p w m output b for timer/counter2) ph5 oc4c(output compare and p w m output c for timer/counter4) ph4 oc4b(output compare and p w m output b for timer/counter4) ph3 oc4a(output compare and p w m output a for timer/counter4) ph2 xck2 (usart2 external clock) ph1 txd2 (usart2 transmit pin) ph0 rxd2 (usart2 receive pin) 108 atmega640/1280/1281/2560/2561 2549k?avr?01/07 ? rxd2 ? port h, bit 0 rxd2, usart2 receive pin: receive data (data input pin for the usart2). w hen the usart2 receiver is enabled, this pin is co nfigured as an input regardless of the value of ddh0. w hen the usart2 forces this pin to be an input, a logical on in porth0 will turn on the internal pull-up. table 61. overriding signals for alternate functions in ph7:ph4 signal name ph7/t4 ph6/oc2b ph5/oc4c ph4/oc4b puoe0 000 puov0 000 ddoe 0 0 0 0 ddov 0 0 0 0 pvoe 0 oc2b e n able oc4c e n able oc4b e n able pvov 0 oc2b oc4c oc4b ptoe? ??? dieoe0 000 dieov0 000 di t4 i n put000 aio? ??? table 62. overriding signals for alternate functions in ph3:ph0 signal name ph3/oc4a ph2/xck2 ph1/txd2 ph0/rxd2 puoe 0 0 txe n 2rxe n 2 puov0 00porth0 ? pud ddoe 0 xck2 output e n able txe n 2rxe n 2 ddov 0 1 1 0 pvoe oc4a e n able xck2 output e n able txe n 20 pvov oc4a xck2 txd2 0 ptoe? ??? dieoe0 000 dieov0 000 di 0 xc2k i n put 0 rxd2 aio? ??? 109 atmega640/1280/1281/2560/2561 2549k?avr?01/07 alternate functions of port j the port j alternate pin configuration is as follows: ? pcint15:12 - port j, bit 6:3 pci n t15:12, pin change interrupt source 15:12. the pj6:3 pins can serve as external interrupt sources ? xck2/pcint11 - port j, bit 2 xck2, usart 2 external clock. the data direc tion register (ddj2) controls whether the clock is output (ddj2 set) or input (ddj2 cleared). the xck2 pin is active only when the usart2 operates in synchronous mode. pci n t11, pin change interrupt source 11. the pj2 pin can serve as external interrupt sources ? txd3/pcint10 - port j, bit 1 txd3, usart3 transmit pin pci n t10, pin change interrupt source 10. the pj1 pin can serve as external interrupt sources ? rxd3/pcint9 - port j, bit 0 rxd3, usart3 receive pin. receive data (data input pin for the usart3). w hen the usart3 receiver is enabled, this pin is co nfigured as an input regardless of the value of ddj0. w hen the usart3 forces this pin to be an input, a logical one in portj0 will turn on the internal pull-up. pci n t9, pin change interrupt source 9. the pj0 pin can serve as external interrupt sources table 64 and table 65 relates the alternate functions of port j to the overriding signals shown in figure 36 on page 89 table 63. port j pins alternate functions port pin alternate function pj7 ? pj6 pci n t15 (pin change interrupt 15) pj5 pci n t14 (pin change interrupt 14) pj4 pci n t13 (pin change interrupt 13) pj3 pci n t12 (pin change interrupt 12) pj2 xck3/pci n t11 (usart3 external clock or pin change interrupt 11) pj1 txd3/pci n t10 (usart3 transmit pin or pin change interrupt 10) pj0 rxd3/pci n t9 (usart3 receive pin or pin change interrupt 9) 110 atmega640/1280/1281/2560/2561 2549k?avr?01/07 table 64. overriding signals for alternate functions in pj7:pj4 signal name pj7 pj6/ pcint15 pj5/ pcint14 pj4/ pcint13 puoe0000 puov0000 ddoe 0 0 0 0 ddov 0 0 0 0 pvoe0000 pvov0000 ptoe---- dieoe 0 pci n t15pcie1 pci n t14pcie1 pci n t13pcie1 dieov0111 di 0 pci n t15 i n put pci n t14 i n put pci n t13 i n put aio---- table 65. overriding signals for alternate functions in pj3:pj0 signal name pj3/pcint12 pj2/xck3/pcin t11 pj1/txd3/pcin t10 pj0/rxd3/pcin t9 puoe 0 0 txe n 3rxe n 3 puov 0 0 0 portj0pud ddoe 0 xck3 output e n able txe n 3rxe n 3 ddov 0 1 1 0 pvoe 0 xck3 output e n able txe n 30 pvov 0 xck3 txd3 0 ptoe---- dieoe pci n t12pcie1 pci n t11pcie1 pci n t10pcie1 pci n t9pcie1 dieov1111 di pci n t12 i n put pci n t11 i n put xck3 i n put pci n t10 i n put pci n t9 i n put rxd3 aio---- 111 atmega640/1280/1281/2560/2561 2549k?avr?01/07 alternate functions of port k the port k alternate pin configuration is as follows: ? adc15:8/pcint23:16 ? port k, bit 7:0 adc15:8, analog to digital converter, channel 15 - 8. pci n t23:16, pin change interrupt source 23:16. the pk7:0 pins can serve as external interrupt sources. table 66. port k pins alternate functions port pin alternate function pk7 adc15/pci n t23 (adc input channel 15 or pin change interrupt 23) pk6 adc14/pci n t22 (adc input channel 14 or pin change interrupt 22) pk5 adc13/pci n t21 (adc input channel 13 or pin change interrupt 21) pk4 adc12/pci n t20 (adc input channel 12 or pin change interrupt 20) pk3 adc11/pci n t19 (adc input channel 11 or pin change interrupt 19) pk2 adc10/pci n t18 (adc input channel 10 or pin change interrupt 18) pk1 adc9/pci n t17 (adc input channel 9 or pin change interrupt 17) pk0 adc8 /pci n t16 (adc input channel 8 or pin change interrupt 16) table 67. overriding signals for alternate functions in pk7:pk4 signal name pk7/adc15/ pcint23 pk6/adc14/ pcint22 pk5/adc13/ pcint21 pk4/adc12/ pcint20 puoe0000 puov0000 ddoe0000 ddov0000 pvoe0000 pvov0000 ptoe???? dieoe pci n t23 ? pcie2 pci n t22 ? pcie2 pci n t21 ? pcie2 pci n t20 ? pcie2 dieov1111 di pci n t23 i n put pci n t22 i n put pci n t21 i n put pci n t20 i n put aio adc15 i n put adc14 i n put adc13 i n put adc12 i n put 112 atmega640/1280/1281/2560/2561 2549k?avr?01/07 table 68. overriding signals for alternate functions in pk3:pk0 signal name pk3/adc11/ pcint19 pk2/adc10/ pcint18 pk1/adc9/ pcint17 pk0/adc8/ pcint16 puoe0000 puov0000 ddoe 0 0 0 0 ddov 0 0 0 0 pvoe0000 pvov0000 ptoe???? dieoe pci n t19 ? pcie2 pci n t18 ? pcie2 pci n t17 ? pcie2 pci n t16 ? pcie2 dieov1111 di pci n t19 i n put pci n t18 i n put pci n t17 i n put pci n t16 i n put aio adc11 i n put adc10i n put adc9 i n put adc8 i n put 113 atmega640/1280/1281/2560/2561 2549k?avr?01/07 alternate functions of port l the port l alternate pin configuration is as follows: ? oc5c ? port l, bit 5 oc5c, output compare match c output: the pl5 pin can serve as an external output for the timer/counter5 output compare c. the pin has to be configured as an output (ddl5 set) to serve this function. the oc5c pin is also the output pin for the p w m mode timer function. ? oc5b ? port l, bit 4 oc5b, output compare match b output: the pl4 pin can serve as an external output for the timer/counter 5 output compare b. the pin has to be configured as an output (ddl4 set) to serve this function. the oc5b pin is also the output pin for the p w m mode timer function. ? oc5a ? port l, bit 3 oc5a, output compare match a output: the pl3 pin can serve as an external output for the timer/counter 5 output compare a. the pin has to be configured as an output (ddl3 set) to serve this function. the oc5a pin is also the output pin for the p w m mode timer function. ? t5 ? port l, bit 2 t5, timer/counter5 counter source. ? icp5 ? port l, bit 1 icp5, input capture pin 5: the pl1 pin can serve as an input capture pin for timer/counter5. ? icp4 ? port l, bit 0 icp4, input capture pin 4: the pl0 pin can serve as an input capture pin for timer/counter4. table 69. port l pins alternate functions port pin alternate function pl7 ? pl6 ? pl5 oc5c (output compare and p w m output c for timer/counter5) pl4 oc5b (output compare and p w m output b for timer/counter5) pl3 oc5a (output compare and p w m output a for timer/counter5) pl2 t5 (timer/counter5 clock input) pl1 icp5 (timer/counter5 input capture trigger) pl0 icp4 (timer/counter4 input capture trigger) 114 atmega640/1280/1281/2560/2561 2549k?avr?01/07 table 70 and table 71 relates the alternate func tions of port l to the overriding signals shown in figure 36 on page 89. table 70. overriding signals for alternate functions in pl7:pl4 signal name pl7 pl6 pl5/oc5c pl4/oc5b puoe0000 puov0000 ddoe ? ? 0 0 ddov ? ? 0 0 pvoe ? ? oc5c e n able oc5b e n able pvov ? ? oc5c oc5b ptoe???? dieoe 0 0 0 0 dieov 0 0 0 0 di0000 aio ? ? ? ? table 71. overriding signals for alternate functions in pl3:pl0 signal name pl3/oc5a pl 2/t5 pl1/icp5 pl0/icp4 puoe0000 puov0000 ddoe 0 0 0 0 ddov 0 0 0 0 pvoe oc5a e n able 0 0 0 pvov oc5a 0 0 0 ptoe???? dieoe 0 0 0 0 dieov 0 0 0 0 di 0 t5 i n put icp5 i n put icp4 i n put aio ? ? ? ? 115 atmega640/1280/1281/2560/2561 2549k?avr?01/07 register description for i/o-ports mcucr ? mcu control register ? bit 4 ? pud: pull-up disable w hen this bit is written to one, the i/o ports pull-up resistors are disabled even if the ddxn and portxn registers are configur ed to enable the pull-up resistor ({ddxn, portxn} = 0b01). see ?configuring the pin? on page 84 for more details about this feature. porta ? port a data register ddra ? port a data direction register pina ? port a input pins address portb ? port b data register ddrb ? port b data direction register pinb ? port b input pins address bit 7 6 5 4 3 2 1 0 0x35 (0x55) jtd ? ?pud ? ? ivsel ivce mcucr read/ w rite r/ w rrr/ w rrr/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x02 (0x22) porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 porta read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 0x01 (0x21) dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 ddra read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 0x00 (0x20) pina7 pina6 pina5 pina4 pi na3 pina2 pina1 pina0 pina read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value n /a n /a n /a n /a n /a n /a n /a n /a bit 76543210 0x05 (0x25) portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 portb read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 0x04 (0x24) ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 ddrb read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 0x03 (0x23) pinb7 pinb6 pinb5 pinb4 pi nb3 pinb2 pinb1 pinb0 pinb read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value n /a n /a n /a n /a n /a n /a n /a n /a 116 atmega640/1280/1281/2560/2561 2549k?avr?01/07 portc ? port c data register ddrc ? port c data direction register pinc? port c input pins address portd ? port d data register ddrd ? port d data direction register pind ? port d input pins address porte ? port e data register ddre ? port e data direction register pine ? port e input pins address bit 76543210 0x08 (0x28) portc7 portc6 portc5 portc4 portc3 portc2 portc1 portc0 portc read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 0x07 (0x27) ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 ddrc read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 0x06 (0x26) pinc7 pinc6 pinc5 pinc4 pi nc3 pinc2 pinc1 pinc0 pinc read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value n /a n /a n /a n /a n /a n /a n /a n /a bit 76543210 0x0b (0x2b) portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 portd read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 0x0a (0x2a) ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 ddrd read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 0x09 (0x29) pind7 pind6 pind5 pind4 pi nd3 pind2 pind1 pind0 pind read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value n /a n /a n /a n /a n /a n /a n /a n /a bit 76543210 0x0e (0x2e) porte7 porte6 porte5 porte4 porte3 porte2 porte1 porte0 porte read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 0x0d (0x2d) dde7 dde6 dde5 dde4 dde3 dde2 dde1 dde0 ddre read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 0x0c (0x2c) pine7 pine6 pine5 pine4 pine3 pine2 pine1 pine0 pine read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value n /a n /a n /a n /a n /a n /a n /a n /a 117 atmega640/1280/1281/2560/2561 2549k?avr?01/07 portf ? port f data register ddrf ? port f data direction register pinf ? port f input pins address portg ? port g data register ddrg ? port g data direction register ping ? port g input pins address porth ? port h data register ddrh ? port h data direction register pinh ? port h input pins address bit 76543210 0x11 (0x31) portf7 portf6 portf5 portf4 portf3 portf2 portf1 portf0 portf read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 0x10 (0x30) ddf7 ddf6 ddf5 ddf4 ddf3 ddf2 ddf1 ddf0 ddrf read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 0x0f (0x2f) pinf7 pinf6 pinf5 pinf4 pinf3 pinf2 pinf1 pinf0 pinf read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value n /a n /a n /a n /a n /a n /a n /a n /a bit 76543210 0x14 (0x34) ?? portg5 portg4 portg3 portg2 portg1 portg0 portg read/ w rite r r r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x13 (0x33) ? ? ddg5 ddg4 ddg3 ddg2 ddg1 ddg0 ddrg read/ w rite r r r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 0x12 (0x32) ? ? ping5 ping4 ping3 ping2 ping1 ping0 ping read/ w rite r r r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 n /a n /a n /a n /a n /a n /a bit 76543210 (0x102) porth7 porth6 porth5 porth4 porth3 porth2 porth1 porth0 porth read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 (0x101) ddh7 ddh6 ddh5 ddh4 ddh3 ddh2 ddh1 ddh0 ddrh read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 (0x100) pinh5 pinh5 pinh5 pinh4 pinh3 pingh pinh1 pinh0 pinh read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value n /a n /a n /a n /a n /a n /a n /a n /a 118 atmega640/1280/1281/2560/2561 2549k?avr?01/07 portj ? port j data register ddrj ? port j data direction register pinj ? port j input pins address portk ? port k data register ddrk ? port k data direction register pink ? port k input pins address portl ? port l data register ddrl ? port l data direction register pinl ? port l input pins address bit 76543210 (0x105) portj7 portj6 portj5 portj4 portj3 portj2 portj1 portj0 portj read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 (0x104) ddj7 ddj6 ddj5 ddj4 ddj3 ddj2 ddj1 ddj0 ddrj read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 (0x103) pinj5 pinj5 pinj5 pinj4 pinj3 pingj pinj1 pinj0 pinj read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value n /a n /a n /a n /a n /a n /a n /a n /a bit 76543210 (0x108) portk7 portk6 portk5 portk4 portk3 portk2 portk1 portk0 portk read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 (0x107) ddk7 ddk6 ddk5 ddk4 ddk3 ddk2 ddk1 ddk0 ddrk read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 (0x106) pink5 pink5 pink5 pink4 pink3 pingk pink1 pink0 pink read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value n /a n /a n /a n /a n /a n /a n /a n /a bit 76543210 (0x10b) portl7 portl6 portl5 portl4 portl3 portl2 portl1 portl0 portl read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 (0x10a) ddl7 ddl6 ddl5 ddl4 ddl3 ddl2 ddl1 ddl0 ddrl read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 (0x109) pinl5 pinl5 pinl5 pinl4 pinl3 pingl pinl1 pinl0 pinl read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value n /a n /a n /a n /a n /a n /a n /a n /a 119 atmega640/1280/1281/2560/2561 2549k?avr?01/07 8-bit timer/counter0 with pwm timer/counter0 is a general purpose 8-bi t timer/counter module, with two independent output compare units, and with p w m support. it allows accurate program execution timing (event management) and wave generation. the main features are: ? two independent output compare units ? double buffered out put compare registers ? clear timer on compar e match (auto reload) ? glitch free, phase correct pulse width modulator (pwm) ? variable pwm period ? frequency generator ? three independent interrupt sources (tov0, ocf0a, and ocf0b) overview a simplified block diagram of the 8-bit time r/counter is shown in figure 37. for the actual placement of i/o pins, refer to ?tqfp-pinout atmega640/1280/2560? on page 2. cpu accessible i/o registers, including i/o bits and i/o pins, are shown in bold. the device-specific i/o register and bit locations are listed in the ?register description? on page 130. figure 37. 8-bit timer/counter block diagram registers the timer/counter (tc n t0) and output compare registers (ocr0a and ocr0b) are 8-bit registers. interrupt request (abbreviated to int.req. in the figure) signals are all vis- ible in the timer interrupt flag register (t ifr0). all interrupts are individually masked with the timer interrupt mask register (timsk0). tifr0 and timsk0 are not shown in the figure. the timer/counter can be clocked internally, via the prescaler, or by an external clock source on the t0 pin. the clock select logic block controls which clock source and edge the timer/counter uses to increment (or decrement) its value. the timer/counter is inactive when no cloc k source is selected. the output from the clock select logic is referred to as the timer clock (clk t0 ). the double buffered output compare registers (ocr0a and ocr0b) are compared with the timer/counter value at all times. the result of the compare can be used by the w aveform generator to generate a p w m or variable frequency output on the output clock select timer/counter data bus ocrna ocrnb = = tcntn waveform generation waveform generation ocna ocnb = fixed top value control logic = 0 top bottom count clear direction tovn (int.req.) ocna (int.req.) ocnb (int.req.) tccrna tccrnb tn edge detector ( from prescaler ) clk tn 120 atmega640/1280/1281/2560/2561 2549k?avr?01/07 compare pins (oc0a and oc0b). see ?output compare unit? on page 121. for details. the compare match event will also set the compare flag (ocf0a or ocf0b) which can be used to generate an output compare interrupt request. definitions many register and bit references in this section are written in general form. a lower case ?n? replaces the timer/counter number, in this case 0. a lower case ?x? replaces the output compare unit, in this case compare unit a or co mpare unit b. however, when using the register or bit defines in a pr ogram, the precise form must be used, i.e., tc n t0 for accessing ti mer/counter0 counter value and so on. the definitions in table 72 are also used extensively throughout the document. timer/counter clock sources the timer/counter can be clocked by an intern al or an external clock source. the clock source is selected by the clock select lo gic which is controlled by the clock select (cs02:0) bits located in the timer/counte r control register (tccr0b). for details on clock sources and prescaler, see ?timer/counter 0, 1, 3, 4, and 5 prescaler? on page 172. counter unit the main part of the 8-bit timer/counter is the programmable bi-directional counter unit. figure 38 shows a block diagram of the counter and its surroundings. figure 38. counter unit block diagram signal description (internal signals): count increment or decrement tc n t0 by 1. direction select between increment and decrement. clear clear tc n t0 (set all bits to zero). clk t n timer/counter clock, referred to as clk t0 in the following. top signalize that tc n t0 has reached maximum value. bottom signalize that tc n t0 has reached minimum value (zero). table 72. definitions bottom the counter reaches the bottom when it becomes 0x00. max the counter reaches its maximum when it becomes 0xff (decimal 255). top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be assigned to be the fixed value 0xff (max) or the value stored in the ocr0a register. the assignment is dependent on the mode of operation. data b u s tcntn control logic count tovn (int.req.) clock select top tn edge detector ( from prescaler ) clk tn bottom direction clear 121 atmega640/1280/1281/2560/2561 2549k?avr?01/07 depending of the mode of operation used, the counter is cleared, incremented, or dec- remented at each timer clock (clk t0 ). clk t0 can be generated from an external or internal clock source, selected by the clock select bits (cs02:0). w hen no clock source is selected (cs02:0 = 0) the timer is stopped. however, the tc n t0 value can be accessed by the cpu, regardless of whether clk t0 is present or not. a cpu write overrides (has priority over) all counter clear or count operations. the counting sequence is determ ined by the setting of the w gm01 and w gm00 bits located in the timer/counter cont rol register (tccr0a) and the w gm02 bit located in the timer/counter control register b (tccr0b). there are close connections between how the counter behaves (counts) and how waveforms are generated on the output compare outputs oc0a and oc0b. for more details about advanced counting sequences and waveform generation, see ?modes of operation? on page 124. the timer/counter overflow flag (tov0) is set according to the mode of operation selected by the w gm02:0 bits. tov0 can be used for generating a cpu interrupt. output compare unit the 8-bit comparator continuously compares tc n t0 with the output compare regis- ters (ocr0a and ocr0b). w henever tc n t0 equals ocr0a or ocr0b, the comparator signals a match. a match will set the output compare flag (ocf0a or ocf0b) at the next timer clock cycle. if the corresponding interrupt is enabled, the out- put compare flag generates an output compare interrupt. the output compare flag is automatically cleared when the interrupt is executed. alternatively, the flag can be cleared by software by writing a logical one to its i/o bit location. the w aveform gener- ator uses the match signal to generate an output according to operating mode set by the w gm02:0 bits and compare output mode (com0x1:0) bits. the max and bottom sig- nals are used by the w aveform generator for handling the special cases of the extreme values in some modes of operation (?modes of operation? on page 124). figure 39 shows a block diagram of the output compare unit. figure 39. output compare unit, block diagram ocfn x (int.req.) = (8-bit comparator ) ocrnx ocnx data b u s tcntn wgmn1:0 waveform generator top focn comnx1:0 bottom 122 atmega640/1280/1281/2560/2561 2549k?avr?01/07 the ocr0x registers are double buffered when using any of the pulse w idth modula- tion (p w m) modes. for the normal and clear timer on compare (ctc) modes of operation, the double buffering is disabled. the double buffering synchronizes the update of the ocr0x compare registers to either top or bottom of the counting sequence. the synchronization prevents the occurrence of odd-length, non-symmetrical p w m pulses, thereby making the output glitch-free. the ocr0x register access may seem complex, but this is not case. w hen the double buffering is enabled, the cpu has access to the ocr0x buffer register, and if double buffering is disabled the cp u will access the ocr0x directly. force output compare in non-p w m waveform generation modes, the match output of the comparator can be forced by writing a one to the force output compare (foc0x) bit. forcing compare match will not set the ocf0x flag or reload /clear the timer, but the oc0x pin will be updated as if a real compare match had occurred (the com0x1:0 bits settings define whether the oc0x pin is set, cleared or toggled). compare match blocking by tcnt0 write all cpu write operations to the tc n t0 register will block any compare match that occur in the next timer clock cycle, even w hen the timer is stopped. this feature allows ocr0x to be initialized to the same value as tc n t0 without triggering an interrupt when the timer/counter clock is enabled. using the output compare unit since writing tc n t0 in any mode of op eration will block all co mpare matches for one timer clock cycle, there are risks involved when changing tc n t0 when using the output compare unit, independently of whether the timer/counter is running or not. if the value written to tc n t0 equals the ocr0x value, the compare match will be missed, resulting in incorrect waveform generation. similarly, do not write the tc n t0 value equal to bottom when the counter is down-counting. the setup of the oc0x should be performed before setting the data direction register for the port pin to output. the easiest way of setting the oc0x value is to use the force output compare (foc0x) strobe bits in n ormal mode. the oc0x registers keep their values even when changing between w aveform generation modes. be aware that the com0x1:0 bits are not double buffered together with the compare value. changing the com0x1:0 bi ts will take effect immediately. 123 atmega640/1280/1281/2560/2561 2549k?avr?01/07 compare match output unit the compare output mode (com0x1:0) bits have two functions. the w aveform gener- ator uses the com0x1:0 bits for defining the output compare (oc0x) state at the next compare match. also, the com0x1:0 bits control the oc0x pin output source. figure 40 shows a simplified schematic of the logic affected by the com0x1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the figur e are shown in bold. only the parts of the general i/o port cont rol registers (ddr and port) that are affected by the com0x1:0 bits are shown. w hen referring to the oc0x state, the reference is for the internal oc0x register, not the oc0x pin. if a system reset occur, the oc0x register is reset to ?0?. figure 40. compare match output unit, schematic the general i/o port function is overridden by the output compare (oc0x) from the w aveform generator if either of the com0x1:0 bits are set. however, the oc0x pin direction (input or output) is still controlled by the data dir ection register (ddr) for the port pin. the data direction register bit for the oc0x pin (ddr_oc0x) must be set as output before the oc0x value is visible on the pin. the port override function is indepen- dent of the w aveform generation mode. the design of the output compare pin logic allows initialization of the oc0x state before the output is enabled. n ote that some com0x1:0 bit settings are reserved for certain modes of operation. see ?register description? on page 130. compare output mode and waveform generation the w aveform generator uses the com0x1:0 bits differently in n ormal, ctc, and p w m modes. for all modes, setting the com0x1:0 = 0 tells the w aveform generator that no action on the oc0x register is to be performed on the next compare match. for com- pare output actions in the non-p w m modes refer to table 73 on page 130. for fast p w m mode, refer to table 74 on page 130, and for phase correct p w m refer to table 75 on page 131. a change of the com0x1:0 bits state will have effect at the first compare match after the bits are written. for non-p w m modes, the action can be forced to have immediate effect by using the foc0x strobe bits. port ddr dq dq ocnx pin ocnx dq waveform generator comnx1 comnx0 0 1 data b u s focn clk i/o 124 atmega640/1280/1281/2560/2561 2549k?avr?01/07 modes of operation the mode of operation, i.e., the behavior of the timer/counter and the output compare pins, is defined by the combination of the w aveform generation mode ( w gm02:0) and compare output mode (com0x1:0) bits. the compare output mode bits do not affect the counting sequence, while the w aveform generation mode bits do. the com0x1:0 bits control whether the p w m output generated should be inverted or not (inverted or non-inverted p w m). for non-p w m modes the com0x1:0 bits control whether the out- put should be set, cleared, or toggled at a compare match (see ?compare match output unit? on page 148.). for detailed timing information see ?timer/counter timing diagrams? on page 128. normal mode the simplest mode of operation is the n ormal mode ( w gm02:0 = 0). in this mode the counting direction is always up (incrementing), and no counter clear is performed. the counter simply overruns when it passes its maximum 8-bit value (top = 0xff) and then restarts from the bottom (0x00). in normal operation the timer/counter overflow flag (tov0) will be set in the same timer clock cycle as the tc n t0 becomes zero. the tov0 flag in this case behaves like a ninth bit, except that it is only set, not cleared. however, combined with the timer overflow interrupt that automatically clears the tov0 flag, the timer resolution can be increased by software. there are no special cases to consider in the n ormal mode, a new counter value can be written anytime. the output compare unit can be used to generate interrupts at some given time. using the output compare to generate waveforms in n ormal mode is not recommended, since this will occupy too much of the cpu time. clear timer on compare match (ctc) mode in clear timer on compare or ctc mode ( w gm02:0 = 2), the ocr0a register is used to manipulate the counter resolution. in ctc mode the counter is cleared to zero when the counter value (tc n t0) matches the ocr0a. the ocr0a defines the top value for the counter, hence also its resolution. this mode allows greater control of the compare match output frequency. it also simplifies th e operation of counting external events. the timing diagram for the ctc mode is shown in figure 41. the counter value (tc n t0) increases until a compare match occurs between tc n t0 and ocr0a, and then counter (tc n t0) is cleared. figure 41. ctc mode, timing diagram an interrupt can be generated each time the counter value reaches the top value by using the ocf0a flag. if the interrupt is enabled, the interrupt handler routine can be used for updating the top value. however, changing top to a value close to bottom when the counter is running with none or a low prescaler value must be done with care since the ctc mode does not have the double buffering feature. if the new value written to ocr0a is lower than the current value of tc n t0, the counter will miss the compare tcntn ocn (toggle) ocnx interrupt flag set 1 4 period 2 3 (comnx1:0 = 1) 125 atmega640/1280/1281/2560/2561 2549k?avr?01/07 match. the counter will then have to count to its maxi mum value (0xff) and wrap around starting at 0x00 before the compare match can occur. for generating a waveform output in ctc mode, the oc0a output can be set to toggle its logical level on each compare match by setting the compare output mode bits to toggle mode (com 0a1:0 = 1). the oc0a value will not be visible on the port pin unless the data direction for the pin is set to output. the waveform generated will have a maxi- mum frequency of f oc0 = f clk_i/o /2 when ocr0a is set to zero (0x00). the waveform frequency is defined by the following equation: the n variable represents the prescale factor (1, 8, 64, 256, or 1024). as for the n ormal mode of operation, the tov0 flag is set in the same timer clock cycle that the counter counts from max to 0x00. fast pwm mode the fast pulse w idth modulation or fast p w m mode ( w gm02:0 = 3 or 7) provides a high frequency p w m waveform generation option. the fast p w m differs from the other p w m option by its single-slope operation. the counter counts from bottom to top then restarts from bottom. top is defined as 0xff when w gm2:0 = 3, and ocr0a when w gm2:0 = 7. in non-inverting compare output mode, the output compare (oc0x) is cleared on the compare match between tc n t0 and ocr0x, and set at bottom. in inverting compare output mode, the output is set on compare match and cleared at bottom. due to the single-slope operation, the operating frequency of the fast p w m mode can be twice as high as the phase correct p w m mode that use dual-slope opera- tion. this high frequency makes the fast p w m mode well suited for power regulation, rectification, and dac applications. high fr equency allows physicall y small sized exter- nal components (coils, capacitors), and therefore reduces total system cost. in fast p w m mode, the counter is incremented until the counter value matches the top value. the counter is then cleared at the following timer clock cycle. the timing diagram for the fast p w m mode is shown in figure 42. the tc n t0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. the diagram includes non-inverted and inverted p w m outputs. the small horizontal line marks on the tc n t0 slopes represent compare matches between ocr0x and tc n t0. figure 42. fast p w m mode, timing diagram f ocnx f clk_i/o 2 n 1 ocrnx + () ?? ------------------------------------------------- - = tcntn ocrnx update and tovn interrupt flag set 1 period 2 3 ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) ocrnx interrupt flag set 4 5 6 7 126 atmega640/1280/1281/2560/2561 2549k?avr?01/07 the timer/counter overflow flag (tov0) is set each time the counter reaches top. if the interrupt is enabled, the interrupt handler routine can be used for updating the com- pare value. in fast p w m mode, the compare unit allows generation of p w m waveforms on the oc0x pins. setting the com0x1:0 bits to two will produce a non-inverted p w m and an inverted p w m output can be generated by setting the com0x1:0 to three: setting the com0a1:0 bits to one allows the oc0a pin to toggle on compare matches if the w gm02 bit is set. this option is not avai lable for the oc0b pin (see table 74 on page 130). the actual oc0x value will only be visible on the port pin if the data direction for the port pin is set as output. the p w m waveform is generated by setting (or clearing) the oc0x register at the compare match between ocr0x and tc n t0, and clearing (or setting) the oc0x register at the timer clo ck cycle the counter is cleared (changes from top to bottom). the p w m frequency for the output can be calculated by the following equation: the n variable represents the prescale factor (1, 8, 64, 256, or 1024). the extreme values for the ocr0a register represents special cases when generating a p w m waveform output in the fast p w m mode. if the ocr0a is set equal to bottom, the output will be a narro w spike for each max+1 timer cl ock cycle. setting the ocr0a equal to max will result in a constantly high or low output (depending on t he polarity of the output set by the com0a1:0 bits.) a frequency (with 50% duty cycle) waveform output in fast p w m mode can be achieved by setting oc0x to toggle its logical leve l on each compare match (com0x1:0 = 1). the waveform generated will have a maximum frequency of f oc0 = f clk_i/o /2 when ocr0a is set to zero. this feature is similar to t he oc0a toggle in ctc mode, except the double buffer feature of the output compare unit is enabled in the fast p w m mode. phase correct pwm mode the phase correct p w m mode ( w gm02:0 = 1 or 5) provides a high resolution phase correct p w m waveform generation option. the phase correct p w m mode is based on a dual-slope operation. the counter counts repeatedly from bottom to top and then from top to bottom. top is defined as 0xff when w gm2:0 = 1, and ocr0a when w gm2:0 = 5. in non-inverting compare output mode, the output compare (oc0x) is cleared on the compare match between tc n t0 and ocr0x while upcounting, and set on the compare match while down-counting. in inverting output compare mode, the operation is inverted. the dual-slope operation has lower maximum operation frequency than single slope operation. however, due to the symmetric feature of the dual-slope p w m modes, these modes are preferred for motor control applications. in phase correct p w m mode the counter is incremented until the counter value matches top. w hen the counter reaches top, it changes the count direction. the tc n t0 value will be equal to top for one timer clock cycle. the timing diagram for the phase correct p w m mode is shown on figure 43. the tc n t0 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. the diagra m includes non-inverted and inverted p w m outputs. the small horizontal line marks on the tc n t0 slopes repre- sent compare matches between ocr0x and tc n t0. f ocnxpwm f clk_i/o n 256 ? ------------------ = 127 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 43. phase correct p w m mode, timing diagram the timer/counter overflow flag (tov0) is set each time the counter reaches bot- tom. the interrupt flag can be used to generate an interrupt each time the counter reaches the bottom value. in phase correct p w m mode, the compare unit allows generation of p w m waveforms on the oc0x pins. setting the com0x1:0 bits to two will produce a non-inverted p w m. an inverted p w m output can be generated by setting the com0x1:0 to three: setting the com0a0 bits to one allows the oc0a pin to toggle on compare matches if the w gm02 bit is set. this option is not available for th e oc0b pin (see table 75 on page 131). the actual oc0x value will only be visible on the port pin if the data direction for the port pin is set as output. the p w m waveform is generated by clearing (or setting) the oc0x register at the compare match between ocr0x and tc n t0 when the counter incre- ments, and setting (or clearing) the oc0x register at compare match between ocr0x and tc n t0 when the counter decrements. the p w m frequency for the output when using phase correct p w m can be calculated by the following equation: the n variable represents the prescale factor (1, 8, 64, 256, or 1024). the extreme values for the ocr0a register represent special cases when generating a p w m waveform output in the phase correct p w m mode. if the ocr0a is set equal to bottom, the output will be cont inuously low and if set e qual to max the output will be continuously high for non-inverted p w m mode. for inverted p w m the output will have the opposite logic values. at the very start of period 2 in figure 43 ocnx has a transition from high to low even though there is no compare match. the point of this transition is to guarantee symmetry around bottom. there are two cases that give a transition without compare match. ? ocr0a changes its value from max, like in figure 43. w hen the ocr0a value is max the ocn pin value is the same as the result of a down-counting compare tovn interrupt flag set ocnx interrupt flag set 1 2 3 tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) ocrnx update f ocnxpcpwm f clk_i/o n 510 ? ------------------ = 128 atmega640/1280/1281/2560/2561 2549k?avr?01/07 match. to ensure symmetry around bottom the ocn value at max must correspond to the result of an up-counting compare match. ? the timer starts counting from a value higher than the one in ocr0a, and for that reason misses the compare match and hence the ocn change that would have happened on the way up. timer/counter timing diagrams the timer/counter is a synchronous design and the timer clock (clk t0 ) is therefore shown as a clock enable signal in the followi ng figures. the figures include information on when interrupt flags are set. figure 44 contains timing data for basic timer/counter operation. the figure shows the count sequence close to the max value in all modes other than phase correct p w m mode. figure 44. timer/counter timing diagram, no prescaling figure 45 shows the same timing data, but with the prescaler enabled. figure 45. timer/counter timing diagram, with prescaler (f clk_i/o /8) figure 46 shows the setting of ocf0b in all modes and ocf0a in all modes except ctc mode and p w m mode, where ocr0a is top. figure 46. timer/counter timing diagram, setting of ocf0x, with prescaler (f clk_i/o /8) clk tn (clk i/o /1) tovn clk i/o tcntn max - 1 max bottom bottom + 1 tovn tcntn max - 1 max bottom bottom + 1 clk i/o clk tn (clk i/o /8) ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) 129 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 47 shows the setting of ocf0a and the clearing of tc n t0 in ctc mode and fast p w m mode where ocr0a is top. figure 47. timer/counter timing diagram, clear timer on compare match mode, with prescaler (f clk_i/o /8) ocfnx ocrnx tcntn (ctc) top top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o /8) 130 atmega640/1280/1281/2560/2561 2549k?avr?01/07 register description tccr0a ? timer/counter control register a ? bits 7:6 ? com0a1:0: compare match output a mode these bits control the output compare pin (oc0a) behavior. if one or both of the com0a1:0 bits are set, the oc0a output overrides the normal port functionality of the i/o pin it is connected to. ho wever, note that t he data direction register (ddr) bit cor- responding to the oc0a pin must be set in order to enable the output driver. w hen oc0a is connected to the pin, the func tion of the com0a1:0 bits depends on the w gm02:0 bit setting. table 73 shows the com0a1:0 bit functionality when the w gm02:0 bits are set to a normal or ctc mode (non-p w m). table 74 shows the com0a1:0 bit functionality when the w gm01:0 bits are set to fast p w m mode. n ote: 1. a special case occurs when ocr0a equals top and com0a1 is set. in this case, the compare match is ignored, but the set or clear is done at bottom. see ?fast p w m mode? on page 125 for more details. table 75 on page 131 shows the com0a1:0 bit functionality when the w gm02:0 bits are set to phase correct p w m mode. bit 7 6 5 4 3 2 1 0 0x24 (0x44) com0a1 com0a0 com0b1 com0b0 ? ? wgm01 wgm00 tccr0a read/ w rite r/ w r/ w r/ w r/ w rrr/ w r/ w initial value 0 0 0 0 0 0 0 0 table 73. compare output mode, non-p w m mode com0a1 com0a0 description 00 n ormal port operation, oc0a disconnected. 0 1 toggle oc0a on compare match 1 0 clear oc0a on compare match 1 1 set oc0a on compare match table 74. compare output mode, fast p w m mode (1) com0a1 com0a0 description 00 n ormal port operation, oc0a disconnected. 01 w gm02 = 0: n ormal port operation, oc0a disconnected. w gm02 = 1: toggle oc0a on compare match. 1 0 clear oc0a on compare match, set oc0a at bottom, (non-inverting mode). 1 1 set oc0a on compare match, clear oc0a at bottom, (inverting mode). 131 atmega640/1280/1281/2560/2561 2549k?avr?01/07 n ote: 1. a special case occurs when ocr0a equals top and com0a1 is set. in this case, the compare match is ignored, but the set or clear is done at top. see ?phase cor- rect p w m mode? on page 126 for more details. ? bits 5:4 ? com0b1:0: compare match output b mode these bits control the output compare pin (oc0b) behavior. if one or both of the com0b1:0 bits are set, the oc0b output overrides the normal port functionality of the i/o pin it is connected to. ho wever, note that t he data direction register (ddr) bit cor- responding to the oc0b pin must be set in order to enable the output driver. w hen oc0b is connected to the pin, the func tion of the com0b1:0 bits depends on the w gm02:0 bit setting. table 73 shows the com0a1:0 bit functionality when the w gm02:0 bits are set to a normal or ctc mode (non-p w m). table 74 shows the com0b1:0 bit functionality when the w gm02:0 bits are set to fast p w m mode. n ote: 1. a special case occurs when ocr0b equals top and com0b1 is set. in this case, the compare match is ignored, but the set or clear is done at bottom. see ?fast p w m mode? on page 125 for more details. table 75. compare output mode, phase correct p w m mode (1) com0a1 com0a0 description 00 n ormal port operation, oc0a disconnected. 01 w gm02 = 0: n ormal port operation, oc0a disconnected. w gm02 = 1: toggle oc0a on compare match. 1 0 clear oc0a on compare match when up-counting. set oc0a on compare match when down-counting. 1 1 set oc0a on compare match when up-counting. clear oc0a on compare match when down-counting. table 76. compare output mode, non-p w m mode com0b1 com0b0 description 00 n ormal port operation, oc0b disconnected. 0 1 toggle oc0b on compare match 1 0 clear oc0b on compare match 1 1 set oc0b on compare match table 77. compare output mode, fast p w m mode (1) com0b1 com0b0 description 00 n ormal port operation, oc0b disconnected. 01reserved 1 0 clear oc0b on compare match, set oc0b at bottom, (non-inverting mode). 1 1 set oc0b on compare match, clear oc0b at bottom, (inverting mode). 132 atmega640/1280/1281/2560/2561 2549k?avr?01/07 table 75 shows the com0b1:0 bit functionality when the w gm02:0 bits are set to phase correct p w m mode. n ote: 1. a special case occurs when ocr0b equals top and com0b1 is set. in this case, the compare match is ignored, but the set or clear is done at top. see ?phase cor- rect p w m mode? on page 126 for more details. ? bits 3, 2 ? res: reserved bits these bits are reserved bits and will always read as zero. ? bits 1:0 ? wgm01:0: waveform generation mode combined with the w gm02 bit found in the tccr0b register, these bits control the counting sequence of the counter, the source for maximum (top) counter value, and what type of waveform generation to be used, see table 79. modes of operation sup- ported by the timer/counter unit are: n ormal mode (counter), clear timer on compare match (ctc) mode, and two types of pulse w idth modulation (p w m) modes (see ?modes of operation? on page 149). n otes: 1. max = 0xff 2. bottom = 0x00 table 78. compare output mode, phase correct p w m mode (1) com0b1 com0b0 description 00 n ormal port operation, oc0b disconnected. 01reserved 1 0 clear oc0b on compare match when up-counting. set oc0b on compare match when down-counting. 1 1 set oc0b on compare match when up-counting. clear oc0b on compare match when down-counting. table 79. w aveform generation mode bit description mode wgm2 wgm1 wgm0 timer/counter mode of operation top update of ocrx at tov flag set on (1)(2) 00 0 0 n ormal 0xff immediate max 10 0 1p w m, phase correct 0xff top bottom 2 0 1 0 ctc ocra immediate max 3 0 1 1 fast p w m 0xff top max 41 0 0reserved ? ? ? 51 0 1p w m, phase correct ocra top bottom 61 1 0reserved ? ? ? 7 1 1 1 fast p w m ocra bottom top 133 atmega640/1280/1281/2560/2561 2549k?avr?01/07 tccr0b ? timer/counter control register b ? bit 7 ? foc0a: force output compare a the foc0a bit is only active when the w gm bits specify a non-p w m mode. however, for ensuring compatib ility with future devices, this bit must be set to zero when tccr0b is written when operating in p w m mode. w hen writing a logical one to the foc0a bit, an immediate compare match is forced on the w aveform generation unit. the oc0a output is changed according to its com0a1:0 bits setting. n ote that the foc0a bit is implemented as a strobe. therefore it is the value present in the com0a1:0 bits that determines the effect of the forced compare. a foc0a strobe will not generate any interrup t, nor will it clear the timer in ctc mode using ocr0a as top. the foc0a bit is always read as zero. ? bit 6 ? foc0b: force output compare b the foc0b bit is only active when the w gm bits specify a non-p w m mode. however, for ensuring compatib ility with future devices, this bit must be set to zero when tccr0b is written when operating in p w m mode. w hen writing a logical one to the foc0b bit, an immediate compare match is forced on the w aveform generation unit. the oc0b output is changed according to its com0b1:0 bits setting. n ote that the foc0b bit is implemented as a strobe. therefore it is the value present in the com0b1:0 bits that determines the effect of the forced compare. a foc0b strobe will not generate any interrup t, nor will it clear the timer in ctc mode using ocr0b as top. the foc0b bit is always read as zero. ? bits 5:4 ? res: reserved bits these bits are reserved bits and will always read as zero. ? bit 3 ? wgm02: waveform generation mode see the description in the ?tccr0a ? timer/counter control register a? on page 130. ? bits 2:0 ? cs02:0: clock select the three clock select bits select the clock source to be used by the timer/counter, see table 80 on page 134. bit 7 6 5 4 3 2 1 0 0x25 (0x45) foc0a foc0b ? ? wgm02 cs02 cs01 cs00 tccr0b read/ w rite ww rrr/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 134 atmega640/1280/1281/2560/2561 2549k?avr?01/07 if external pin modes are used for the timer/counter0, transitions on the t0 pin will clock the counter even if the pin is configured as an output. this feature allows software control of the counting. tcnt0 ? timer/counter register the timer/counter register gives direct access, both for read and write operations, to the timer/counter unit 8-bit counter. w riting to the tc n t0 register blocks (removes) the compare match on the following timer clock. modifying the counter (tc n t0) while the counter is running, introduces a risk of missing a compare match between tc n t0 and the ocr0x registers. ocr0a ? output compare register a the output compare register a contains an 8-bit value that is continuously compared with the counter value (tc n t0). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc0a pin. ocr0b ? output compare register b the output compare register b contains an 8-bit value that is continuously compared with the counter value (tc n t0). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc0b pin. table 80. clock select bit description cs02 cs01 cs00 description 000 n o clock source (timer/counter stopped) 001clk i/o /( n o prescaling) 010clk i/o /8 (from prescaler) 011clk i/o /64 (from prescaler) 100clk i/o /256 (from prescaler) 101clk i/o /1024 (from prescaler) 1 1 0 external clock source on t0 pin. clock on falling edge. 1 1 1 external clock source on t0 pin. clock on rising edge. bit 76543210 0x26 (0x46) tcnt0[7:0] tcnt0 read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 0x27 (0x47) ocr0a[7:0] ocr0a read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 0x28 (0x48) ocr0b[7:0] ocr0b read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 135 atmega640/1280/1281/2560/2561 2549k?avr?01/07 timsk0 ? timer/counter interrupt mask register ? bits 7:3, 0 ? res: reserved bits these bits are reserved bits and will always read as zero. ? bit 2 ? ocie0b: timer/counter output compare match b interrupt enable w hen the ocie0b bit is written to one, and the i-bit in the status register is set, the timer/counter compare match b interrupt is enabled. the corresponding interrupt is executed if a compare match in timer/counter occurs, i.e., when the ocf0b bit is set in the timer/counter interrupt flag register ? tifr0. ? bit 1 ? ocie0a: timer/counter0 output compare match a interrupt enable w hen the ocie0a bit is written to one, and the i-bit in the status register is set, the timer/counter0 compare match a interrupt is enabled. the corresponding interrupt is executed if a compare match in timer/counter0 occurs, i.e., when the ocf0a bit is set in the timer/counter 0 interrupt flag register ? tifr0. ? bit 0 ? toie0: timer/counter0 overflow interrupt enable w hen the toie0 bit is written to one, and the i-bit in the status register is set, the timer/counter0 overflow interrupt is enable d. the corresponding interrupt is executed if an overflow in timer/counter0 occurs, i.e., when the tov0 bit is set in the timer/counter 0 interrupt flag register ? tifr0. tifr0 ? timer/counter 0 interrupt flag register ? bits 7:3, 0 ? res: reserved bits these bits are reserved bits and will always read as zero. ? bit 2 ? ocf0b: timer/counter 0 output compare b match flag the ocf0b bit is set when a compare match occurs between the timer/counter and the data in ocr0b ? output compare register0 b. ocf0b is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, ocf0b is cleared by writing a logic one to the flag. w hen the i-bit in sreg, ocie0b (timer/counter compare b match interrupt enable), and ocf0b are set, the timer/counter compare match interrupt is executed. ? bit 1 ? ocf0a: timer/counter 0 output compare a match flag the ocf0a bit is set when a compare match occurs between the timer/counter0 and the data in ocr0a ? output compare register0. ocf0a is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, ocf0a is cleared by writing a logic one to the flag. w hen the i-bit in sreg, ocie0a (timer/counter0 compare match interrupt enable), and ocf0a are set, the timer/counter0 compare match interrupt is executed. bit 76543 210 (0x6e) ?????ocie0bocie0atoie0timsk0 read/ w riterrrrrr/ w r/ w r/ w initial value00000 000 bit 76543210 0x15 (0x35) ?????ocf0bocf0a tov0 tifr0 read/ w riterrrrrr/ w r/ w r/ w initial value00000000 136 atmega640/1280/1281/2560/2561 2549k?avr?01/07 ? bit 0 ? tov0: timer/counter0 overflow flag the bit tov0 is set when an overflow occu rs in timer/counter0. tov0 is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, tov0 is cleared by writing a logic one to the flag. w hen the sreg i-bit, toie0 (timer/counter0 overflow interrupt enable), and tov0 are set, the timer/counter0 overflow interrupt is executed. the setting of this flag is dependent of the w gm02:0 bit setting. refer to table 79, ? w aveform generation mode bit description? on page 132. 137 atmega640/1280/1281/2560/2561 2549k?avr?01/07 16-bit timer/counter (timer /counter 1, 3, 4, and 5) the 16-bit timer/counter unit allows accura te program execution timing (event man- agement), wave generation, and signal timing measurement. the main features are: ? true 16-bit design (i.e., allows 16-bit pwm) ? three independent output compare units ? double buffered out put compare registers ? one input capture unit ? input capture noise canceler ? clear timer on compar e match (auto reload) ? glitch-free, phase correct pu lse width modulator (pwm) ? variable pwm period ? frequency generator ? external event counter ? twenty independent interrupt sources (tov1, ocf1a, ocf1b, ocf1c, icf1, tov3, ocf3a, ocf3b, ocf3c, icf3, tov4, ocf4 a, ocf4b, ocf4c, icf4, tov5, ocf5a, ocf5b, ocf5c and icf5) overview most register and bit references in this se ction are written in general form. a lower case ?n? replaces the timer/counter number, and a lower case ?x? replaces the output com- pare unit channel. however, when using the register or bit defines in a program, the precise form must be used, i.e., tc n t1 for accessing timer/counter1 counter value and so on. a simplified block diagram of the 16-bit time r/counter is shown in figure 48. for the actual placement of i/o pins, see ?tqfp-pinout atmega640/1280/2560? on page 2 and ?pinout atmega1281/2561? on page 4. cpu accessible i/o registers, including i/o bits and i/o pins, are shown in bold. the device-s pecific i/o register and bit locations are listed in the ?register description? on page 160. the power reduction timer/counter1 bit, prtim1, in ?prr0 ? power reduction regis- ter 0? on page 55 must be written to zero to enable timer/counter1 module. the power reduction timer/counter3 bit, prtim3, in ?prr1 ? power reduction regis- ter 1? on page 56 must be written to zero to enable timer/counter3 module. the power reduction timer/counter4 bit, prtim4, in ?prr1 ? power reduction regis- ter 1? on page 56 must be written to zero to enable timer/counter4 module. the power reduction timer/counter5 bit, prtim5, in ?prr1 ? power reduction regis- ter 1? on page 56 must be written to zero to enable timer/counter5 module. timer/counter4 and timer/counter5 only have full functionality in the atmega640/1280/2560. input capture and output compare are not available in the atmega1281/2561. 138 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 48. 16-bit timer/counter block diagram (1) n ote: 1. refer to figure 1 on page 2, table 41 on page 92, and table 47 on page 96 for timer/counter1 and 3 and 3 pin placement and description. registers the timer/counter (tc n tn), output compare registers (ocrna/b/c), and input cap- ture register (icrn) are all 16-bit registers. special procedures must be followed when accessing the 16-bit registers. these procedur es are described in the section ?access- ing 16-bit registers? on page 139. the timer/counter control registers (tccrna/b/c) are 8-bit registers and have no cpu access restrictions. interrupt requests (shorten as int.req.) signals are all visible in the timer interrupt flag register (tifrn). all interrupts are individually masked with the timer interrupt mask register (timskn). tifrn and timskn are not shown in the figure since these registers are shared by other timer units. the timer/counter can be clocked internally, via the prescaler, or by an external clock source on the tn pin. the clock select logic block controls which clock source and edge the timer/counter uses to increment (or decrement) its value. the timer/counter is inactive when no clock source is selected. the output from the clock select logic is referred to as the timer clock (clk t n ). the double buffered output compare registers (ocrna/b/c) are compared with the timer/counter value at all time. the result of the compare can be used by the w aveform generator to generate a p w m or variable frequency output on the output compare pin (ocna/b/c). see ?o utput compare units? on page 146.. the co mpare match event will icfn (int.req.) tovn (int.req.) clock select timer/counter databus icrn = = = tcntn waveform generation waveform generation waveform generation ocna ocnb ocnc noise canceler icpn = fixed top values edge detector control logic = 0 top bottom count clear direction ocfna (int.req.) ocfnb (int.req.) ocfnc (int.req.) tccrna tccrnb tccrnc ( from analog comparator ouput ) tn edge detector ( from prescaler ) tclk ocrnc ocrnb ocrna 139 atmega640/1280/1281/2560/2561 2549k?avr?01/07 also set the compare match flag (ocfna/b/c) which can be used to generate an out- put compare interrupt request. the input capture register can capture the timer/counter value at a given external (edge triggered) event on either the input capture pin (icpn) or on the analog compar- ator pins (see ?ac ? analog comparator? on page 275.) the input capture unit includes a digital filtering unit ( n oise canceler) for reducing the chance of capturing noise spikes. the top value, or maximum timer/counter value, can in some modes of operation be defined by either the ocrna register, the icrn register, or by a set of fixed values. w hen using ocrna as top value in a p w m mode, the ocrna register can not be used for generating a p w m output. however, th e top value will in this case be double buffered allowing the top value to be changed in run time. if a fixed top value is required, the icrn register can be used as an alternative, freeing the ocrna to be used as p w m output. definitions the following definitions are used extensively throughout the document: accessing 16-bit registers the tc n tn, ocrna/b/c, and icrn are 16-bit registers that can be accessed by the avr cpu via the 8-bit data bus. the 16-bit register must be byte accessed using two read or write operations. each 16-bit timer has a single 8-bit register for temporary stor- ing of the high byte of the 16-bit access . the same temporary register is shared between all 16-bit registers within each 16-bit timer. accessing the low byte triggers the 16-bit read or write operation. w hen the low byte of a 16-bit register is written by the cpu, the high byte stored in the temporary register, and the low byte written are both copied into the 16-bit register in the same clock cycle. w hen the low byte of a 16-bit reg- ister is read by the cpu, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as the low byte is read. n ot all 16-bit accesses uses the temporary register for the high byte. reading the ocrna/b/c 16-bit registers does not involve using the temporary register. to do a 16-bit write, the high byte must be written before the low byte. for a 16-bit read, the low byte must be read before the high byte. the following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. the same principle can be used directly for accessing the ocrna/b/c and icrn registers. n ote that when using ?c?, the compiler handles the 16-bit access. table 81. definitions bottom the counter reaches the bottom when it becomes 0x0000. max the counter reaches its max imum when it becomes 0xffff (decimal 65535). top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be assigned to be one of the fixed values: 0x00ff, 0x01ff, or 0x03ff, or to the value stored in the ocrna or icrn register. the assignment is dependent of the mode of operation. 140 atmega640/1280/1281/2560/2561 2549k?avr?01/07 n ote: 1. see ?about code examples? on page 9. the assembly code example returns the tc n tn value in the r17:r16 register pair. it is important to notice that accessing 16-bit registers are atomic operations. if an inter- rupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit timer registers, then the result of the access outside the interrupt will be corrupted. therefore, when both the main code and the interrupt code update the temporary regis- ter, the main code must disable the interrupts during the 16-bit access. assembly code examples (1) ... ; set tcntn to 0x01ff ldi r17,0x01 ldi r16,0xff out tcntnh,r17 out tcntnl,r16 ; read tcntn into r17:r16 in r16,tcntnl in r17,tcntnh ... c code examples (1) unsigned int i; ... /* set tcntn to 0x01ff */ tcntn = 0x1ff; /* read tcntn into i */ i = tcntn; ... 141 atmega640/1280/1281/2560/2561 2549k?avr?01/07 the following code examples show how to do an atomic read of the tc n tn register contents. reading any of the ocrna/b/c or icrn registers can be done by using the same principle. n ote: 1. see ?about code examples? on page 9. the assembly code example returns the tc n tn value in the r17:r16 register pair. assembly code example (1) tim16_readtcntn: ; save global interrupt flag in r18,sreg ; disable interrupts cli ; read tcntn into r17:r16 in r16,tcntnl in r17,tcntnh ; restore global interrupt flag out sreg,r18 ret c code example (1) unsigned int tim16_readtcntn( void ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ __disable_interrupt(); /* read tcntn into i */ i = tcntn; /* restore global interrupt flag */ sreg = sreg; return i; } 142 atmega640/1280/1281/2560/2561 2549k?avr?01/07 the following code examples show how to do an atomic write of the tc n tn register contents. w riting any of the ocrna/b/c or icrn registers can be done by using the same principle. n ote: 1. see ?about code examples? on page 9. the assembly code example requires that the r17:r16 register pair contains the value to be written to tc n tn. reusing the temporary high byte register if writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. however, note that the same rule of atomic operation described pr eviously also applies in this case. assembly code example (1) tim16_writetcntn: ; save global interrupt flag in r18,sreg ; disable interrupts cli ; set tcntn to r17:r16 out tcntnh,r17 out tcntnl,r16 ; restore global interrupt flag out sreg,r18 ret c code example (1) void tim16_writetcntn( unsigned int i ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ __disable_interrupt(); /* set tcntn to i */ tcntn = i; /* restore global interrupt flag */ sreg = sreg; } 143 atmega640/1280/1281/2560/2561 2549k?avr?01/07 timer/counter clock sources the timer/counter can be clocked by an intern al or an external clock source. the clock source is selected by the clock sele ct logic which is controlled by the clock select (csn2:0) bits located in the timer/counter cont rol register b (tccrnb). for details on clock sources and prescaler, see ?timer/counter 0, 1, 3, 4, and 5 prescaler? on page 172. counter unit the main part of the 16-bit timer/counter is the programmable 16-bit bi-directional counter unit. figure 49 shows a block diagram of the counter and its surroundings. figure 49. counter unit block diagram signal description (internal signals): count increment or decrement tc n tn by 1. direction select between increment and decrement. clear clear tc n tn (set all bits to zero). clk t n timer/counter clock. top signalize that tc n tn has reached maximum value. bottom signalize that tc n tn has reached minimum value (zero). the 16-bit counter is mapped into two 8-bit i/o memory locations: counter high (tc n tnh) containing the upper eight bits of the counter, and counter low (tc n tnl) containing the lower eight bits. the tc n tnh register can only be indirectly accessed by the cpu. w hen the cpu does an access to the tc n tnh i/o location, the cpu accesses the high byte temporary register (temp). the temporary register is updated with the tc n tnh value when the tc n tnl is read, and tc n tnh is updated with the temporary register value when tc n tnl is written. this allows the cpu to read or write the entire 16-bit counter value within one cl ock cycle via the 8-bit data bus. it is impor- tant to notice that there are special cases of writing to the tc n tn register when the counter is counting that will give unpredictable results. the special cases are described in the sections where they are of importance. depending on the mode of operation used, the counter is cleared, incremented, or dec- remented at each timer clock (clk t n ). the clk t n can be generated from an external or internal clock source, selected by the clock select bits (csn2:0). w hen no clock source is selected (csn2:0 = 0) the timer is stopped. however, the tc n tn value can be accessed by the cpu, independent of whether clk t n is present or not. a cpu write over- rides (has priority over) all counter clear or count operations. the counting sequence is determined by the setting of the waveform generation mode bits ( w gmn3:0) located in the timer/counter control registers a and b (tccrna and tccrnb). there are close connections between how the counter behaves (counts) and temp (8-bit) data bus (8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) control logic count clear direction tovn (int.req.) clock select top bottom tn edge detector ( from prescaler ) clk tn 144 atmega640/1280/1281/2560/2561 2549k?avr?01/07 how waveforms are generated on the output compare outputs ocnx. for more details about advanced counting sequences and waveform generation, see ?modes of opera- tion? on page 149. the timer/counter overflow flag (tovn) is set according to the mode of operation selected by the w gmn3:0 bits. tovn can be used for generating a cpu interrupt. input capture unit the timer/counter incorporates an input capture unit that can capture external events and give them a time-stamp indicating time of occurrence. the external signal indicating an event, or multiple events, can be applied via the icpn pin or alternatively, for the timer/counter1 only, via the analog comparator unit. the time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. alter- natively the time-stamps can be used for creating a log of the events. the input capture unit is illustrated by the block diagram shown in figure 50. the ele- ments of the block diagram that are not directly a part of the input capture unit are gray shaded. the small ?n? in register and bit names indicates the timer/counter number. figure 50. input capture unit block diagram n ote: the analog comparator ou tput (aco) can only trigger the timer/counter1 icp ? not timer/counter3, 4 or 5. w hen a change of the logic level (an event) occurs on the input capture pin (icpn), alternatively on the analog comparator output (aco), and this change confirms to the setting of the edge detector , a capture will be triggered. w hen a capture is triggered, the 16-bit value of the counter (tc n tn) is written to the input capture register (icrn). the input capture flag (icfn) is set at the same system clock as the tc n tn value is copied into icrn register. if enabled (ticien = 1), the input capture flag generates an input capture interrupt. the icfn flag is automati cally cleared when the interrupt is executed. alternatively the icfn flag can be cleared by so ftware by writing a logical one to its i/o bit location. icfn (int.req.) analog comparator write icrn (16-bit register) icrnh (8-bit) noise canceler icpn edge detector temp (8-bit) data bus (8-bit) icrnl (8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) acic* icnc ices aco* 145 atmega640/1280/1281/2560/2561 2549k?avr?01/07 reading the 16-bit value in the input capture register (icrn) is done by first reading the low byte (icrnl) and then the high byte (icrnh). w hen the low byte is read the high byte is copied into the high byte temporary register (temp). w hen the cpu reads the icrnh i/o location it will a ccess the temp register. the icrn register can only be written when using a w aveform generation mode that utilizes the icrn register for defining the counter?s top value. in these cases the waveform generation mode ( w gmn3:0) bits must be set before the top value can be written to the icrn register. w hen writing the icrn register the high byte must be writ- ten to the icrnh i/o location before the low byte is written to icrnl. for more information on how to access the 16-bit registers refer to ?accessing 16-bit registers? on page 139. input capture trigger source the main trigger source for the input capture unit is the input capture pin (icpn). timer/counter1 can alternatively use the analog comparator output as trigger source for the input capture unit. the analog comparator is selected as trigger source by setting the analog comparator input capture (acic) bit in the analog comparator control and status register (acsr). be aware that changing trigger source can trigger a capture. the input capture flag must therefore be cleared after the change. both the input capture pin (icpn) and the analog comparator output (aco) inputs are sampled using the same technique as for the tn pin (figure 61 on page 172). the edge detector is also identical. ho wever, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles. n ote that the input of the noise canceler and edge detector is always enabled unless the timer/counter is set in a w aveform generation mode that uses icrn to define top. an input capture can be trig gered by software by controllin g the port of the icpn pin. noise canceler the noise canceler improves noise immunity by using a simple digital filtering scheme. the noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. the noise canceler is enabled by setting the input capture noise canceler (ic n cn) bit in timer/counter cont rol register b (tccrnb). w hen enabled the noise canceler intro- duces additional four system clock cycles of delay from a change applied to the input, to the update of the icrn register. the noise canceler uses the system clock and is there- fore not affected by the prescaler. using the input capture unit the main challenge when using the input capture unit is to assign enough processor capacity for handling the incoming events. the time between two events is critical. if the processor has not read the captured value in the icrn register before the next event occurs, the icrn will be overwritten with a new va lue. in this case the result of the cap- ture will be incorrect. w hen using the input capture interrupt, the icrn register should be read as early in the interrupt handler routine as possible. even though the input capture interrupt has rela- tively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. using the input capture unit in any mode of operation when the top value (resolution) is actively changed during operation, is not recommended. measurement of an external signal?s duty cycle requires that the trigger edge is changed after each capture. changing the edge sensing must be done as early as possible after the icrn register has been read. after a change of the edge, the input capture flag 146 atmega640/1280/1281/2560/2561 2549k?avr?01/07 (icfn) must be cleared by software (writing a logical one to the i/o bit location). for measuring frequency only, the clearing of the icfn flag is not required (if an interrupt handler is used). output compare units the 16-bit comparator continuously compares tc n tn with the output compare regis- ter (ocrnx). if tc n t equals ocrnx the comparator signals a match. a match will set the output compare flag (ocfnx) at the next timer cl ock cycle. if enabled (ocienx = 1), the output compare flag generates an output compare interrupt. the ocfnx flag is automatically cleared when the interrup t is executed. altern atively the ocfnx flag can be cleared by software by writing a logical one to its i/o bit location. the w aveform generator uses the match signal to generate an output according to operating mode set by the waveform generation mode ( w gmn3:0) bits and compare output mode (comnx1:0) bits. the top and bottom signals are used by the w aveform generator for handling the special cases of the extreme values in some modes of operation (see ?modes of operation? on page 149.) a special feature of output compare unit a allows it to define the timer/counter top value (i.e., counter resolution). in addition to the counter resolution, the top value defines the period time for waveforms generated by the w aveform generator. figure 51 shows a block diagram of the output compare unit. the small ?n? in the regis- ter and bit names indicates the device number (n = n for timer/counter n), and the ?x? indicates output compare unit (a/b/c). the elements of the block diagram that are not directly a part of the output compare unit are gray shaded. figure 51. output compare unit, block diagram the ocrnx register is double buffered when using any of the twelve pulse width mod- ulation (p w m) modes. for the n ormal and clear timer on compare (ctc) modes of operation, the double buffering is disabled. the double buffering synchronizes the update of the ocrnx compare register to either top or bottom of the counting sequence. the synchronization prevents the occurrence of odd-length, non-symmetrical p w m pulses, thereby making the output glitch-free. ocfnx (int.req.) = (16-bit comparator ) ocrnx buffer (16-bit register) ocrnxh buf. (8-bit) ocnx temp (8-bit) data bus (8-bit) ocrnxl buf. (8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) comnx1:0 wgmn3:0 ocrnx (16-bit register) ocrnxh (8-bit) ocrnxl (8-bit) waveform generator top bottom 147 atmega640/1280/1281/2560/2561 2549k?avr?01/07 the ocrnx register access may seem complex, but this is not case. w hen the double buffering is enabled, the cpu has access to the ocrnx buffer register, and if double buffering is disabled the cpu will access the ocrnx directly. the co ntent of the ocr1x (buffer or compare) register is only changed by a write operation (the timer/counter does not update this register automatically as the tc n t1 and icr1 register). therefore ocr1x is not read via the high byte temporary register (temp). however, it is a good practice to read the low byte first as when accessing other 16-bit registers. w riting the ocrnx registers must be done via the temp register since the compare of all 16 bits is done continuously. the high byte (o crnxh) has to be written first. w hen the high byte i/o location is written by the cpu, the temp register will be updated by the value written. then when the low by te (ocrnxl) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the ocrnx buffer or ocrnx compare reg- ister in the same system clock cycle. for more information of how to access the 16-bit registers refer to ?accessing 16-bit registers? on page 139. force output compare in non-p w m w aveform generation modes, the match output of the comparator can be forced by writing a one to the force output compare (focnx) bit. forcing compare match will not set the ocfnx flag or reload /clear the timer, but the ocnx pin will be updated as if a real compare match had occurred (the comn1:0 bits settings define whether the ocnx pin is set, cleared or toggled). compare match blocking by tcntn write all cpu writes to the tc n tn register will block any comp are match that occurs in the next timer clock cycle, even when the timer is stopped. this feature allows ocrnx to be initialized to the same value as tc n tn without triggering an interrupt when the timer/counter clock is enabled. using the output compare unit since writing tc n tn in any mode of operation will block all compare matches for one timer clock cycle, there are ri sks involved when changing tc n tn when using any of the output compare channels, independent of whether the timer/counter is running or not. if the value written to tc n tn equals the ocrnx value, the compare match will be missed, resulting in incorrect waveform generation. do not write the tc n tn equal to top in p w m modes with variable top values. the compare match for the top will be ignored and the counter will continue to 0xffff . similarly, do not write the tc n tn value equal to bottom when the counter is downcounting. the setup of the ocnx should be performed before setting the data direction register for the port pin to output. the easiest way of setting the ocnx value is to use the force output compare (focnx) strobe bits in n ormal mode. the ocnx register keeps its value even when changing between w aveform generation modes. be aware that the comnx1:0 bits are not double buffered together with the compare value. changing the comnx1:0 bi ts will take effect immediately. 148 atmega640/1280/1281/2560/2561 2549k?avr?01/07 compare match output unit the compare output mode (comnx1:0) bits have two functions. the w aveform gener- ator uses the comnx1:0 bits for defining the output compare (ocnx) state at the next compare match. secondly the comnx1:0 bits control the ocnx pin output source. fig- ure 52 shows a simplified schematic of the logic affected by the comnx1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the parts of the general i/o port control registers (ddr and port) that are affected by the comnx1:0 bits are shown. w hen referring to the ocnx state, the reference is for the internal ocnx register, not the ocnx pin. if a system reset occur, the ocnx register is reset to ?0?. figure 52. compare match output unit, schematic the general i/o port function is overridden by the output compare (ocnx) from the w aveform generator if either of the comnx1:0 bits are set. however, the ocnx pin direction (input or output ) is still controlled by the data direction register (ddr) for the port pin. the data direction register bit for the ocnx pin (ddr_ocnx) must be set as output before the ocnx value is visible on th e pin. the port override function is generally independent of the w aveform generation mode, but there are some exceptions. refer to table 83, table 84 and table 85 for details. the design of the output compare pin logic allows initialization of the ocnx state before the output is enabled. n ote that some comnx1:0 bit settings are reserved for certain modes of operation. see ?register description? on page 160. the comnx1:0 bits have no effect on the input capture unit. compare output mode and waveform generation the w aveform generator uses the comnx1:0 bits differently in normal, ctc, and p w m modes. for all modes, setting the comnx1:0 = 0 tells the w aveform generator that no action on the ocnx register is to be performed on the next compare match. for com- pare output actions in the non-p w m modes refer to table 83 on page 161. for fast p w m mode refer to table 84 on page 161, and for phase correct and phase and fre- quency correct p w m refer to table 85 on page 161. port ddr dq dq ocnx pin ocnx dq waveform generator comnx1 comnx0 0 1 data b u s focnx clk i/o 149 atmega640/1280/1281/2560/2561 2549k?avr?01/07 a change of the comnx1:0 bits state will have effect at the first co mpare match after the bits are written. for non-p w m modes, the action can be forced to have immediate effect by using the focnx strobe bits. modes of operation the mode of operation, i.e., the behavior of the timer/counter and the output compare pins, is defined by the combination of the waveform generation mode ( w gmn3:0) and compare output mode (comnx1:0) bits. the compare output mode bits do not affect the counting sequence, while the w aveform generation mode bits do. the comnx1:0 bits control whether the p w m output generated should be inverted or not (inverted or non-inverted p w m). for non-p w m modes the comnx1:0 bits control whether the out- put should be set, cleared or toggle at a compare match (see ?compare match output unit? on page 148.) n ote: 1. the ctcn and p w mn1:0 bit definition names are obsolete. use the w gm n2:0 definitions. however, the functionality and location of these bits are compatible with previous versions of the timer. for detailed timing information refer to ?timer/counter timing diagrams? on page 157. table 82. w aveform generation mode bit description (1) mode wgmn3 wgmn2 (ctcn) wgmn1 (pwmn1) wgmn0 (pwmn0) timer/counter mode of operation top update of ocrn x at tovn flag set on 00 0 0 0 n ormal 0xffff immediate max 10 0 0 1p w m, phase correct, 8-bit 0x00ff top bottom 20 0 1 0p w m, phase correct, 9-bit 0x01ff top bottom 30 0 1 1p w m, phase correct, 10-bit 0x03ff top bottom 4 0 1 0 0 ctc ocrna immediate max 50 1 0 1fast p w m, 8-bit 0x00ff bottom top 60 1 1 0fast p w m, 9-bit 0x01ff bottom top 70 1 1 1fast p w m, 10-bit 0x03ff bottom top 81 0 0 0p w m, phase and frequency correct icrn bottom bottom 91 0 0 1p w m,phase and frequency correct ocrna bottom bottom 101010p w m, phase correct icrn top bottom 111011p w m, phase correct ocrna top bottom 12 1 1 0 0 ctc icrn immediate max 13 1 1 0 1 (reserved) ? ? ? 141110fast p w m icrn bottom top 151111fast p w m ocrna bottom top 150 atmega640/1280/1281/2560/2561 2549k?avr?01/07 normal mode the simplest mode of operation is the normal mode ( w gmn3:0 = 0). in this mode the counting direction is always up (incrementing), and no counter clear is performed. the counter simply overruns when it passes its maximum 16-bit value (max = 0xffff) and then restarts from the bottom (0x0000). in normal operation the timer/counter over- flow flag (tovn) will be set in the same timer clock cycle as the tc n tn becomes zero. the tovn flag in this case behaves like a 17th bit, except that it is only set, not cleared. however, combined with the timer overflow interrupt that automatically clears the tovn flag, the timer resolution can be increased by software. there are no special cases to consider in the n ormal mode, a new counter value can be written anytime. the input capture unit is easy to use in n ormal mode. however, observe that the maxi- mum interval between the external events must not exceed the resolution of the counter. if the interval between events are too long, the timer overflow interrupt or the prescaler must be used to extend the resolution for the capture unit. the output compare units can be used to generate interrupts at some given time. using the output compare to generate waveforms in n ormal mode is not recommended, since this will occupy too much of the cpu time. clear timer on compare match (ctc) mode in clear timer on compare or ctc mode ( w gmn3:0 = 4 or 12), the ocrna or icrn register are used to manipulate the counte r resolution. in ctc mode the counter is cleared to zero when the counter value (tc n tn) matches either the ocrna ( w gmn3:0 = 4) or the icrn ( w gmn3:0 = 12). the ocrna or icrn define the top value for the counter, hence also its resolution. this mode allows greater control of the compare match output frequency. it also simplifies th e operation of counting external events. the timing diagram for the ctc mode is shown in figure 53. the counter value (tc n tn) increases until a compare match occurs with either ocrna or icrn, and then counter (tc n tn) is cleared. figure 53. ctc mode, timing diagram an interrupt can be generated at each time the counter value reaches the top value by either using the ocfna or icfn flag according to the register used to define the top value. if the interrupt is enabled, the interrupt handler routine can be used for updating the top value. however, changing the top to a value close to bottom when the counter is running with none or a low prescaler value must be done with care since the ctc mode does not have the double buffering feature. if the new value written to ocrna or icrn is lower th an the current value of tc n tn, the counter will miss the com- pare match. the counter will then have to count to its maximum value (0xffff) and wrap around starting at 0x0000 before the compare match can occur. in many cases this feature is not desira ble. an alternative will then be to use the fast p w m mode using tcntn ocna (toggle) ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 4 period 2 3 (comna1:0 = 1) 151 atmega640/1280/1281/2560/2561 2549k?avr?01/07 ocrna for defining top ( w gmn3:0 = 15) since the ocrna then will be double buffered. for generating a waveform output in ctc mode, the ocna output can be set to toggle its logical level on each compare match by setting the compare output mode bits to tog- gle mode (comna1:0 = 1). the ocna value w ill not be visible on the port pin unless the data direction for the pin is set to output (ddr_ocna = 1). the waveform generated will have a maximum frequency of f oc n a = f clk_i/o /2 when ocrna is set to zero (0x0000). the waveform frequency is defined by the following equation: the n variable represents the prescaler factor (1, 8, 64, 256, or 1024). as for the n ormal mode of operation, the tovn flag is set in the same timer clock cycle that the counter counts from max to 0x0000. fast pwm mode the fast pulse width modulation or fast p w m mode ( w gmn3:0 = 5, 6, 7, 14, or 15) pro- vides a high frequency p w m waveform generation option. the fast p w m differs from the other p w m options by its single-slope operation. the counter counts from bottom to top then restarts from bottom. in non-inverting compare output mode, the output compare (ocnx) is cleared on the compare match between tc n tn and ocrnx, and set at bottom. in inverting compare output mode output is set on compare match and cleared at bottom. due to the single-slope operation, the operating frequency of the fast p w m mode can be twice as high as the phase correct and phase and frequency correct p w m modes that use dual-slope operation. this high frequency makes the fast p w m mode well suited for power regulation, rectification, and dac applications. high frequency allows physically small sized external components (coils, capacitors), hence reduces total system cost. the p w m resolution for fast p w m can be fixed to 8-, 9-, or 10-bit, or defined by either icrn or ocrna. the minimum resolution allowed is 2-bit (icrn or ocrna set to 0x0003), and the maximum resolution is 16-bit (icrn or ocrna set to max). the p w m resolution in bits can be calculated by using the following equation: in fast p w m mode the counter is incremented until the counter value matches either one of the fixed values 0x00ff, 0x01ff, or 0x03ff ( w gmn3:0 = 5, 6, or 7), the value in icrn ( w gmn3:0 = 14), or th e value in ocrna ( w gmn3:0 = 15). the counter is then cleared at the following timer clock cycle. the timing diagram for the fast p w m mode is shown in figure 54. the figure shows fast p w m mode when ocrna or icrn is used to define top. the tc n tn value is in the timing diag ram shown as a histogram for illus- trating the single-slope operation. the diagram includes non-inverted and inverted p w m outputs. the small horizontal line marks on the tc n tn slopes represent compare matches between ocrnx and tc n tn. the ocnx interrupt fl ag will be set when a com- pare match occurs. f ocna f clk_i/o 2 n 1 ocrna + () ?? -------------------------------------------------- - = r fpwm top 1 + () log 2 () log ---------------------------------- - = 152 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 54. fast p w m mode, timing diagram the timer/counter overflow flag (tovn) is set each time the counter reaches top. in addition the ocna or icfn flag is set at t he same timer clock cy cle as tovn is set when either ocrna or icrn is used for defining the top value. if one of the interrupts are enabled, the interrupt handler routine can be used for updating the top and com- pare values. w hen changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will never occur between the tc n tn and the ocrnx. n ote that when using fixed top values the unused bits are masked to zero when any of the ocrnx registers are written. the procedure for updating icrn differs from updating ocrna when used for defining the top value. the icrn register is not dou ble buffered. this means that if icrn is changed to a low value when the counter is running with none or a low prescaler value, there is a risk that the new icrn value written is lower than the current value of tc n tn. the result will then be that the counter will miss the comp are match at the top value. the counter will then have to count to t he max value (0xffff) and wrap around start- ing at 0x0000 before the compare match can occur. the ocrna register however, is double buffered. this feature allows the ocrna i/o location to be written anytime. w hen the ocrna i/o location is written the value written will be put into the ocrna buffer register. the ocrna compare register will then be updated with the value in the buffer register at the next timer clock cycle the tc n tn matches top. the update is done at the same timer clock cycle as the tc n tn is cleared and the tovn flag is set. using the icrn register for defining top works well when using fixed top values. by using icrn, the ocrna register is free to be used for generating a p w m output on ocna. however, if the base p w m frequency is actively changed (by changing the top value), using the ocrna as top is clearly a better choice due to its double buffer feature. in fast p w m mode, the compare units allow generation of p w m waveforms on the ocnx pins. setting the comnx1:0 bits to two will produce a non-inverted p w m and an inverted p w m output can be generated by setting the comnx1:0 to three (see table on page 161). the actual ocnx value will only be vi sible on the port pin if the data direction for the port pin is set as output (ddr_ocnx). the p w m waveform is generated by set- ting (or clearing) the ocnx register at the compare match between ocrnx and tc n tn, tcntn ocrnx / top update and tovn interrupt flag set and ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 7 period 2 3 4 5 6 8 ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) 153 atmega640/1280/1281/2560/2561 2549k?avr?01/07 and clearing (or setting) the ocnx register at the timer clock cycle the counter is cleared (changes from top to bottom). the p w m frequency for the output can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocrnx register represents special cases when generating a p w m waveform output in the fast p w m mode. if the ocrnx is set equal to bottom (0x0000) the output will be a na rrow spike for each top+1 timer clock cycle. setting the ocrnx equal to top will result in a constant high or low output (depending on the polar- ity of the output set by the comnx1:0 bits.) a frequency (with 50% duty cycle) waveform output in fast p w m mode can be achieved by setting ocna to toggle its logical leve l on each compare match (comna1:0 = 1). this applies only if ocr1a is used to define the top value ( w gm13:0 = 15). the wave- form generated will have a maximum frequency of f oc n a = f clk_i/o /2 when ocrna is set to zero (0x0000). this feature is similar to the ocna toggle in ctc mode, except the dou- ble buffer feature of the output compare unit is enabled in the fast p w m mode. phase correct pwm mode the phase correct pulse width modulation or phase correct p w m mode ( w gmn3:0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct p w m waveform generation option. the phase correct p w m mode is, like the phase and frequency correct p w m mode, based on a dual-slope operation. the counter counts repeatedly from bottom (0x0000) to top and then from top to bottom. in non-inverting compare output mode, the output compare (ocnx) is cleared on the compare match between tc n tn and ocrnx while upcounting, and set on the compare match while downcounting. in inverting output compare mode, the operation is inverted. the dual-slope operation has lower maximum operation frequency than single slope operation. however, due to the symmetric feature of the dual-slope p w m modes, these modes are preferred for motor control applications. the p w m resolution for the phase correct p w m mode can be fixed to 8-, 9-, or 10-bit, or defined by either icrn or ocrna. the minimum resolution allowed is 2-bit (icrn or ocrna set to 0x0003), and the maximum resolution is 16-bit (icrn or ocrna set to max). the p w m resolution in bits can be calculated by using the following equation: in phase correct p w m mode the counter is incremented until the counter value matches either one of the fixed values 0x00ff, 0x01ff, or 0x03ff ( w gmn3:0 = 1, 2, or 3), the value in icrn ( w gmn3:0 = 10), or th e value in ocrna ( w gmn3:0 = 11). the counter has then reached the top and changes the count direction. the tc n tn value will be equal to top for one timer clock cycle. the timing diagram for the phase correct p w m mode is shown on figure 55. the figure shows phase correct p w m mode when ocrna or icrn is used to define top. the tc n tn value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. the di agram includes non-inverted and inverted p w m outputs. the small horizontal line marks on the tc n tn slopes repre- sent compare matches between ocrnx and tc n tn. the ocnx interrupt flag will be set when a compare match occurs. f ocnxpwm f clk_i/o n 1 top + () ? ---------------------------------- - = r pcpwm top 1 + () log 2 () log ---------------------------------- - = 154 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 55. phase correct p w m mode, timing diagram the timer/counter overflow flag (tovn) is set each time the counter reaches bot- tom. w hen either ocrna or icrn is used for defining the top value, the ocna or icfn flag is set accordingly at the same timer clock cycle as the ocrnx registers are updated with the double buffer value (at top). the interrupt flags can be used to gen- erate an interrupt each time the counter reaches the top or bottom value. w hen changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will never occur between the tc n tn and the ocrnx. n ote that when using fixed top values, the unused bits are masked to zero when any of the ocrnx registers are written. as the third period shown in figure 55 illustrates, changing the top ac tively while the timer/ counter is running in the phase correct mode can result in an unsymmetrical output. the reason for this can be found in the time of update of the ocrnx register. since the ocrnx update occurs at top, the p w m period starts and ends at top. this implies that the length of the fall- ing slope is determined by the previous top value, while the length of the rising slope is determined by the new top value. w hen these two values differ the two slopes of the period will differ in length. the difference in length gives the unsymme trical result on the output. it is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the top value while the timer/counter is running. w hen using a static top value there are practically no differences between the two modes of operation. in phase correct p w m mode, the compare units allow generation of p w m waveforms on the ocnx pins. setting the comnx1:0 bi ts to two will produce a non-inverted p w m and an inverted p w m output can be generated by setting the comnx1:0 to three (see table 85 on page 161). the actual ocnx value will only be visible on the port pin if the data direction for the port pin is se t as output (ddr_ocnx). the p w m waveform is gener- ated by setting (or clearing) the ocnx regi ster at the compare match between ocrnx and tc n tn when the counter increments, and clearing (or setting) the ocnx register at compare match between ocrnx and tc n tn when the counter decrements. the p w m ocrnx/top update and ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 2 3 4 tovn interrupt flag set (interrupt on bottom) tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) 155 atmega640/1280/1281/2560/2561 2549k?avr?01/07 frequency for the output when using phase correct p w m can be calculated by the fol- lowing equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocrnx register represent special cases when generating a p w m waveform output in the phase correct p w m mode. if the ocrnx is set equal to bottom the output will be continuously low and if set equal to top the output will be continuously high for non-inverted p w m mode. for inverted p w m the output will have the opposite logic values. if ocr1a is used to define the top value ( w gm13:0 = 11) and com1a1:0 = 1, the oc1a output will toggle with a 50% duty cycle. phase and frequency correct pwm mode the phase and frequency correct pulse width modulation, or phase and frequency cor- rect p w m mode ( w gmn3:0 = 8 or 9) provides a high resolution phase and frequency correct p w m waveform generation option. the phase and frequency correct p w m mode is, like the phase correct p w m mode, based on a dual-slope operation. the counter counts repeatedly from bottom (0x0000) to top and then from top to bot- tom. in non-inverting compare output mode, the output compare (ocnx) is cleared on the compare match between tc n tn and ocrnx while upcounting, and set on the compare match while downcounting. in inverting compare output mode, the operation is inverted. the dual-slope operation gives a lower maximum operation frequency com- pared to the single-slope operation. however, due to the symmetric feature of the dual- slope p w m modes, these modes are preferred for motor control applications. the main difference between the phase correct, and the phase and frequency correct p w m mode is the time the ocrnx register is updated by the ocrnx buffer register, (see figure 55 and figure 56). the p w m resolution for the phase and frequency correct p w m mode can be defined by either icrn or ocrna. the minimum resolution allowed is 2-bit (icrn or ocrna set to 0x0003), and the maximum resolution is 16-bit (icrn or ocrna set to max). the p w m resolution in bits can be calculated using the following equation: in phase and frequency correct p w m mode the counter is incremented until the counter value matches either the value in icrn ( w gmn3:0 = 8), or the value in ocrna ( w gmn3:0 = 9). the counter has then reached the top and changes the count direc- tion. the tc n tn value will be equal to top for one timer clock cycle. the timing diagram for the phase correct and frequency correct p w m mode is shown on figure 56. the figure shows phase and frequency correct p w m mode when ocrna or icrn is used to define top. the tc n tn value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. the diagram includes non-inverted and inverted p w m outputs. the small horizontal line marks on the tc n tn slopes represent compare matches between ocrnx and tc n tn. the ocnx interrupt fl ag will be set when a com- pare match occurs. f ocnxpcpwm f clk_i/o 2 ntop ?? --------------------------- - = r pfcpwm top 1 + () log 2 () log ---------------------------------- - = 156 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 56. phase and frequency correct p w m mode, timing diagram the timer/counter overflow flag (tovn) is set at the same timer clock cycle as the ocrnx registers are updated with the double buffer value (at bottom). w hen either ocrna or icrn is used for defining the to p value, the ocna or icfn flag set when tc n tn has reached top. the interrupt flags can then be used to generate an interrupt each time the counter reaches the top or bottom value. w hen changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will never occur between the tc n tn and the ocrnx. as figure 56 shows the output generated is, in contrast to the phase correct mode, sym- metrical in all periods. since the ocrnx registers are updated at bottom, the length of the rising and the falling slopes will always be equal. this gives symmetrical output pulses and is therefore frequency correct. using the icrn register for defining top works well when using fixed top values. by using icrn, the ocrna register is free to be used for generating a p w m output on ocna. however, if the base p w m frequency is actively changed by changing the top value, using the ocrna as top is clearl y a better choice due to its double buffer feature. in phase and frequency correct p w m mode, the compare units allow generation of p w m waveforms on the ocnx pins. setting the comnx1:0 bits to two will produce a non-inverted p w m and an inverted p w m output can be generated by setting the comnx1:0 to three (see table 85 on page 161). the actual ocnx value will only be vis- ible on the port pin if the data direction for the port pin is set as output (ddr_ocnx). the p w m waveform is generated by setting (or clearing) the ocnx register at the compare match between ocrnx and tc n tn when the counter increments, and clearing (or set- ting) the ocnx register at compare match between ocrnx and tc n tn when the counter decrements. the p w m frequency for the output when using phase and fre- quency correct p w m can be calculated by the following equation: ocrnx/top updateand tovn interrupt flag set (interrupt on bottom) ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 2 3 4 tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) f ocnxpfcpwm f clk_i/o 2 ntop ?? --------------------------- - = 157 atmega640/1280/1281/2560/2561 2549k?avr?01/07 the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocrnx register represents special cases when generating a p w m waveform output in the phase correct p w m mode. if the ocrnx is set equal to bottom the output will be continuously low and if set equal to top the output will be set to high for non-inverted p w m mode. for inverted p w m the output will have the opposite logic values. if ocr1a is used to define the top value ( w gm13:0 = 9) and com1a1:0 = 1, the oc1a output will toggle with a 50% duty cycle. timer/counter timing diagrams the timer/counter is a synchronous design and the timer clock (clk tn ) is therefore shown as a clock enable signal in the followi ng figures. the figures include information on when interrupt flags are set, and when the ocrnx register is updated with the ocrnx buffer value (only for mo des utilizing double buffering ). figure 57 shows a timing diagram for the setting of ocfnx. figure 57. timer/counter timing diagram, setting of ocfnx, no prescaling figure 58 shows the same timing data, but with the prescaler enabled. figure 58. timer/counter timing diagram, setting of ocfnx, with prescaler (f clk_i/o /8) figure 59 shows the count sequence close to top in various modes. w hen using phase and frequency correct p w m mode the ocrnx register is updated at bottom. the timing diagrams will be th e same, but top should be replaced by bottom, top-1 by clk tn (clk i/o /1) ocfnx clk i/o ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) 158 atmega640/1280/1281/2560/2561 2549k?avr?01/07 bottom+1 and so on. the same renaming applies for modes that set the tovn flag at bottom. figure 59. timer/counter timing diagram, no prescaling figure 60 shows the same timing data, but with the prescaler enabled. tovn (fpwm) and icfn (if used as top) ocrnx (update at top) tcntn (ctc and fpwm) tcntn (pc and pfc pwm) top - 1 top top - 1 top - 2 old ocrnx value new ocrnx value top - 1 top bottom bottom + 1 clk tn (clk i/o /1) clk i/o 159 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 60. timer/counter timing diagram, with prescaler (f clk_i/o /8) tovn (fpwm) and icf n (if used as top) ocrnx (update at top) tcntn (ctc and fpwm) tcntn (pc and pfc pwm) top - 1 top top - 1 top - 2 old ocrnx value new ocrnx value top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o /8) 160 atmega640/1280/1281/2560/2561 2549k?avr?01/07 register description tccr1a ? timer/counter 1 control register a tccr3a ? timer/counter 3 control register a tccr4a ? timer/counter 4 control register a tccr5a ? timer/counter 5 control register a ? bit 7:6 ? comna1:0: compare output mode for channel a ? bit 5:4 ? comnb1:0: compare output mode for channel b ? bit 3:2 ? comnc1:0: compare output mode for channel c the comna1:0, comnb1:0, and comnc1:0 control the output compare pins (ocna, ocnb, and ocnc respectively) behavior. if one or both of the comna1:0 bits are writ- ten to one, the ocna output overrides the normal port functionality of the i/o pin it is connected to. if one or both of the comnb1:0 bits are written to one, the ocnb output overrides the normal port functionality of the i/o pin it is connected to. if one or both of the comnc1:0 bits are written to one, the ocnc output overrides the normal port func- tionality of the i/o pin it is connected to. however, note that the data direction register (ddr) bit corresponding to the ocna, ocnb or ocnc pin must be set in order to enable the output driver. w hen the ocna, ocnb or ocnc is connected to the pin, the function of the comnx1:0 bits is dependent of the w gmn3:0 bits setting. table 83 shows the comnx1:0 bit func- tionality when the w gmn3:0 bits are set to a normal or a ctc mode (non-p w m). ? bit 1:0 ? wgmn1:0: waveform generation mode combined with the w gmn3:2 bits found in the tccrnb register, these bits control the counting sequence of the counter, the source for maximum (top) counter value, and what type of waveform generation to be used, see table 82. modes of operation sup- ported by the timer/counter unit are: n ormal mode (counter), clear timer on compare match (ctc) mode, and three types of pulse w idth modulation (p w m) modes. for more information on the different modes, see ?modes of operation? on page 149. bit 76543210 (0x80) com1a1 com1a0 com1b1 com1b0 com1c1 com1c0 wgm11 wgm10 tccr1a read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 (0x90) com3a1 com3a0 com3b1 com3b0 com3c1 com3c0 wgm31 wgm30 tccr3a read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 (0xa0) com4a1 com4a0 com4b1 com4b0 com4c1 com4c0 wgm41 wgm40 tccr4a read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 (0x120) com5a1 com5a0 com5b1 com5b0 com5c1 com5c0 wgm51 wgm50 tccr5a read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 161 atmega640/1280/1281/2560/2561 2549k?avr?01/07 . table 84 shows the comnx1:0 bit functionality when the w gmn3:0 bits are set to the fast p w m mode. n ote: a special case occurs when ocrna/ocrnb/ocrnc equals top and comna1/comnb1/comnc1 is set. in this ca se the compare match is ignored, but the set or clear is done at bottom. see ?fast p w m mode? on page 151. for more details. table 85 shows the comnx1:0 bit functionality when the w gmn3:0 bits are set to the phase correct and frequency correct p w m mode. n ote: a special case occurs when ocrna/ocrnb/ocrnc equals top and comna1/comnb1//comnc1 is set. see ?phase correct p w m mode? on page 153. for more details. table 83. compare output mode, non-p w m comna1 comnb1 comnc1 comna0 comnb0 comnc0 description 00 n ormal port operation, ocna/ocnb/ocnc disconnected. 0 1 toggle ocna/ocnb/ocnc on compare match. 1 0 clear ocna/ocnb/ocnc on compare match (set output to low level). 1 1 set ocna/ocnb/ocnc on compare match (set output to high level). table 84. compare output mode, fast p w m comna1 comnb1 comnc1 comna0 comnb0 comnc0 description 00 n ormal port operation, ocna/ocnb/ocnc disconnected. 01 w gm13:0 = 14 or 15: toggle oc1a on compare match, oc1b and oc1c disconnected (normal port operation). for all other w gm1 settings, normal port operation, oc1a/oc1b/oc1c disconnected. 1 0 clear ocna/ocnb/ocnc on compare match, set ocna/ocnb/ocnc at bottom (non-inverting mode). 1 1 set ocna/ocnb/ocnc on compare match, clear ocna/ocnb/ocnc at bottom (inverting mode). table 85. compare output mode, phase correct and phase and frequency correct p w m comna1 comnb1 comnc1 comna0 comnb0 comnc0 description 00 n ormal port operation, ocna/ocnb/ocnc disconnected. 01 w gm13:0 =9 or 11: toggle oc1a on compare match, oc1b and oc1c disconnected (normal port operation). for all other w gm1 settings, normal port operation, oc1a/oc1b/oc1c disconnected. 1 0 clear ocna/ocnb/ocnc on compare match when up-counting. set ocna/ocnb/ocnc on compare match when downcounting. 1 1 set ocna/ocnb/ocnc on compare match when up-counting. clear ocna/ocnb/ocnc on compare match when downcounting. 162 atmega640/1280/1281/2560/2561 2549k?avr?01/07 tccr1b ? timer/counter 1 control register b tccr3b ? timer/counter 3 control register b tccr4b ? timer/counter 4 control register b tccr5b ? timer/counter 5 control register b ? bit 7 ? icncn: input capture noise canceler setting this bit (to one) activates the input capture n oise canceler. w hen the n oise canceler is activated, the input from the i nput capture pin (icpn) is filtered. the filter function requires four successive equal valued samples of the icpn pin for changing its output. the input capture is therefore delayed by four oscillator cycles when the noise canceler is enabled. ? bit 6 ? icesn: input capture edge select this bit selects which edge on the input capture pin (icpn) that is used to trigger a cap- ture event. w hen the icesn bit is written to zero, a falling (negative) edge is used as trigger, and when the icesn bit is written to one, a rising (positive) edge will trigger the capture. w hen a capture is triggered according to the icesn setting, the counter value is copied into the input capture register (icrn). t he event will also set the input capture flag (icfn), and this can be used to cause an input capture interrupt, if this interrupt is enabled. w hen the icrn is used as top value (see description of the w gmn3:0 bits located in the tccrna and the tccrnb register), t he icpn is disconnected and consequently the input capture function is disabled. ? bit 5 ? reserved bit this bit is reserved for future use. for ensuring compatibility with future devices, this bit must be written to zero when tccrnb is written. ? bit 4:3 ? wgmn3:2: waveform generation mode see tccrna register description. bit 76543210 (0x81) icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 tccr1b read/ w rite r/ w r/ w rr/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 (0x91) icnc3 ices3 ? wgm33 wgm32 cs32 cs31 cs30 tccr3b read/ w rite r/ w r/ w rr/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 (0xa1) icnc4 ices4 ? wgm43 wgm42 cs42 cs41 cs40 tccr4b read/ w rite r/ w r/ w rr/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 (0x121) icnc5 ices5 ? wgm53 wgm52 cs52 cs51 cs50 tccr5b read/ w rite r/ w r/ w rr/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 163 atmega640/1280/1281/2560/2561 2549k?avr?01/07 ? bit 2:0 ? csn2:0: clock select the three clock select bits select the clock so urce to be used by the timer/counter, see figure 57 and figure 58. if external pin modes are used for the timer/countern, transitions on the tn pin will clock the counter even if the pin is configured as an output. this feature allows software control of the counting. table 86. clock select bit description csn2 csn1 csn0 description 000 n o clock source. (timer/counter stopped) 001clk i/o /1 ( n o prescaling 010clk i/o /8 (from prescaler) 011clk i/o /64 (from prescaler) 100clk i/o /256 (from prescaler) 101clk i/o /1024 (from prescaler) 1 1 0 external clock source on tn pin. clock on falling edge 1 1 1 external clock source on tn pin. clock on rising edge 164 atmega640/1280/1281/2560/2561 2549k?avr?01/07 tccr1c ? timer/counter 1 control register c tccr3c ? timer/counter 3 control register c tccr4c ? timer/counter 4 control register c tccr5c ? timer/counter 5 control register c ? bit 7 ? focna: force outp ut compare for channel a ? bit 6 ? focnb: force outp ut compare for channel b ? bit 5 ? focnc: force outp ut compare for channel c the focna/focnb/focnc bits are only active when the w gmn3:0 bits specifies a non-p w m mode. w hen writing a logical one to the focna/focnb/focnc bit, an immediate compare match is forced on the waveform generation unit. the ocna/ocnb/ocnc output is changed according to its comnx1:0 bits setting. n ote that the focna/focnb/focnc bits are implemented as strobes. therefore it is the value present in the comnx1:0 bits that determine the effect of the forced compare. a focna/focnb/focnc stro be will not generate any interr upt nor will it clear the timer in clear timer on compare match (ctc) mode using ocrna as top. the focna/focnb/focnb bits are always read as zero. ? bit 4:0 ? reserved bits these bits are reserved for future use. for ensuring compatibility with future devices, these bits must be written to zero when tccrnc is written. bit 7654 3210 (0x82) foc1a foc1b foc1c ? ? ? ? ? tccr1c read/ w rite www rrrrr initial value 0 0 0 0 0 0 0 0 bit 7654 3210 (0x92) foc3a foc3b foc3c ? ? ? ? ? tccr3c read/ w rite www rrrrr initial value 0 0 0 0 0 0 0 0 bit 7654 3210 (0xa2) foc4a foc4b foc4c ? ? ? ? ? tccr4c read/ w rite www rrrrr initial value 0 0 0 0 0 0 0 0 bit 7654 3210 (0x122) foc5a foc5b foc3c ? ? ? ? ? tccr5c read/ w rite www rrrrr initial value 0 0 0 0 0 0 0 0 165 atmega640/1280/1281/2560/2561 2549k?avr?01/07 tcnt1h and tcnt1l ? timer/counter 1 tcnt3h and tcnt3l ? timer/counter 3 tcnt4h and tcnt4l ? timer/counter 4 tcnt5h and tcnt5l ? timer/counter 5 the two timer/counter i/o locations (tc n tnh and tc n tnl, combined tc n tn) give direct access, both for read and for write operations, to the timer/counter unit 16-bit counter. to ensure that both the high and low bytes are read and written simultaneously when the cpu accesses these registers, the access is performed using an 8-bit tempo- rary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 139. modifying the counter (tc n tn) while the counter is running introduces a risk of missing a compare match between tc n tn and one of the ocrnx registers. w riting to the tc n tn register blocks (removes) the compare match on the following timer clock for all compare units. bit 76543210 (0x85) tcnt1[15:8] tcnt1h (0x84) tcnt1[7:0] tcnt1l read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 (0x95) tcnt3[15:8] tcnt3h (0x94) tcnt3[7:0] tcnt3l read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 (0xa5) tcnt4[15:8] tcnt4h (0xa4) tcnt4[7:0] tcnt4l read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 (0x125) tcnt5[15:8] tcnt5h (0x124) tcnt5[7:0] tcnt5l read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 166 atmega640/1280/1281/2560/2561 2549k?avr?01/07 ocr1ah and ocr1al ? output compare register 1 a ocr1bh and ocr1bl ? output compare register 1 b ocr1ch and ocr1cl ? output compare register 1 c ocr3ah and ocr3al ? output compare register 3 a ocr3bh and ocr3bl ? output compare register 3 b ocr3ch and ocr3cl ? output compare register 3 c ocr4ah and ocr4al ? output compare register 4 a ocr4bh and ocr4bl ? output compare register 4 b bit 76543210 (0x89) ocr1a[15:8] ocr1ah (0x88) ocr1a[7:0] ocr1al read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 (0x8b) ocr1b[15:8] ocr1bh (0x8a) ocr1b[7:0] ocr1bl read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 (0x8d) ocr1c[15:8] ocr1ch (0x8c) ocr1c[7:0] ocr1cl read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 (0x99) ocr3a[15:8] ocr3ah (0x98) ocr3a[7:0] ocr3al read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 (0x9b) ocr3b[15:8] ocr3bh (0x9a) ocr3b[7:0] ocr3bl read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 (0x9d) ocr3c[15:8] ocr3ch (0x9c) ocr3c[7:0] ocr3cl read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 (0xa9) ocr4a[15:8] ocr4ah (0xa8) ocr4a[7:0] ocr4al read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 (0xaa) ocr4b[15:8] ocr4bh (0xab) ocr4b[7:0] ocr4bl read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 167 atmega640/1280/1281/2560/2561 2549k?avr?01/07 ocr4ch and ocr4cl ? output compare register 4 c ocr5ah and ocr5al ? output compare register 5 a ocr5bh and ocr5bl ? output compare register 5 b ocr5ch and ocr5cl ? output compare register 5 c the output compare registers contain a 16- bit value that is continuously compared with the counter value (tc n tn). a match can be used to generate an output compare interrupt, or to generate a waveform output on the ocnx pin. the output compare registers are 16-bit in size. to ensure that both the high and low bytes are written simultaneously when the cpu writes to these registers, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 139. bit 76543210 (0xad) ocr4c[15:8] ocr4ch (0xac) ocr4c[7:0] ocr4cl read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 (0x129) ocr5a[15:8] ocr5ah (0x128) ocr5a[7:0] ocr5al read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 (0x12b) ocr5b[15:8] ocr5bh (0x12a) ocr5b[7:0] ocr5bl read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 (0x12d) ocr5c[15:8] ocr5ch (0x12c) ocr5c[7:0] ocr5cl read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 168 atmega640/1280/1281/2560/2561 2549k?avr?01/07 icr1h and icr1l ? input capture register 1 icr3h and icr3l ? input capture register 3 ? icr4h and icr4l ? input capture register 4 icr5h and icr5l ? input capture register 5 the input capture is updated with the counter (tc n tn) value each time an event occurs on the icpn pin (or optionally on the analog comparator output for timer/counter1). the input capture can be used for defining the counter top value. the input capture register is 16-bit in size. to ensure that both the high and low bytes are read simultaneously when the cpu accesses these registers, the access is per- formed using an 8-bit temporary high byte re gister (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 139. bit 76543210 (0x87) icr1[15:8] icr1h (0x86) icr1[7:0] icr1l read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 (0x97) icr3[15:8] icr3h (0x96) icr3[7:0] icr3l read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 (0xa7) icr4[15:8] icr4h (0xa6) icr4[7:0] icr4l read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 (0x127) icr5[15:8] icr5h (0x126) icr5[7:0] icr5l read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 169 atmega640/1280/1281/2560/2561 2549k?avr?01/07 timsk1 ? timer/counter 1 interrupt mask register timsk3 ? timer/counter 3 interrupt mask register timsk4 ? timer/counter 4 interrupt mask register timsk5 ? timer/counter 5 interrupt mask register ? bit 5 ? icien: timer/countern, input capture interrupt enable w hen this bit is written to one, and the i-flag in the status register is set (interrupts glo- bally enabled), the timer/countern input capture interrupt is enabled. the corresponding interrupt vector (see ?interrupts? on page 69.) is executed when the icfn flag, located in tifrn, is set. ? bit 3 ? ocienc: timer/countern, output compare c match interrupt enable w hen this bit is written to one, and the i-flag in the status register is set (interrupts glo- bally enabled), the timer/countern output compare c match interrupt is enabled. the corresponding interrupt vector (see ?interrupts? on page 69.) is executed when the ocfnc flag, located in tifrn, is set. ? bit 2 ? ocienb: timer/countern, output compare b match interrupt enable w hen this bit is written to one, and the i-flag in the status register is set (interrupts glo- bally enabled), the timer/countern output compare b match interrupt is enabled. the corresponding interrupt vector (see ?interrupts? on page 69.) is executed when the ocfnb flag, located in tifrn, is set. ? bit 1 ? ociena: timer/countern, output compare a match interrupt enable w hen this bit is written to one, and the i-flag in the status register is set (interrupts glo- bally enabled), the timer/countern output compare a match interrupt is enabled. the corresponding interrupt vector (see ?interrupts? on page 69.) is executed when the ocfna flag, located in tifrn, is set. ? bit 0 ? toien: timer/countern, overflow interrupt enable w hen this bit is written to one, and the i-flag in the status register is set (interrupts glo- bally enabled), the timer/countern overflow interrupt is enabled. the corresponding interrupt vector (see ?interrupts? on page 69.) is executed when the tovn flag, located in tifrn, is set. bit 76543210 (0x6f) ? ?icie1 ? ocie1c ocie1b ocie1a toie1 timsk1 read/ w rite r r r/ w rr/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 (0x71) ? ?icie3 ? ocie3c ocie3b ocie3a toie3 timsk3 read/ w rite r r r/ w rr/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 (0x72) ? ?icie4 ? ocie4c ocie4b ocie4a toie4 timsk4 read/ w rite r r r/ w rr/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 (0x73) ? ?icie5 ? ocie5c ocie5b ocie5a toie5 timsk5 read/ w rite r r r/ w rr/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 170 atmega640/1280/1281/2560/2561 2549k?avr?01/07 tifr1 ? timer/counter1 interrupt flag register tifr3 ? timer/counter3 interrupt flag register tifr4 ? timer/counter4 interrupt flag register tifr5 ? timer/counter5 interrupt flag register ? bit 5 ? icfn: timer/count ern, input capture flag this flag is set when a capture event occurs on the icpn pin. w hen the input capture register (icrn) is set by the w gmn3:0 to be used as the top value, the icfn flag is set when the counter reaches the top value. icfn is automatically cleared when the input capture interrupt vector is executed. alter- natively, icfn can be cleared by writing a logic one to its bit location. ? bit 3? ocfnc: timer/countern, output compare c match flag this flag is set in the timer clock cycle after the counter (tc n tn) value matches the out- put compare register c (ocrnc). n ote that a forced output compare (foc nc) strobe will not set the ocfnc flag. ocfnc is automatically cleared when the output compare match c interrupt vector is executed. alternatively, ocfnc can be cleared by writing a logic one to its bit location. ? bit 2 ? ocfnb: timer/counter1, output compare b match flag this flag is set in the timer clock cycle after the counter (tc n tn) value matches the out- put compare register b (ocrnb). n ote that a forced output compare (foc nb) strobe will not set the ocfnb flag. ocfnb is automatically cleared when the output compare match b interrupt vector is executed. alternatively, ocfnb can be cleared by writing a logic one to its bit location. ? bit 1 ? ocf1a: timer/counter1, output compare a match flag this flag is set in the timer clock cycle after the counter (tc n tn value matches the out- put compare register a (ocrna). n ote that a forced output compare (foc na) strobe will not set the ocfna flag. bit 76543210 0x16 (0x36) ? ?icf1 ? ocf1c ocf1b ocf1a tov1 tifr1 read/ w rite r r r/ w rr/ w r/ w r/ w r/ w initial value00000000 bit 76543210 0x18 (0x38) ? ?icf3 ? ocf3c ocf3b ocf3a tov3 tifr3 read/ w rite r r r/ w rr/ w r/ w r/ w r/ w initial value00000000 bit 76543210 0x19 (0x39) ? ?icf4 ? ocf4c ocf4b ocf4a tov4 tifr4 read/ w rite r r r/ w rr/ w r/ w r/ w r/ w initial value00000000 bit 76543210 0x1a (0x3a) ? ?icf5 ? ocf5c ocf5b ocf5a tov5 tifr5 read/ w rite r r r/ w rr/ w r/ w r/ w r/ w initial value00000000 171 atmega640/1280/1281/2560/2561 2549k?avr?01/07 ocfna is automatically cleared when the output compare match a interrupt vector is executed. alternatively, ocfna can be cleared by writing a logic one to its bit location. ? bit 0 ? tovn: timer/countern, overflow flag the setting of this flag is dependent of the w gmn3:0 bits setting. in n ormal and ctc modes, the tovn flag is set when the timer overflows. refer to table 82 on page 149 for the tovn flag behavior when using another w gmn3:0 bit setting. tovn is automatically cleared when the time r/countern overflow interrupt vector is executed. alternatively, tovn can be cleared by writing a logic one to its bit location. 172 atmega640/1280/1281/2560/2561 2549k?avr?01/07 timer/counter 0, 1, 3, 4, and 5 prescaler timer/counter 0, 1, 3, 4, and 5 share the same prescaler module, but the timer/counters can have different prescaler settings. the description below applies to all timer/counters. tn is used as a general name, n = 0, 1, 3, 4, or 5. internal clock source the timer/counter can be clocked directly by the system clock (by setting the csn2:0 = 1). this provides the fastes t operation, with a maximum timer/counter clock frequency equal to system clock frequency (f clk_i/o ). alternatively, one of four taps from the pres- caler can be used as a clock source. the prescaled clock has a frequency of either f clk_i/o /8, f clk_i/o /64, f clk_i/o /256, or f clk_i/o /1024. prescaler reset the prescaler is free running, i.e., operates independently of the clock select logic of the timer/counter, and it is shared by the timer/counter tn. since the prescaler is not affected by the timer/co unter?s clock select, the state of the prescaler will have implica- tions for situations where a prescaled clock is used. one example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > csn2:0 > 1). the number of system clock cycles from when t he timer is enabled to the first count occurs can be from 1 to n +1 system clock cycles, where n equals the prescaler divisor (8, 64, 256, or 1024). it is possible to use the prescaler reset fo r synchronizing the timer/counter to program execution. however, care must be taken if the other timer/counter that shares the same prescaler also uses prescaling. a pr escaler reset will affect the prescaler period for all timer/counters it is connected to. external clock source an external clock source applied to the tn pin can be used as timer/counter clock (clk tn ). the tn pin is sampled once every system clock cycle by the pin synchronization logic. the synchronized (sampled) signal is then passed through the edge detector. fig- ure 61 shows a functional equivalent block diagram of the tn synchronization and edge detector logic. the registers are clocked at th e positive edge of the internal system clock ( clk i/o ). the latch is transparent in the high period of the internal system clock. the edge detector generates one clk tn pulse for each positive (csn2:0 = 7) or negative (csn2:0 = 6) edge it detects. figure 61. tn/t0 pin sampling the synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the tn pin to the counter is updated. enabling and disabling of the clock input must be done when tn has been stable for at least one system clock cycle, otherwise it is a risk that a false timer/counter clock pulse is generated. each half period of the exte rnal clock applied must be longer than one system clock cycle to ensure correct sampling. the external clock must be guaranteed to have less than half the system clock frequency (f extclk < f clk_i/o /2) given a 50/50% duty cycle. since tn_sync (to clock select logic) edge detector synchronization dq dq le dq tn clk i/o 173 atmega640/1280/1281/2560/2561 2549k?avr?01/07 the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency ( n yquist sampling theorem). however, due to vari- ation of the system clock freq uency and duty cycle caused by oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than f clk_i/o /2.5. an external clock source can not be prescaled. figure 62. prescaler for synchr onous timer/counters register description gtccr ? general timer/counter control register ? bit 7 ? tsm: timer/counter synchronization mode w riting the tsm bit to one activates the timer/counter synchronization mode. in this mode, the value that is written to the psrasy and psrsy n c bits is kept, hence keep- ing the corresponding prescaler reset signals asserted. this ensures that the corresponding timer/counters are halted and can be configured to the same value with- out the risk of one of them advancing during configuration. w hen the tsm bit is written to zero, the psrasy and psrsy n c bits are cleared by hardware, and the timer/counters start counting simultaneously. ? bit 0 ? psrsync: prescaler reset for synchronous timer/counters w hen this bit is one, timer/counter0, timer/counter1, timer/counter3, timer/counter4 and timer/counte r5 prescaler will be reset. this bit is normally clea red immediately by hardware, except if the tsm bit is set. n ote that timer/counter0, timer/counter1, timer/counter3, timer/counter4 and timer/counter5 share the same prescaler and a reset of this prescale r will affect all timers. psr10 clear tn tn clk i/o synchronization synchronization timer/countern clock source clk tn timer/countern clock source clk tn csn0 csn1 csn2 csn0 csn1 csn2 bit 7 6 5 4 3 2 1 0 0x23 (0x43) tsm ? ? ? ? ? psrasy psrsync gtccr read/ w rite r/ w rrrrrr/ w r/ w initial value 0 0 0 0 0 0 0 0 174 atmega640/1280/1281/2560/2561 2549k?avr?01/07 output compare modulator (ocm1c0a) overview the output compare modulator (ocm) allows generation of waveforms modulated with a carrier frequency. the modulator uses the outputs from the output compare unit c of the 16-bit timer/counter1 and the output compare unit of the 8-bit timer/counter0. for more details about these timer/counters see ?timer/counter 0, 1, 3, 4, and 5 prescaler? on page 172 and ?8-bit timer/counter2 with p w m and asynchronous operation? on page 176. figure 63. output compare modulator, block diagram w hen the modulator is enabled, the two output compare channels are modulated together as shown in the block diagram (figure 63). description the output compare unit 1c and output compare unit 2 shares the pb7 port pin for output. the outputs of the output compare units (oc1c and oc0a) overrides the nor- mal portb7 register when one of them is enabled (i.e., when comnx1:0 is not equal to zero). w hen both oc1c and oc0a are enabled at the same time, the modulator is automatically enabled. the functional equivalent schematic of the modulator is shown on figure 64. the sche- matic includes part of the timer/counter units and the port b pin 7 output driver circuit. figure 64. output compare modulator, schematic oc1c pin oc1c / oc0a / pb7 timer/counter 1 timer/counter 0 oc0a portb7 ddrb7 dq dq pin coma01 coma00 databus oc1c / oc0a/ pb7 com1c1 com1c0 modulator 1 0 oc1c dq oc0a dq ( from waveform generator ) ( from waveform generator ) 0 1 vcc 175 atmega640/1280/1281/2560/2561 2549k?avr?01/07 w hen the modulator is enabled the type of modulation (logical a n d or or) can be selected by the portb7 register. n ote that the ddrb7 controls the direction of the port independent of the comnx1:0 bit setting. timing example figure 65 illustrates th e modulator in action. in this ex ample the timer/counter1 is set to operate in fast p w m mode (non-inverted) and timer/counter0 uses ctc waveform mode with toggle compare output mode (comnx1:0 = 1). figure 65. output compare modulator, timing diagram in this example, timer/counter2 provides the carrier, while the modulating signal is gen- erated by the output compare unit c of the timer/counter1. the resolution of the p w m signal (oc1c) is reduced by the modulation. the reduction factor is equal to the number of system cloc k cycles of one period of the carrier (oc0a). in this example the resolution is reduced by a factor of two. the reason for the reduction is illustrated in figure 65 at the second and third period of the pb7 output when portb7 equals zero. the period 2 high time is one cycle longer than the period 3 high time, but the result on the pb7 output is equal in both periods. 1 2 oc0a (ctc mode) oc1c (fpwm mode) pb7 (portb7 = 0) pb7 (portb7 = 1) (period) 3 clk i/o 176 atmega640/1280/1281/2560/2561 2549k?avr?01/07 8-bit timer/counter2 with pw m and asynchronous operation timer/counter2 is a general purpose, single channel, 8-bit timer/counter module. the main features are: ? single channel counter ? clear timer on compar e match (auto reload) ? glitch-free, phase correct pu lse width modulator (pwm) ? frequency generator ? 10-bit clock prescaler ? overflow and compare match interr upt sources (tov2, ocf2a and ocf2b) ? allows clocking from external 32 khz wa tch crystal independent of the i/o clock overview a simplified block diagram of the 8-bit timer/counter is shown in figure 59.. for the actual placement of i/o pins, see ?pin c onfigurations? on page 2. cpu accessible i/o registers, including i/o bits and i/o pins, are shown in bold. the device-specific i/o register and bit locations are listed in the ?register description? on page 191. the power reduction timer/counter2 bit, prtim2, in ?prr0 ? power reduction regis- ter 0? on page 55 must be written to zero to enable timer/counter2 module. figure 66. 8-bit timer/counter block diagram timer/counter data bus ocrna ocrnb = = tcntn waveform generation waveform generation ocna ocnb = fixed top value control logic = 0 top bottom count clear direction tovn (int.req.) ocna (int.req.) ocnb (int.req.) tccrna tccrnb clk tn assrn synchronization unit prescaler t/c oscillator clk i/o clk asy asynchronous mode select (asn) synchronized status flags tosc1 tosc2 status flags clk i/o 177 atmega640/1280/1281/2560/2561 2549k?avr?01/07 registers the timer/counter (tc n t2) and output compare register (ocr2a and ocr2b) are 8-bit registers. interrupt request (abbreviated to int.req.) signals are all visible in the timer interrupt flag register (tifr2). all interrupts are individually masked with the timer interrupt mask register (timsk2). tifr2 and timsk2 are not shown in the figure. the timer/counter can be clocked internally, via the prescaler, or asynchronously clocked from the tosc1/2 pins, as detailed later in this section. the asynchronous operation is controlled by the asynchronous status register (assr). the clock select logic block controls which cl ock source the timer/counter uses to increment (or decre- ment) its value. the timer/counter is inactive when no clock source is selected. the output from the clock select logic is referred to as the timer clock (clk t2 ). the double buffered output compare register (ocr2a and ocr2b) are compared with the timer/counter value at all times. the result of the compare can be used by the w aveform generator to generate a p w m or variable frequency output on the output compare pins (oc2a and oc2b). see ?output compare unit? on page 184. for details. the compare match event will also set the co mpare flag (ocf2a or ocf2b) which can be used to generate an output compare interrupt request. definitions many register and bit references in this document are written in general form. a lower case ?n? replaces the timer/counter number, in this case 2. however, when using the register or bit defines in a program, the precise form must be used, i.e., tc n t2 for accessing timer/counter2 co unter value and so on. the definitions in table 87 are also used extensively throughout the section. timer/counter clock sources the timer/counter can be clocked by an internal synchronous or an external asynchro- nous clock source. t he clock source clk t2 is by default equal to the mcu clock, clk i/o . w hen the as2 bit in the assr regi ster is written to logic one , the clock source is taken from the timer/counter oscillator connec ted to tosc1 and tosc2. for details on asynchronous operation, see ?asynchronous operation of timer/counter2? on page 188. for details on clock sources and prescaler, see ?timer/counter prescaler? on page 190. counter unit the main part of the 8-bit timer/counter is the programmable bi-directional counter unit. figure 67 shows a block diagram of the counter and its surrounding environment. table 87. definitions bottom the counter reaches the bottom when it becomes zero (0x00). max the counter reaches its maximum when it becomes 0xff (decimal 255). top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be assigned to be the fixed value 0xff (max) or the value stored in the ocr2a register. the assignment is dependent on the mode of operation. 178 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 67. counter unit block diagram signal description (internal signals): count increment or decrement tc n t2 by 1. direction selects between increment and decrement. clear clear tc n t2 (set all bits to zero). clk tn timer/counter clock, referred to as clk t2 in the following. top signalizes that tc n t2 has reached maximum value. bottom signalizes that tc n t2 has reached minimum value (zero). depending on the mode of operation used, the counter is cleared, incremented, or dec- remented at each timer clock (clk t2 ). clk t2 can be generated from an external or internal clock source, selected by the clock select bits (cs22:0). w hen no clock source is selected (cs22:0 = 0) the timer is stopped. however, the tc n t2 value can be accessed by the cpu, regardless of whether clk t2 is present or not. a cpu write overrides (has priority over) all counter clear or count operations. the counting sequence is determined by the setting of the w gm21 and w gm20 bits located in the timer/ counter control register (tccr2a) and the w gm22 located in the timer/counter control register b (tcc r2b). there are close connections between how the counter behaves (counts) and how waveforms are generated on the output compare outputs oc2a and oc2b. for more details about advanced counting sequences and waveform generation, see ?modes of operation? on page 179. the timer/counter overflow flag (tov2) is set according to the mode of operation selected by the w gm22:0 bits. tov2 can be used for generating a cpu interrupt. data b u s tcntn control logic count tovn (int.req.) top bottom direction clear tosc1 t/c oscillator tosc2 prescaler clk i/o clk tn 179 atmega640/1280/1281/2560/2561 2549k?avr?01/07 modes of operation the mode of operation, i.e., the behavior of the timer/counter and the output compare pins, is defined by the combination of the w aveform generation mode ( w gm22:0) and compare output mode (com2x1:0) bits. the compare output mode bits do not affect the counting sequence, while the w aveform generation mode bits do. the com2x1:0 bits control whether the p w m output generated should be inverted or not (inverted or non-inverted p w m). for non-p w m modes the com2x1:0 bits control whether the out- put should be set, cleared, or toggled at a compare match (see ?compare match output unit? on page 185.). for detailed timing information refer to ?timer/counter timing diagrams? on page 186. normal mode the simplest mode of operation is the n ormal mode ( w gm22:0 = 0). in this mode the counting direction is always up (incrementing), and no counter clear is performed. the counter simply overruns when it passes its maximum 8-bit value (top = 0xff) and then restarts from the bottom (0x00). in normal operation the timer/counter overflow flag (tov2) will be set in the same timer clock cycle as the tc n t2 becomes zero. the tov2 flag in this case behaves like a ninth bit, except that it is only set, not cleared. however, combined with the timer overflow interrupt that automatically clears the tov2 flag, the timer resolution can be increased by software. there are no special cases to consider in the n ormal mode, a new counter value can be written anytime. the output compare unit can be used to generate interrupts at some given time. using the output compare to generate waveforms in n ormal mode is not recommended, since this will occupy too much of the cpu time. clear timer on compare match (ctc) mode in clear timer on compare or ctc mode ( w gm22:0 = 2), the ocr2a register is used to manipulate the counter resolution. in ctc mode the counter is cleared to zero when the counter value (tc n t2) matches the ocr2a. the ocr2a defines the top value for the counter, hence also its resolution. this mode allows greater control of the compare match output frequency. it also simplifies th e operation of counting external events. the timing diagram for the ctc mode is shown in table 68. the counter value (tc n t2) increases until a compare match occurs between tc n t2 and ocr2a, and then counter (tc n t2) is cleared. figure 68. ctc mode, timing diagram an interrupt can be generated each time the counter value reaches the top value by using the ocf2a flag. if the interrupt is enabled, the interrupt handler routine can be used for updating the top value. however, changing top to a value close to bottom when the counter is running with none or a low prescaler value must be done with care since the ctc mode does not have the double buffering feature. if the new value written to ocr2a is lower than the current value of tc n t2, the counter will miss the compare tcntn ocnx (toggle) ocnx interrupt flag set 1 4 period 2 3 (comnx1:0 = 1) 180 atmega640/1280/1281/2560/2561 2549k?avr?01/07 match. the counter will then have to count to its maxi mum value (0xff) and wrap around starting at 0x00 before the compare match can occur. for generating a waveform output in ctc mode, the oc2a output can be set to toggle its logical level on each compare match by setting the compare output mode bits to tog- gle mode (com2a1:0 = 1). the oc2a value w ill not be visible on the port pin unless the data direction for the pin is set to outp ut. the waveform gene rated will have a maximum frequency of f oc2a = f clk_i/o /2 when ocr2a is set to zero (0x00). the waveform fre- quency is defined by the following equation: the n variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). as for the n ormal mode of operation, the tov2 flag is set in the same timer clock cycle that the counter counts from max to 0x00. fast pwm mode the fast pulse w idth modulation or fast p w m mode ( w gm22:0 = 3 or 7) provides a high frequency p w m waveform generation option. the fast p w m differs from the other p w m option by its single-slope operation. the counter counts from bottom to top then restarts from bottom. top is defined as 0xff when w gm22:0 = 3, and ocr2a when mgm22:0 = 7. in non-inverting compare output mode, the output compare (oc2x) is cleared on the compare match between tc n t2 and ocr2x, and set at bottom. in inverting compare output mode, the output is set on compare match and cleared at bottom. due to the single-slope operation, the operating frequency of the fast p w m mode can be twice as high as the phase correct p w m mode that uses dual-slope oper- ation. this high frequency makes the fast p w m mode well suited for power regulation, rectification, and dac applications. high fr equency allows physicall y small sized exter- nal components (coils, capacitors), and therefore reduces total system cost. in fast p w m mode, the counter is incremented until the counter value matches the top value. the counter is then cleared at the following timer clock cycle. the timing diagram for the fast p w m mode is shown in figure 60. the tc n t2 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. the diagram includes non-inverted and inverted p w m outputs. the small horizontal line marks on the tc n t2 slopes represent compare matches between ocr2x and tc n t2. figure 69. fast p w m mode, timing diagram f ocnx f clk_i/o 2 n 1 ocrnx + () ?? ------------------------------------------------- - = tcntn ocrnx update and tovn interrupt flag set 1 period 2 3 ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) ocrnx interrupt flag set 4 5 6 7 181 atmega640/1280/1281/2560/2561 2549k?avr?01/07 the timer/counter overflow flag (tov2) is set each time the counter reaches top. if the interrupt is enabled, the interrupt handler routine can be used for updating the com- pare value. in fast p w m mode, the compare unit allows generation of p w m waveforms on the oc2x pin. setting the com2x1:0 bits to two will produce a non-inverted p w m and an inverted p w m output can be generated by setting the com2x1:0 to three. top is defined as 0xff when w gm2:0 = 3, and ocr2a when w gm2:0 = 7 (see table 89 on page 191). the actual oc2x value will only be vi sible on the port pin if the data direction for the port pin is set as output. the p w m waveform is generated by setting (or clearing) the oc2x register at the compare match between ocr2x and tc n t2, and clearing (or setting) the oc2x register at the timer clo ck cycle the counter is cleared (changes from top to bottom). the p w m frequency for the output can be calculated by the following equation: the n variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). the extreme values for the ocr2a register represent special cases when generating a p w m waveform output in the fast p w m mode. if the ocr2a is set equal to bottom, the output will be a narro w spike for each max+1 timer cl ock cycle. setting the ocr2a equal to max will result in a constantly high or low output (depending on t he polarity of the output set by the com2a1:0 bits.) a frequency (with 50% duty cycle) waveform output in fast p w m mode can be achieved by setting oc2x to toggle its logical level on each compare match (com2x1:0 = 1). the waveform generated will have a maximum frequency of f oc2 = f clk_i/o /2 when ocr2a is set to zero. this feature is similar to t he oc2a toggle in ctc mode, except the double buffer feature of the output compare unit is enabled in the fast p w m mode. f ocnxpwm f clk_i/o n 256 ? ------------------ = 182 atmega640/1280/1281/2560/2561 2549k?avr?01/07 phase correct pwm mode the phase correct p w m mode ( w gm22:0 = 1 or 5) provides a high resolution phase correct p w m waveform generation option. the phase correct p w m mode is based on a dual-slope operation. the counter counts repeatedly from bottom to top and then from top to bottom. top is defined as 0xff when w gm22:0 = 1, and ocr2a when mgm22:0 = 5. in non-inverting compare output mode, the output compare (oc2x) is cleared on the compare match between tc n t2 and ocr2x while upcounting, and set on the compare match while downcounting. in inverting output compare mode, the operation is inverted. the dual-slope operation has lower maximum operation frequency than single slope operation. however, due to the symmetric feature of the dual-slope p w m modes, these modes are preferred for motor control applications. in phase correct p w m mode the counter is incremented until the counter value matches top. w hen the counter reaches top, it changes the count direction. the tc n t2 value will be equal to top for one timer clock cycle. the timing diagram for the phase correct p w m mode is shown on figure 70. the tc n t2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. the diagra m includes non-inverted and inverted p w m outputs. the small horizontal line marks on the tc n t2 slopes repre- sent compare matches between ocr2x and tc n t2. figure 70. phase correct p w m mode, timing diagram the timer/counter overflow flag (tov2) is set each time the counter reaches bot- tom. the interrupt flag can be used to generate an interrupt each time the counter reaches the bottom value. in phase correct p w m mode, the compare unit allows generation of p w m waveforms on the oc2x pin. setting the com2x1:0 bi ts to two will produce a non-inverted p w m. an inverted p w m output can be generated by setting the com2x1:0 to three. top is defined as 0xff when w gm2:0 = 3, and ocr2a when mgm2:0 = 7 (see table 90 on page 192). the actual oc2x value will only be vi sible on the port pin if the data direction for the port pin is set as output. the p w m waveform is generated by clearing (or setting) the oc2x register at the compare match between ocr2x and tc n t2 when the counter increments, and setting (or clearing) the oc2x register at compare match tovn interrupt flag set ocnx interrupt flag set 1 2 3 tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) ocrnx update 183 atmega640/1280/1281/2560/2561 2549k?avr?01/07 between ocr2x and tc n t2 when the counter decrements. the p w m frequency for the output when using phase correct p w m can be calculated by the following equation: the n variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). the extreme values for the ocr2a register represent special cases when generating a p w m waveform output in the phase correct p w m mode. if the ocr2a is set equal to bottom, the output will be cont inuously low and if set e qual to max the output will be continuously high for non-inverted p w m mode. for inverted p w m the output will have the opposite logic values. at the very start of period 2 in figure 70 ocnx has a transition from high to low even though there is no compare match. the point of this transition is to guarantee symmetry around bottom. there are two cases that give a transition without compare match. ? ocr2a changes its value from max, like in figure 70. w hen the ocr2a value is max the ocn pin value is the same as the result of a down-counting compare match. to ensure symmetry around bottom the ocn value at max must correspond to the result of an up-counting compare match. ? the timer starts counting from a value higher than the one in ocr2a, and for that reason misses the compare match and hence the ocn change that would have happened on the way up. f ocnxpcpwm f clk_i/o n 510 ? ------------------ = 184 atmega640/1280/1281/2560/2561 2549k?avr?01/07 output compare unit the 8-bit comparator continuously compares tc n t2 with the output compare register (ocr2a and ocr2b). w henever tc n t2 equals ocr2a or ocr2b, the comparator signals a match. a match will set the output compare flag (ocf2a or ocf2b) at the next timer clock cycle. if the correspondi ng interrupt is enabled, the output compare flag generates an output compare interrupt. the output compare flag is automatically cleared when the interrupt is executed. alternatively, the output compare flag can be cleared by software by writing a logical one to its i/o bit location. the w aveform gener- ator uses the match signal to generate an output according to operating mode set by the w gm22:0 bits and compare output mode (com2x1:0) bits. the max and bottom sig- nals are used by the w aveform generator for handling the special cases of the extreme values in some modes of operation (?modes of operation? on page 179). figure 57 on page 157 shows a block diagram of the output compare unit. figure 71. output compare unit, block diagram the ocr2x register is double buffered when using any of the pulse w idth modulation (p w m) modes. for the n ormal and clear timer on compare (ctc) modes of operation, the double buffering is disabled. the double buffering synchronizes the update of the ocr2x compare register to either top or bottom of the counting sequence. the syn- chronization prevents the occurrence of odd-length, non-symmetrical p w m pulses, thereby making the output glitch-free. the ocr2x register access may seem complex, but this is not case. w hen the double buffering is enabled, the cpu has access to the ocr2x buffer register, and if double buffering is disabled the cp u will access the ocr2x directly. force output compare in non-p w m waveform generation modes, the match output of the comparator can be forced by writing a one to the force output compare (foc2x) bit. forcing compare match will not set the ocf2x flag or reload /clear the timer, but the oc2x pin will be updated as if a real compare match had occurred (the com2x1:0 bits settings define whether the oc2x pin is set, cleared or toggled). compare match blocking by tcnt2 write all cpu write operations to the tc n t2 register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. this feature allows ocfn x (int.req.) = (8-bit comparator ) ocrnx ocnx data b u s tcntn wgmn1:0 waveform generator top focn comnx1:0 bottom 185 atmega640/1280/1281/2560/2561 2549k?avr?01/07 ocr2x to be initialized to the same value as tc n t2 without triggering an interrupt when the timer/counter clock is enabled. using the output compare unit since writing tc n t2 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing tc n t2 when using the output compare channel, independently of whether the timer/counter is running or not. if the value written to tc n t2 equals the ocr2x value, the compare match will be missed, resulting in incorrect waveform generation. similarly, do not write the tc n t2 value equal to bottom when the counter is downcounting. the setup of the oc2x should be performed before setting the data direction register for the port pin to output. the easiest way of setting the oc2x value is to use the force output compare (foc2x) strobe bit in n ormal mode. the oc2x register keeps its value even when changing between w aveform generation modes. be aware that the com2x1:0 bits are not double buffered together with the compare value. changing the com2x1:0 bi ts will take effect immediately. compare match output unit the compare output mode (com2x1:0) bits have two functions. the w aveform gener- ator uses the com2x1:0 bits for defining the output compare (oc2x) state at the next compare match. also, the com2x1:0 bits control the oc2x pin output source. figure 72 shows a simplified schematic of the logic affected by the com2x1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the figur e are shown in bold. only the parts of the general i/o port cont rol registers (ddr and port) that are affected by the com2x1:0 bits are shown. w hen referring to the oc2x state, the reference is for the internal oc2x register, not the oc2x pin. figure 72. compare match output unit, schematic the general i/o port function is overridden by the output compare (oc2x) from the w aveform generator if either of the com2x1:0 bits are set. however, the oc2x pin direction (input or output) is still controlled by the data dir ection register (ddr) for the port ddr dq dq ocnx pin ocnx dq waveform generator comnx1 comnx0 0 1 data b u s focnx clk i/o 186 atmega640/1280/1281/2560/2561 2549k?avr?01/07 port pin. the data direction register bit for the oc2x pin (ddr_oc2x) must be set as output before the oc2x value is visible on the pin. the port override function is indepen- dent of the w aveform generation mode. the design of the output compare pin logic allows initialization of the oc2x state before the output is enabled. n ote that some com2x1:0 bit settings are reserved for certain modes of operation. see ?register description? on page 191. compare output mode and waveform generation the w aveform generator uses the com2x1:0 bits differently in normal, ctc, and p w m modes. for all modes, setting the com2x1:0 = 0 tells the w aveform generator that no action on the oc2x register is to be performed on the next compare match. for com- pare output actions in the non-p w m modes refer to table 91 on page 192. for fast p w m mode, refer to table 92 on page 192, and for phase correct p w m refer to table 93 on page 193. a change of the com2x1:0 bits state will have effect at the first co mpare match after the bits are written. for non-p w m modes, the action can be forced to have immediate effect by using the foc2x strobe bits. timer/counter timing diagrams the following figures show the timer/counter in synchronous mode, and the timer clock (clk t2 ) is therefore shown as a clock enable signal. in asynchronous mode, clk i/o should be replaced by the timer/counter oscillato r clock. the figures include information on when interrupt flags are set. figure 73 c ontains timing data for basic timer/counter operation. the figure shows the count sequence close to the max value in all modes other than phase correct p w m mode. figure 73. timer/counter timing diagram, no prescaling figure 74 shows the same timing data, but with the prescaler enabled. clk tn (clk i/o /1) tovn clk i/o tcntn max - 1 max bottom bottom + 1 187 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 74. timer/counter timing diagram, with prescaler (f clk_i/o /8) figure 75 shows the setting of ocf2a in all modes except ctc mode. figure 75. timer/counter timing diagram, setting of ocf2a, with prescaler (f clk_i/o /8) figure 76 shows the setting of ocf2a and the clearing of tc n t2 in ctc mode. figure 76. timer/counter timing diagram, clear timer on compare match mode, with prescaler (f clk_i/o /8) tovn tcntn max - 1 max bottom bottom + 1 clk i/o clk tn (clk i/o /8) ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) ocfnx ocrnx tcntn (ctc) top top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o /8) 188 atmega640/1280/1281/2560/2561 2549k?avr?01/07 asynchronous operation of timer/counter2 w hen timer/counter2 operates asynchronously, some considerations must be taken. ? w arning: w hen switching between asynchronous and synchronous clocking of timer/counter2, the timer registers tc n t2, ocr2x, and tccr2x might be corrupted. a safe procedure for switching clock source is: 1. disable the timer/counter2 interrupts by clearing ocie2x and toie2. 2. select clock source by setting as2 as appropriate. 3. w rite new values to tc n t2, ocr2x, and tccr2x. 4. to switch to asynchronous operation: w ait for tc n 2ub, ocr2xub, and tcr2xub. 5. clear the timer/counter2 interrupt flags. 6. enable interrupts, if needed. ? the cpu main clock frequency must be more than four times the oscillator frequency. ? w hen writing to one of the registers tc n t2, ocr2x, or tccr2x, the value is transferred to a temporary register, and latched after two positive edges on tosc1. the user should not write a new value before the contents of the temporary register have been transferred to its destination. each of the five mentioned registers have their individual temporary register, which means that e.g. writing to tc n t2 does not disturb an ocr2x write in progress. to detect that a transfer to the destination register has taken place, the asynchronous status register ? assr has been implemented. ? w hen entering power-save or adc n oise reduction mode after having written to tc n t2, ocr2x, or tccr2x, the user must wait until the written register has been updated if timer/ counter2 is used to wake up th e device. otherwise, the mcu will enter sleep mode before the changes are effective. this is particularly important if any of the output compare2 interrupt is used to wake up the device, since the output compare function is disabled during writing to ocr2x or tc n t2. if the write cycle is not finished, and the mcu enters sleep mode before the corresponding ocr2xub bit returns to zero, the devi ce will never receive a compare match interrupt, and the mcu will not wake up. ? if timer/counter2 is used to wake the device up from power-save or adc n oise reduction mode, precautions must be taken if the user wants to re-enter one of these modes: the interrupt logic needs one tosc1 cycle to be reset. if the time between wake-up and re-entering sleep mode is less than one tosc1 cycle, the interrupt will not occur, and the device will fa il to wake up. if the user is in doubt whether the time before re-entering power-save or adc n oise reduction mode is sufficient, the following algorithm can be used to ensure that one tosc1 cycle has elapsed: 1. w rite a value to tccr2x, tc n t2, or ocr2x. 2. w ait until the corresponding update busy flag in assr returns to zero. 3. enter power-save or adc n oise reduction mode. ? w hen the asynchronous operation is se lected, the 32.768 khz oscillator for timer/counter2 is always running, except in power-down and standby modes. after a power-up reset or wake-up from power-down or standby mode, the user should be aware of the fact that this oscillator mi ght take as long as one second to stabilize. the user is advised to wait for at least one second before using timer/counter2 after power-up or wake-up from power-down or standby mode. the contents of all timer/counter2 registers must be considered lost after a wake-up from power- 189 atmega640/1280/1281/2560/2561 2549k?avr?01/07 down or standby mode due to unstable clock signal upon start-up, no matter whether the oscillator is in use or a cl ock signal is applied to the tosc1 pin. ? description of wake up from power-save or adc n oise reduction mode when the timer is clocked asynchronously: w hen the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. after wake-up, the mcu is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following sleep. ? reading of the tc n t2 register shortly after wake-u p from power-save may give an incorrect result. since tc n t2 is clocked on the asynchronous tosc clock, reading tc n t2 must be done through a register synchronized to the internal i/o clock domain. synchronization takes place for every rising tosc1 edge. w hen waking up from power-save mode, and the i/o clock (clk i/o ) again becomes active, tc n t2 will read as the previous value (before entering sleep) until the next rising tosc1 edge. the phase of the tosc clock after waking up from power-save mode is essentially unpredictable, as it depends on the wake-up time. the recommended procedure for reading tc n t2 is thus as follows: 1. w rite any value to either of the registers ocr2x or tccr2x. 2. w ait for the corresponding update busy flag to be cleared. 3. read tc n t2. ? during asynchronous operation, the synchronization of the interrupt flags for the asynchronous timer takes 3 processor cycles plus one timer cycle. the timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the interrupt flag. the output compare pin is changed on the timer clock and is not synchronized to the processor clock. 190 atmega640/1280/1281/2560/2561 2549k?avr?01/07 timer/counter prescaler figure 77. prescaler for timer/counter2 the clock source for timer/counter2 is named clk t2s . clk t2s is by default connected to the main system i/o clock clk i o . by setting the as2 bit in assr , timer/counter2 is asyn- chronously clocked from the tosc1 pin. th is enables use of timer/counter2 as a real time counter (rtc). w hen as2 is set, pins tosc1 and tosc2 are disconnected from port c. a crystal can then be connected between the tosc1 and tosc2 pins to serve as an independent clock source for timer/counter2. the oscillator is optimized for use with a 32.768 khz crystal. by setting the exclk bit in the assr, a 32 khz external clock can be applied. see ?assr ? asynchro nous status regist er? on page 196 for details. for timer/counter2, the possible prescaled selections are: clk t2s /8, clk t2s /32, clk t2s /64, clk t2s /128, clk t2s /256, and clk t2s /1024. additionally, clk t2s as well as 0 (stop) may be selected. setting the psrasy bit in gtccr resets the prescaler. this allows the user to operate with a predictable prescaler. 10-bit t/c prescaler timer/counter2 clock source clk i/o clk t2s tosc1 as2 cs20 cs21 cs22 clk t2s /8 clk t2s /64 clk t2s /128 clk t2s /1024 clk t2s /256 clk t2s /32 0 psrasy clear clk t2 191 atmega640/1280/1281/2560/2561 2549k?avr?01/07 register description tccr2a ?timer/counter control register a ? bits 7:6 ? com2a1:0: compare match output a mode these bits control the output compare pi n (oc2a) behavior. if one or both of the com2a1:0 bits are set, the oc2a output overrides the normal port functionality of the i/o pin it is connected to. ho wever, note that t he data direction register (ddr) bit cor- responding to the oc2a pin must be set in order to enable the output driver. w hen oc2a is connected to the pin, the func tion of the com2a1:0 bits depends on the w gm22:0 bit setting. table 88 shows the com2a1:0 bit functionality when the w gm22:0 bits are set to a normal or ctc mode (non-p w m). table 89 shows the com2a1:0 bit functionality when the w gm21:0 bits are set to fast p w m mode. n ote: 1. a special case occurs when ocr2a equals top and com2a1 is set. in this case, the compare match is ignored, but the set or clear is done at bottom. see ?fast p w m mode? on page 180 for more details. table 90 shows the com2a1:0 bit functionality when the w gm22:0 bits are set to phase correct p w m mode. bit 7 6 5 4 3 2 1 0 (0xb0) com2a1 com2a0 com2b1 com2b0 ? ? wgm21 wgm20 tccr2a read/ w rite r/ w r/ w r/ w r/ w rrr/ w r/ w initial value 0 0 0 0 0 0 0 0 table 88. compare output mode, non-p w m mode com2a1 com2a0 description 00 n ormal port operation, oc2a disconnected. 0 1 toggle oc2a on compare match 1 0 clear oc2a on compare match 1 1 set oc2a on compare match table 89. compare output mode, fast p w m mode (1) com2a1 com2a0 description 00 n ormal port operation, oc2a disconnected. 01 w gm22 = 0: n ormal port operation, oc2a disconnected. w gm22 = 1: toggle oc2a on compare match. 1 0 clear oc2a on compare match, set oc2a at bottom, (non-inverting mode). 1 1 set oc2a on compare match, clear oc2a at bottom, (inverting mode). 192 atmega640/1280/1281/2560/2561 2549k?avr?01/07 n ote: 1. a special case occurs when ocr2a equals top and com2a1 is set. in this case, the compare match is ignored, but the set or clear is done at top. see ?phase cor- rect p w m mode? on page 182 for more details. ? bits 5:4 ? com2b1:0: compare match output b mode these bits control the output compare pi n (oc2b) behavior. if one or both of the com2b1:0 bits are set, the oc2b output overrides the normal port functionality of the i/o pin it is connected to. ho wever, note that t he data direction register (ddr) bit cor- responding to the oc2b pin must be set in order to enable the output driver. w hen oc2b is connected to the pin, the func tion of the com2b1:0 bits depends on the w gm22:0 bit setting. table 91 shows the com2b1:0 bit functionality when the w gm22:0 bits are set to a normal or ctc mode (non-p w m). table 92 shows the com2b1:0 bit functionality when the w gm22:0 bits are set to fast p w m mode. n ote: 1. a special case occurs when ocr2b equals top and com2b1 is set. in this case, the compare match is ignored, but the set or clear is done at bottom. see ?fast p w m mode? on page 180 for more details. table 90. compare output mode, phase correct p w m mode (1) com2a1 com2a0 description 00 n ormal port operation, oc2a disconnected. 01 w gm22 = 0: n ormal port operation, oc2a disconnected. w gm22 = 1: toggle oc2a on compare match. 1 0 clear oc2a on compare match when up-counting. set oc2a on compare match when down-counting. 1 1 set oc2a on compare match when up-counting. clear oc2a on compare match when down-counting. table 91. compare output mode, non-p w m mode com2b1 com2b0 description 00 n ormal port operation, oc2b disconnected. 0 1 toggle oc2b on compare match 1 0 clear oc2b on compare match 1 1 set oc2b on compare match table 92. compare output mode, fast p w m mode (1) com2b1 com2b0 description 00 n ormal port operation, oc2b disconnected. 01reserved 1 0 clear oc2b on compare match, set oc2b at bottom, (non-inverting mode). 1 1 set oc2b on compare match, clear oc2b at bottom, (inverting mode). 193 atmega640/1280/1281/2560/2561 2549k?avr?01/07 table 93 shows the com2b1:0 bit functionality when the w gm22:0 bits are set to phase correct p w m mode. n ote: 1. a special case occurs when ocr2b equals top and com2b1 is set. in this case, the compare match is ignored, but the set or clear is done at top. see ?phase cor- rect p w m mode? on page 182 for more details. ? bits 3, 2 ? res: reserved bits these bits are reserved bits and will always read as zero. ? bits 1:0 ? wgm21:0: waveform generation mode combined with the w gm22 bit found in the tccr2b register, these bits control the counting sequence of the counter, the source for maximum (top) counter value, and what type of waveform generation to be used, see table 94. modes of operation sup- ported by the timer/counter unit are: n ormal mode (counter), clear timer on compare match (ctc) mode, and two types of pulse w idth modulation (p w m) modes (see ?modes of operation? on page 179). n otes: 1. max= 0xff 2. bottom= 0x00 table 93. compare output mode, phase correct p w m mode (1) com2b1 com2b0 description 00 n ormal port operation, oc2b disconnected. 01reserved 1 0 clear oc2b on compare match when up-counting. set oc2b on compare match when down-counting. 1 1 set oc2b on compare match when up-counting. clear oc2b on compare match when down-counting. table 94. w aveform generation mode bit description mode wgm2 wgm1 wgm0 timer/counter mode of operation top update of ocrx at tov flag set on (1)(2) 00 0 0 n ormal 0xff immediate max 10 0 1p w m, phase correct 0xff top bottom 2 0 1 0 ctc ocra immediate max 3 0 1 1 fast p w m0xffbottommax 41 0 0reserved ? ? ? 51 0 1p w m, phase correct ocra top bottom 61 1 0reserved ? ? ? 7 1 1 1 fast p w m ocra bottom top 194 atmega640/1280/1281/2560/2561 2549k?avr?01/07 tccr2b ? timer/counter control register b ? bit 7 ? foc2a: force output compare a the foc2a bit is only active when the w gm bits specify a non-p w m mode. however, for ensuring compatib ility with future devices, this bit must be set to zero when tccr2b is written when operating in p w m mode. w hen writing a logical one to the foc2a bit, an immediate compare match is forced on the w aveform generation unit. the oc2a output is changed according to its com2a1:0 bits setting. n ote that the foc2a bit is implemented as a strobe. therefore it is the value present in the com2a1:0 bits that determines the effect of the forced compare. a foc2a strobe will not generate any interrup t, nor will it clear the timer in ctc mode using ocr2a as top. the foc2a bit is always read as zero. ? bit 6 ? foc2b: force output compare b the foc2b bit is only active when the w gm bits specify a non-p w m mode. however, for ensuring compatib ility with future devices, this bit must be set to zero when tccr2b is written when operating in p w m mode. w hen writing a logical one to the foc2b bit, an immediate compare match is forced on the w aveform generation unit. the oc2b output is changed according to its com2b1:0 bits setting. n ote that the foc2b bit is implemented as a strobe. therefore it is the value present in the com2b1:0 bits that determines the effect of the forced compare. a foc2b strobe will not generate any interrup t, nor will it clear the timer in ctc mode using ocr2b as top. the foc2b bit is always read as zero. ? bits 5:4 ? res: reserved bits these bits are reserved bits and will always read as zero. ? bit 3 ? wgm22: waveform generation mode see the description in the ?tccr2a ?timer/counter control register a? on page 191. ? bit 2:0 ? cs22:0: clock select the three clock select bits select the clock source to be used by the timer/counter, see table 95. bit 7 6 5 4 3 2 1 0 (0xb1) foc2a foc2b ? ? wgm22 cs22 cs21 cs20 tccr2b read/ w rite ww rrr/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 195 atmega640/1280/1281/2560/2561 2549k?avr?01/07 if external pin modes are used for the timer/counter0, transitions on the t0 pin will clock the counter even if the pin is configured as an output. this feature allows software control of the counting. tcnt2 ? timer/counter register the timer/counter register gives direct access, both for read and write operations, to the timer/counter unit 8-bit counter. w riting to the tc n t2 register blocks (removes) the compare match on the following timer clock. modifying the counter (tc n t2) while the counter is running, introduces a risk of missing a compare match between tc n t2 and the ocr2x registers. ocr2a ? output compare register a the output compare register a contains an 8-bit value that is continuously compared with the counter value (tc n t2). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc2a pin. ocr2b ? output compare register b the output compare register b contains an 8-bit value that is continuously compared with the counter value (tc n t2). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc2b pin. table 95. clock select bit description cs22 cs21 cs20 description 000 n o clock source (timer/counter stopped). 001clk t2s /( n o prescaling) 010clk t2s /8 (from prescaler) 011clk t2s /32 (from prescaler) 100clk t2s /64 (from prescaler) 101clk t2s /128 (from prescaler) 110clk t 2 s /256 (from prescaler) 111clk t 2 s /1024 (from prescaler) bit 76543210 (0xb2) tcnt2[7:0] tcnt2 read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 (0xb3) ocr2a[7:0] ocr2a read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 (0xb4) ocr2b[7:0] ocr2b read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 196 atmega640/1280/1281/2560/2561 2549k?avr?01/07 assr ? asynchronous status register ? bit 6 ? exclk: enable external clock input w hen exclk is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on timer oscillator 1 (tosc1) pin instead of a 32 khz crystal. w riting to exclk should be done before asynchronous operation is selected. n ote that the crystal o scillator will only run when this bit is zero. ? bit 5 ? as2: asynchronous timer/counter2 w hen as2 is written to zero, timer/counter2 is clocked from the i/o clock, clk i/o . w hen as2 is written to one, timer/counter2 is cl ocked from a crystal oscillator connected to the timer oscillator 1 (tosc1) pin. w hen the value of as2 is changed, the contents of tc n t2, ocr2a, ocr2b, tccr2a and tccr2b might be corrupted. ? bit 4 ? tcn2ub: timer/counter2 update busy w hen timer/counter2 operates asynchronously and tc n t2 is written, this bit becomes set. w hen tc n t2 has been updated from the temporary storage register, this bit is cleared by hardware. a logical zero in this bit indicates that tc n t2 is ready to be updated with a new value. ? bit 3 ? ocr2aub: output co mpare register2 update busy w hen timer/counter2 operates asynchronously and ocr2a is written, this bit becomes set. w hen ocr2a has been updated from the temporary storage register, this bit is cleared by hardware. a logical zero in this bit indicates that ocr2a is ready to be updated with a new value. ? bit 2 ? ocr2bub: output compare register2 update busy w hen timer/counter2 operates asynchronously and ocr2b is written, this bit becomes set. w hen ocr2b has been updated from the temporary storage register, this bit is cleared by hardware. a logical zero in this bit indicates that ocr2b is ready to be updated with a new value. ? bit 1 ? tcr2aub: timer/counter control register2 update busy w hen timer/counter2 operates asynchronously and tccr2a is written, this bit becomes set. w hen tccr2a has been updated from the temporary storage register, this bit is cleared by hardware. a logical zero in this bit indicate s that tccr2a is ready to be updated with a new value. ? bit 0 ? tcr2bub: timer/counter control register2 update busy w hen timer/counter2 operates asynchronously and tccr2b is written, this bit becomes set. w hen tccr2b has been updated from the temporary storage register, this bit is cleared by hardware. a logical zero in this bit indicate s that tccr2b is ready to be updated with a new value. if a write is performed to any of the five timer/counter2 registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur. bit 7 6 5 4 3 2 1 0 (0xb6) ? exclk as2 tcn2ub ocr2aub ocr2bub tcr2aub tcr2bub assr read/ w rite r r/ w r/ w rr r r r initial value 0 0 0 0 0 0 0 0 197 atmega640/1280/1281/2560/2561 2549k?avr?01/07 the mechanisms for reading tc n t2, ocr2a, ocr2b, tccr2a and tccr2b are dif- ferent. w hen reading tc n t2, the actual timer value is read. w hen reading ocr2a, ocr2b, tccr2a and tccr2b the value in the temporary storage register is read. timsk2 ? timer/counter2 interrupt mask register ? bit 2 ? ocie2b: timer/counter2 output compare match b interrupt enable w hen the ocie2b bit is written to one and the i-bit in the status register is set (one), the timer/counter2 compare match b interrupt is enabled. the corresponding interrupt is executed if a compare match in timer/counter2 occurs, i.e., when the ocf2b bit is set in the timer/counter 2 interrupt flag register ? tifr2. ? bit 1 ? ocie2a: timer/counter2 output compare match a interrupt enable w hen the ocie2a bit is written to one and the i-bit in the status register is set (one), the timer/counter2 compare match a interrupt is enabled. the corresponding interrupt is executed if a compare match in timer/counter2 occurs, i.e., when the ocf2a bit is set in the timer/counter 2 interrupt flag register ? tifr2. ? bit 0 ? toie2: timer/counter2 overflow interrupt enable w hen the toie2 bit is written to one and the i-bi t in the status register is set (one), the timer/counter2 overflow interrupt is enable d. the corresponding interrupt is executed if an overflow in timer/counter2 occurs, i.e., when the tov2 bit is set in the timer/counter2 interrupt flag register ? tifr2. tifr2 ? timer/counter2 interrupt flag register ? bit 2 ? ocf2b: output compare flag 2 b the ocf2b bit is set (one) when a compare match occurs between the timer/counter2 and the data in ocr2b ? output compare register2. ocf2b is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, ocf2b is cleared by writing a logic one to the flag. w hen the i-bit in sreg, ocie2b (timer/counter2 compare match interrupt enable), and ocf2b are set (one), the timer/counter2 compare match interrupt is executed. ? bit 1 ? ocf2a: output compare flag 2 a the ocf2a bit is set (one) when a compare match occurs between the timer/counter2 and the data in ocr2a ? output compare register2. ocf2a is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, ocf2a is cleared by writing a logic one to the flag. w hen the i-bit in sreg, ocie2a (timer/counter2 compare match interrupt enable), and ocf2a are set (one), the timer/counter2 compare match interrupt is executed. bit 76543 2 1 0 (0x70) ? ? ? ? ? ocie2b ocie2a toie2 timsk2 read/ w rite r r r r r r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x17 (0x37) ?????ocf2bocf2atov2tifr2 read/ w riterrrrrr/ w r/ w r/ w initial value00000000 198 atmega640/1280/1281/2560/2561 2549k?avr?01/07 ? bit 0 ? tov2: timer/counter2 overflow flag the tov2 bit is set (one) when an overflow occurs in timer/counter2. tov2 is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, tov2 is cleared by writing a logic one to the flag. w hen the sreg i-bit, toie2a (timer/counter2 overflow interrupt enable), and tov2 are set (one), the timer/counter2 overflow interrupt is executed. in p w m mode, this bit is set when timer/counter2 changes counting direction at 0x00. gtccr ? general timer/counter control register ? bit 1 ? psrasy: prescaler reset timer/counter2 w hen this bit is one, the ti mer/counter2 prescaler will be reset. this bit is normally cleared immediately by hardware. if the bit is written when timer/counter2 is operating in asynchronous mode, the bit will remain one until the pr escaler has been reset. the bit will not be cleared by hardware if the tsm bit is set. refer to the description of the ?bit 7 ? tsm: timer/counter synchronization mo de? on page 173 for a description of the timer/counter synchronization mode. bit 7 6 5 4 3 2 1 0 0x23 (0x43) tsm ? ? ? ? ?psrasy psrsync gtccr read/ w rite r/ w rrrrrr/ w r/ w initial value 0 0 0 0 0 0 0 0 199 atmega640/1280/1281/2560/2561 2549k?avr?01/07 spi ? serial peripheral interface the serial peripheral interface (spi) allows high-speed synchronous data transfer between the atmega640/1280/1281/2560/2561 and peripheral devices or between sev- eral avr devices. the atmega640/1280/1281/2560/2561 spi includes the following features: ? full-duplex, three-wire synchronous data transfer ? master or slave operation ? lsb first or msb first data transfer ? seven programmable bit rates ? end of transmission interrupt flag ? write collision flag protection ? wake-up from idle mode ? double speed (ck/2) master spi mode usart can also be used in master spi mode, see ?usart in spi mode? on page 236. the power reduction spi bit, prspi, in ?prr0 ? power reduction register 0? on page 55 on page 50 must be written to zero to enable spi module. figure 78. spi block diagram (1) n ote: 1. refer to figure 1 on page 2, and t able 42 on page 92 for spi pin placement. the interconnection between master and slav e cpus with spi is shown in figure 79. the system consists of two shift registers, and a master clock generator. the spi mas- ter initiates the communication cycle when pulling low the slave select ss pin of the desired slave. master and slave prepare the data to be sent in their respective shift spi2x spi2x divider /2/4/8/16/32/64/128 200 atmega640/1280/1281/2560/2561 2549k?avr?01/07 registers, and the master generates the required clock pulses on the sck line to inter- change data. data is always shifted from master to slave on the master out ? slave in, mosi, line, and from slave to master on the master in ? slave out, miso, line. after each data packet, the master will synchronize the slave by pulling high the slave select, ss , line. w hen configured as a master, the spi interface has no automatic control of the ss line. this must be handled by user software before communication can start. w hen this is done, writing a byte to the spi data register starts the spi clock generator, and the hardware shifts the eight bits into the slave. after shifting one byte, the spi clock gener- ator stops, setting the end of transmission fl ag (spif). if the spi interrupt enable bit (spie) in the spcr register is set, an interrupt is requested. the master may continue to shift the next byte by writing it into spdr, or signal the end of packet by pulling high the slave select, ss line. the last incoming byte will be kept in the buffer register for later use. w hen configured as a slave, the spi interf ace will remain sleeping with miso tri-stated as long as the ss pin is driven high. in this state, software may update the contents of the spi data register, spdr, but the data will not be shifted out by incoming clock pulses on the sck pin until the ss pin is driven low. as one byte has been completely shifted, the end of transmission flag, spif is set. if the spi interrupt enable bit, spie, in the spcr register is set, an interrupt is requested. the slave may continue to place new data to be sent into spdr before reading the incoming data. the last incoming byte will be kept in the buffer register for later use. figure 79. spi master-slave interconnection the system is single buffered in the transmit direction and double buffered in the receive direction. this means that bytes to be tr ansmitted cannot be written to the spi data register before the entire shift cycle is completed. w hen receiving data, however, a received character must be read from the spi data register before the next character has been completely shifted in. otherwise, the first byte is lost. in spi slave mode, the control logic will sample the incoming signal of the sck pin. to ensure correct sampling of the clock signal , the minimum low and high periods should be: low period: longer than 2 cpu clock cycles high period: longer than 2 cpu clock cycles shift enable 201 atmega640/1280/1281/2560/2561 2549k?avr?01/07 w hen the spi is enabled, the data direction of the mosi, miso, sck, and ss pins is overridden according to table 96. for more details on automatic port overrides, refer to ?alternate port functions? on page 89. n ote: 1. see ?alternate functions of port b? on page 92 for a detailed description of how to define the direction of the user defined spi pins. the following code examples show how to initialize the spi as a master and how to per- form a simple transmission. ddr_spi in the ex amples must be replaced by the actual data direction register controlling the spi pins. dd_mosi, dd_miso and dd_sck must be replaced by the actual data direction bits for these pins. e.g. if mosi is placed on pin pb5, replace dd_mosi with ddb5 and ddr_spi with ddrb. table 96. spi pin overrides (1) pin direction, master spi direction, slave spi mosi user defined input miso input user defined sck user defined input ss user defined input 202 atmega640/1280/1281/2560/2561 2549k?avr?01/07 n ote: 1. see ?about code examples? on page 9. assembly code example (1) spi_masterinit: ; set mosi and sck output, all others input ldi r17,(1< 205 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 80. spi transfer format with cpha = 0 figure 81. spi transfer format with cpha = 1 table 97. cpol functionality leading edge trailing edge spi mode cpol=0, cpha=0 sample (rising) setup (falling) 0 cpol=0, cpha=1 setup (rising) sample (falling) 1 cpol=1, cpha=0 sample (falling) setup (rising) 2 cpol=1, cpha=1 setup (falling) sample (rising) 3 bit 1 bit 6 lsb msb sck (cpol = 0) mode 0 sample i mosi/miso change 0 mosi pin change 0 miso pin sck (cpol = 1) mode 2 ss msb lsb bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 msb first (dord = 0) lsb first (dord = 1) sck (cpol = 0) mode 1 sample i mosi/miso change 0 mosi pin change 0 miso pin sck (cpol = 1) mode 3 ss msb lsb bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 lsb msb msb first (dord = 0) lsb first (dord = 1) 206 atmega640/1280/1281/2560/2561 2549k?avr?01/07 register description spcr ? spi control register ? bit 7 ? spie: spi interrupt enable this bit causes the spi interrupt to be execut ed if spif bit in the spsr register is set and the if the global interrupt enable bit in sreg is set. ? bit 6 ? spe: spi enable w hen the spe bit is written to one, the spi is enabled. this bit must be set to enable any spi operations. ? bit 5 ? dord: data order w hen the dord bit is written to one, the lsb of the data word is transmitted first. w hen the dord bit is written to zero, the msb of the data word is transmitted first. ? bit 4 ? mstr: master/slave select this bit selects master spi mode when written to one, and slave spi mode when written logic zero. if ss is configured as an i nput and is driven low while mstr is set, mstr will be cleared, and spif in spsr will become set. the user will then have to set mstr to re-enable spi master mode. ? bit 3 ? cpol: clock polarity w hen this bit is written to one, sck is high when idle. w hen cpol is written to zero, sck is low when idle. refer to figure 80 and figure 81 for an example. the cpol func- tionality is summarized below: ? bit 2 ? cpha: clock phase the settings of the clock phase bit (cpha) determine if data is sampled on the leading (first) or trailing (last) edge of sck. refer to figure 80 and figure 81 for an example. the cpol functionality is summarized below: bit 76543210 0x2c (0x4c) spie spe dord mstr cpol cpha spr1 spr0 spcr read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 table 98. cpol functionality cpol leading edge trailing edge 0 rising falling 1 falling rising table 99. cpha functionality cpha leading edge trailing edge 0 sample setup 1 setup sample 207 atmega640/1280/1281/2560/2561 2549k?avr?01/07 ? bits 1, 0 ? spr1, spr0: spi clock rate select 1 and 0 these two bits control the sck rate of the device configured as a master. spr1 and spr0 have no effect on the slave. the relationship between sck and the oscillator clock frequency f osc is shown in the following table: spsr ? spi status register ? bit 7 ? spif: spi interrupt flag w hen a serial transfer is complete, the spif flag is set. an interrupt is generated if spie in spcr is set and global interrupts are enabled. if ss is an input and is driven low when the spi is in master mo de, this will also set the sp if flag. spif is cleared by hardware when executing the corresponding in terrupt handling vector. alternatively, the spif bit is cleared by first reading the spi status register with spif set, then accessing the spi data register (spdr). ? bit 6 ? wcol: write collision flag the w col bit is set if the spi data register (spdr) is written during a data transfer. the w col bit (and the spif bit) are cleared by first reading the spi status register with w col set, and then accessing the spi data register. ? bit 5:1 ? res: reserved bits these bits are reserved bits and will always read as zero. ? bit 0 ? spi2x: double spi speed bit w hen this bit is written logic one the spi speed (sck frequency) will be doubled when the spi is in master mode (see table 100). this means that the minimum sck period will be two cpu clock periods. w hen the spi is configured as slave, the spi is only guaranteed to work at f osc /4 or lower. the spi interface on the atmega640/1280/1281/2560/2561 is also used for program memory and eeprom downloading or upload ing. see ?serial downloading? on page 356 for serial programming and verification. table 100. relationship between sck a nd the oscillator frequency spi2x spr1 spr0 sck frequency 000 f osc / 4 001 f osc / 16 010 f osc / 64 011 f osc / 128 100 f osc / 2 101 f osc / 8 110 f osc / 32 111 f osc / 64 bit 76543210 0x2d (0x4d) spif wcol ? ? ? ? ? spi2x spsr read/ w riterrrrrrrr/ w initial value00000000 208 atmega640/1280/1281/2560/2561 2549k?avr?01/07 spdr ? spi data register the spi data register is a read/write register used for data transfer between the regis- ter file and the spi shift register. w riting to the register initiates data transmission. reading the register causes the shift register receive buffer to be read. bit 76543210 0x2e (0x4e) msb lsb spdr read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value x x x x x x x x undefined 209 atmega640/1280/1281/2560/2561 2549k?avr?01/07 usart the universal synchronous and asynchronous serial receiver and transmitter (usart) is a highly flexible serial communication device. the main features are: ? full duplex operation (i ndependent serial receive and transmit registers) ? asynchronous or synchronous operation ? master or slave clocked synchronous operation ? high resolution baud rate generator ? supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits ? odd or even parity generation and parity check supported by hardware ? data overrun detection ? framing error detection ? noise filtering includes false start bit detection and digital low pass filter ? three separate interrupts on tx complete , tx data register empty and rx complete ? multi-processor communication mode ? double speed asynchronous communication mode quad usart the atmega640/1280/2560 has four usart?s, usart0, usart1, usart2, and usart3. the functionality for all four usart?s is described below. usart0, usart1, usart2, and usart3 have different i/o registers as shown in ?register summary? on page 416. overview a simplified block diagram of the usart transmitter is shown in figure 82 on page 210. cpu accessible i/o registers and i/o pins are shown in bold. the power reducion usart0 bit, prusart0, in ?prr0 ? power reduction register 0? on page 55 must be disabled by writing a logical zero to it. the power reducion usart1 bit, prusart1, in ?prr1 ? power reduction register 1? on page 56 must be disabled by writing a logical zero to it. the power reducion usart2 bit, prusart2, in ?prr1 ? power reduction register 1? on page 56 must be disabled by writing a logical zero to it. the power reducion usart3 bit, prusart3, in ?prr1 ? power reduction register 1? on page 56 must be disabled by writing a logical zero to it. 210 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 82. usart block diagram (1) n ote: 1. see figure 1 on page 2, figure 3 on p age 4, table 48 on page 97, table 51 on page 99, table 60 on page 107 and table 63 on page 109 for usart pin placement. the dashed boxes in the block diagram separate the three main parts of the usart (listed from the top): clock generator, transmitter and receiver. control registers are shared by all units. the clock generation l ogic consists of sync hronization logic for external clock input used by synchronous slave operation, and the baud rate generator. the xckn (transfer clock) pin is only used by synchronous transfer mode. the trans- mitter consists of a single write buffer, a serial shift register, parity generator and control logic for handling different serial frame formats. the write buffer allows a contin- uous transfer of data without any delay between frames. the receiver is the most complex part of the usart module due to its clock and data recovery units. the recov- ery units are used for asynchronous data reception. in addition to the recovery units, the receiver includes a parity checker, control logic, a shift register and a two level receive buffer (udrn). the receiver supports the same frame formats as the transmit- ter, and can detect frame error, data overrun and parity errors. parity generator ubrr[h:l] udr (transmit) ucsra ucsrb ucsrc baud rate generator transmit shift register receive shift register rxd txd pin control udr (receive) pin control xck data recovery clock recovery pin control tx control rx control parity checker data bus osc sync logic clock generator transmitter receiver 211 atmega640/1280/1281/2560/2561 2549k?avr?01/07 clock generation the clock generation logic generates the bas e clock for the transmitter and receiver. the usartn supports four modes of clock operation: n ormal asynchronous, double speed asynchronous, master synchronous and slave synchronous mode. the umseln bit in usart control and status register c (ucsrnc) selects between asynchronous and synchronous operation. double speed (asynchronous mode only) is controlled by the u2xn found in the ucsrna register. w hen using synchronous mode (umseln = 1), the data direction register for the xckn pin (ddr_xckn) co ntrols whether the clock source is internal (master mode) or external (slave mode). the xckn pin is only active when using synchronous mode. figure 83 shows a block diagram of the clock generation logic. figure 83. clock generation logic, block diagram signal description: txclk transmitter clock (internal signal). rxclk receiver base clock (internal signal). xcki input from xck pin (internal signal). used for synchronous slave operation. xcko clock output to xck pin (internal signal). used for synchronous master operation. f osc xtal pin frequency (system clock). prescaling down-counter /2 ubrr /4 /2 fosc ubrr+1 sync register osc xck pin txclk u2x umsel ddr_xck 0 1 0 1 xcki xcko ddr_xck rxclk 0 1 1 0 edge detector ucpol 212 atmega640/1280/1281/2560/2561 2549k?avr?01/07 internal clock generation ? the baud rate generator internal clock generation is used for the asynchronous and the synchronous master modes of operation. the description in this section refers to figure 83. the usart baud rate register (ubrrn) and the down-counter connected to it func- tion as a programmable prescaler or baud rate generator. the down-counter, running at system clock (f osc ), is loaded with the ubrrn value each time the counter has counted down to zero or when the ubrrln register is written. a clock is generated each time the counter reaches zero. this clock is the baud rate generator clock output (= f osc /(ubrrn+1)). the transmitter divides the baud rate generator clock output by 2, 8 or 16 depending on mode. the baud rate generator output is used directly by the receiver?s clock and data recovery units. however, the recovery units use a state machine that uses 2, 8 or 16 states dependi ng on mode set by the state of the umseln, u2xn and ddr_xckn bits. table 101 contains equations for calculating the baud rate (in bits per second) and for calculating the ubrrn value for each mode of operation using an internally generated clock source. n ote: 1. the baud rate is defined to be the transfer rate in bit per second (bps) baud baud rate (in bits per second, bps) f osc system oscillator clock frequency ubrrn contents of the ubrrhn an d ubrrln registers, (0-4095) table 101. equations for calculating baud rate register setting operating mode equation for calculating baud rate (1) equation for calculating ubrr value asynchronous n ormal mode (u2xn = 0) asynchronous double speed mode (u2xn = 1) synchronous master mode baud f osc 16 ubrr n 1 + () ----------------------------------------- - = ubrr n f osc 16 baud ----------------------- - 1 ? = baud f osc 8 ubrr n 1 + () -------------------------------------- - = ubrr n f osc 8 baud -------------------- 1 ? = baud f osc 2 ubrr n 1 + () -------------------------------------- - = ubrr n f osc 2 baud -------------------- 1 ? = 213 atmega640/1280/1281/2560/2561 2549k?avr?01/07 some examples of ubrrn values for some system clock frequencies are found in table 109 on page 232. double speed operation (u2xn) the transfer rate can be doubled by setting the u2xn bit in ucsrna. setting this bit only has effect for the asynchronous operation. set this bit to zero when using synchro- nous operation. setting this bit will reduce the divisor of the baud rate di vider from 16 to 8, effectively doubling the transfer rate for asynchronous communication. n ote however that the receiver will in this case only use half the number of samples (reduced from 16 to 8) for data sampling and clock recovery, and therefore a more accurate baud rate setting and system clock are required when this mode is used. for the transmitter, there are no downsides. external clock external clocking is used by the synchron ous slave modes of operation. the description in this section refers to figure 83 for details. external clock input from the xckn pin is sa mpled by a synchronization register to mini- mize the chance of meta-stability. the output from the synchronization register must then pass through an edge detector before it can be used by the transmitter and receiver. this process introduces a two cp u clock period delay and therefore the max- imum external xckn clock frequency is limited by the following equation: n ote that f osc depends on the stability of the system clock source. it is therefore recom- mended to add some margin to avoid possible loss of data due to frequency variations. synchronous clock operation w hen synchronous mode is used (umseln = 1), the xckn pin will be used as either clock input (slave) or cl ock output (master). the dependency between the clock edges and data sampling or data change is the same. the basic principle is that data input (on rxdn) is sampled at the opposite xckn cl ock edge of the edge the data output (txdn) is changed. figure 84. synchronous mode xckn timing. the ucpoln bit ucrsc selects which xckn cl ock edge is used for data sampling and which is used for data change. as figure 84 shows, when ucpoln is zero the data will be changed at rising xckn edge and sampled at falling xckn edge. if ucpoln is set, the data will be changed at falling xckn edge and sampled at rising xckn edge. f xck f osc 4 ----------- < rxd / txd xck rxd / txd xck ucpol = 0 ucpol = 1 sample sample 214 atmega640/1280/1281/2560/2561 2549k?avr?01/07 frame formats a serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit fo r error checking. the usart accepts all 30 combinations of the following as valid frame formats: ? 1 start bit ? 5, 6, 7, 8, or 9 data bits ? no, even or odd parity bit ? 1 or 2 stop bits a frame starts with the start bit followed by the least significant data bit. then the next data bits, up to a total of nine, are succeeding, ending with the most significant bit. if enabled, the parity bit is inserted after the data bits, before the stop bits. w hen a com- plete frame is transmitted, it can be dire ctly followed by a new frame, or the communication line can be set to an idle (high) state. figure 85 illustrates the possible combinations of the frame formats. bits inside brackets are optional. figure 85. frame formats st start bit, always low. (n) data bits (0 to 8). p parity bit. can be odd or even. sp stop bit, always high. idle n o transfers on the communication line (rxdn or txdn). an idle line must be high. the frame format used by the usart is set by the ucszn2:0, upmn1:0 and usbsn bits in ucsrnb and ucsrnc. the receiv er and transmitter use the same setting. n ote that changing the setting of any of these bits will corrupt all ongoing communica- tion for both the receiver and transmitter. the usart character size (ucszn2:0) bits select the number of data bits in the frame. the usart parity mode (upmn1:0) bits enable and set the type of parity bit. the selec- tion between one or two stop bits is done by the usart stop bit select (usbsn) bit. the receiver ignores the second stop bit. an fe (frame error) will therefore only be detected in the cases where the first stop bit is zero. parity bit calculation the parity bit is calculated by doing an exclus ive-or of all the data bits. if odd parity is used, the result of the exclusive or is inverted. the parity bit is located between the last data bit and first stop bit of a serial frame. the relation between the parity bit and data bits is as follows:: p even parity bit using even parity p odd parity bit using odd parity d n data bit n of the character 1 0 2 3 4 [5] [6] [7] [8] [p] st sp1 [sp2] (st / idle) (idle) frame p even d n 1 ? d 3 d 2 d 1 d 0 0 p odd d n 1 ? d 3 d 2 d 1 d 0 1 = = 215 atmega640/1280/1281/2560/2561 2549k?avr?01/07 usart initialization the usart has to be initialized before any communication can take place. the initial- ization process normally consists of setting the baud rate, setting frame format and enabling the transmitter or the receiver depending on the usage. for interrupt driven usart operation, the global interrupt flag should be cleared (and interrupts globally disabled) when doing the initialization. before doing a re-initialization with changed baud rate or frame format, be sure that there are no ongoing transmissions during th e period the registers are changed. the txcn flag can be used to check that the transmitter has completed all transfers, and the rxc flag can be used to check that there are no unread data in the receive buffer. n ote that the txcn flag must be cleared before each transmission (before udrn is written) if it is us ed for this purpose. the following simple usart initialization code examples show one assembly and one c function that are equal in functionality. the examples assume asynchronous opera- tion using polling (no interrupts enabled) and a fixed frame format. the baud rate is given as a function parameter. for the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers. n ote: 1. see ?about code examples? on page 9. assembly code example (1) usart_init: ; set baud rate out ubrrnh, r17 out ubrrnl, r16 ; enable receiver and transmitter ldi r16, (1< 219 atmega640/1280/1281/2560/2561 2549k?avr?01/07 data reception ? the usart receiver the usart receiver is enabled by writing the receive enable (rxe n n) bit in the ucsrnb register to one. w hen the receiver is enabled, the normal pin operation of the rxdn pin is overridden by the usart and given the function as the receiver?s serial input. the baud rate, mode of operation and frame format must be set up once before any serial reception can be done. if synchronous operation is used, the clock on the xckn pin will be used as transfer clock. receiving frames with 5 to 8 data bits the receiver starts data reception when it detects a valid start bit. each bit that follows the start bit will be sampled at the baud rate or xckn clock, and shifted into the receive shift register until the first stop bit of a frame is received. a second stop bit will be ignored by the receiver. w hen the first stop bit is received, i.e., a complete serial frame is present in the receive shift register, the contents of the shift register will be moved into the receive buffer. the receive buffer can then be read by reading the udrn i/o location. the following code example shows a simple usart receive function based on polling of the receive complete (rxcn) flag. w hen using frames with less than eight bits the most significant bits of the data read fr om the udrn will be masked to zero. the usart has to be initialized before the function can be used. n ote: 1. see ?about code examples? on page 9. the function simply waits for data to be pres ent in the receive buffer by checking the rxcn flag, before reading the buffer and returning the value. receiving frames with 9 data bits if 9-bit characters are used (ucszn=7) the ninth bit must be read from the rxb8n bit in ucsrnb before reading the low bits from the udrn. this rule applies to the fen, dorn and upen status flags as well. read status from ucsrna, then data from udrn. reading the udrn i/o location will change the state of the receive buffer fifo and consequently the txb8n, fen, dorn and upen bits, which all are stored in the fifo, will change. the following code example shows a simple u sart receive function that handles both nine bit characters and the status bits. assembly code example (1) usart_receive: ; wait for data to be received sbis ucsrna, rxcn rjmp usart_receive ; get and return received data from buffer in r16, udrn ret c code example (1) unsigned char usart_receive( void ) { /* wait for data to be received */ while ( !(ucsrna & (1< 221 atmega640/1280/1281/2560/2561 2549k?avr?01/07 receive compete flag and interrupt the usart receiver has one flag that indicates the receiver state. the receive complete (rxcn) flag indicate s if there are unread data present in the receive buffer. this flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). if the receiver is disabled (rxe n n = 0), the receive buffer will be flushed and cons equently the rxcn bit will become zero. w hen the receive complete interrupt enable (rxcien) in ucsrnb is set, the usart receive complete inte rrupt will be executed as long as the rxcn flag is set (provided that global interrupts are enabled). w hen interrupt-driven data reception is used, the receive complete routine must read the received data from udrn in order to clear the rxcn flag, otherwise a new interrupt will o ccur once the interrupt routine terminates. receiver error flags the usart receiver has three error flags: frame error (fen), data overrun (dorn) and parity error (upen). all can be accessed by reading ucsrna. common for the error flags is that they are located in the receive buffer together with the frame for which they indicate the error status. due to the buffering of the error flags, the ucsrna must be read before the receive buffer (udrn), since reading the udrn i/o location changes the buffer read location. another equality for the error flags is that they can not be altered by software doing a write to the flag location. however, all flags must be set to zero when the ucsrna is wri tten for upward compatibility of future usart implementa- tions. n one of the error flags can generate interrupts. the frame error (fen) flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer. the fen flag is zero when the stop bit was correctly read (as one), and the fen flag will be one when the stop bit was incorre ct (zero). this flag can be used for detecting out-of-sync c onditions, detecting break conditions and protocol handling. the fen flag is not affected by the setting of the usbsn bit in ucs- rnc since the receiver ignores all, except for the first, stop bits. for compatibility with future devices, always set this bit to zero when writing to ucsrna. the data overrun (dorn) flag indicates data loss due to a receiver buffer full condi- tion. a data overrun occurs when the receive buffer is full (two char acters), it is a new character waiting in the receive shift register, and a new start bit is detected. if the dorn flag is set there was one or more serial frame lost between the frame last read from udrn, and the next frame read from udrn. for compatibility with future devices, always write this bit to zero when writing to ucsrna. t he dorn flag is cleared when the frame received was successfully moved from the shift register to the receive buffer. the parity error (upen) flag indicates that the next frame in the receive buffer had a parity error when received. if parity chec k is not enabled the upen bit will always be read zero. for compatibility with future devices, always set this bit to zero when writing to ucsrna. for more details see ?parity bit calculation? on page 214 and ?parity checker? on page 221. parity checker the parity checker is active when the hi gh usart parity mode (upmn1) bit is set. type of parity check to be performed (odd or even) is selected by the upmn0 bit. w hen enabled, the parity checker calculates the par ity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. the result of the check is stored in the receive buffer together with the received data and stop bits. the parity error (upen) flag can then be read by software to check if the frame had a parity error. the upen bit is set if the next character that can be read from the receive buffer had a parity error when received and the parity checking was enabled at that point (upmn1 = 1). this bit is valid until the re ceive buffer (udrn) is read. 222 atmega640/1280/1281/2560/2561 2549k?avr?01/07 disabling the receiver in contrast to the transmitter, disabling of the receiver will be immediate. data from ongoing receptions w ill therefore be lost. w hen disabled (i.e., the rxe n n is set to zero) the receiver will no longer override the nor mal function of the rxdn port pin. the receiver buffer fifo will be flushed when the receiver is disabled. remaining data in the buffer will be lost flushing the receive buffer the receiver buffer fifo will be flushed when the receiver is disabled, i.e., the buffer will be emptied of its contents. unread data will be lost. if the buffer has to be flushed during normal operation, due to for instance an error condition, read the udrn i/o loca- tion until the rxcn flag is cleared. the following code example shows how to flush the receive buffer. n ote: 1. see ?about code examples? on page 9. assembly code example (1) usart_flush: sbis ucsrna, rxcn ret in r16, udrn rjmp usart_flush c code example (1) void usart_flush( void ) { unsigned char dummy; while ( ucsrna & (1< 224 atmega640/1280/1281/2560/2561 2549k?avr?01/07 are emphasized on the figure by having the sample number inside boxes. the majority voting process is done as follows: if two or all three samples have high levels, the received bit is registered to be a logic 1. if two or all three samples have low levels, the received bit is registered to be a logic 0. this majority voting process acts as a low pass filter for the incoming signal on the rxdn pin. the recovery process is then repeated until a complete frame is received. including the first stop bit. n ote that the receiver only uses the first stop bit of a frame. figure 88 shows the sampling of the stop bit and the earliest possible beginning of the start bit of the next frame. figure 88. stop bit sampling and n ext start bit sampling the same majority voting is done to the stop bit as done for the other bits in the frame. if the stop bit is registered to have a logic 0 value, the frame error (fen) flag will be set. a new high to low transition indicating the start bit of a new frame can come right after the last of the bits used for majority voting. for n ormal speed mode, the first low level sample can be at point marked (a) in figur e 88. for double speed mode the first low level must be delayed to (b). (c) marks a stop bit of full length. the early start bit detec- tion influences the operational range of the receiver. asynchronous operational range the operational range of the receiver is dependent on the mismatch between the received bit rate and the internally generated baud rate. if the transmitter is sending frames at too fast or too slow bit rates, or the internally generated baud rate of the receiver does not have a si milar (see table 102) base fr equency, the receiver will not be able to synchronize the frames to the start bit. the following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate. d sum of character size and parity size (d = 5 to 10 bit) s samples per bit. s = 16 for n ormal speed mode and s = 8 for double speed mode. s f first sample number used for majority voting. s f = 8 for normal speed and s f = 4 for double speed mode. s m middle sample number used for majority voting. s m = 9 for normal speed and s m = 5 for double speed mode. r slow is the ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate. r fast is the ratio of the fastest incoming data rate that can be accepted in relation to the receiver baud rate. 1234567 8 9 10 0/1 0/1 0/1 stop 1 123 4 5 6 0/1 rxd sample (u2x = 0) sample (u2x = 1) (a) (b) (c) r slow d 1 + () s s 1 ? ds ? s f ++ ------------------------------------------ - = r fast d 2 + () s d 1 + () ss m + ----------------------------------- = 225 atmega640/1280/1281/2560/2561 2549k?avr?01/07 table 102 and table 103 list the maximum receiver baud rate error that can be toler- ated. n ote that n ormal speed mode has higher toleration of baud rate variations. the recommendations of the maximum receiver baud rate error was made under the assumption that the receiver and transmitter equally divides the maximum total error. there are two possible sources for the receivers baud rate error. the receiver?s system clock (xtal) will always have some minor in stability over the supp ly voltage range and the temperature range. w hen using a crystal to generate the system clock, this is rarely a problem, but for a resonator the system clock may differ more than 2% depending of the resonators tolerance. the second source for the error is more controllable. the baud rate generator can not always do an exact division of the system frequency to get the baud rate wanted. in this case an ubrr value that gives an acceptable low error can be used if possible. table 102. recommended maximum receiver baud rate error for n ormal speed mode (u2xn = 0) d # (data+parity bit) r slow (%) r fast (%) max total error (%) recommended max receiver error (%) 5 93.20 106.67 +6.67/-6.8 3.0 6 94.12 105.79 +5.79/-5.88 2.5 7 94.81 105.11 +5.11/-5.19 2.0 8 95.36 104.58 +4.58/-4.54 2.0 9 95.81 104.14 +4.14/-4.19 1.5 10 96.17 103.78 +3.78/-3.83 1.5 table 103. recommended maximum receiver baud rate error for double speed mode (u2xn = 1) d # (data+parity bit) r slow (%) r fast (%) max total error (%) recommended max receiver error (%) 5 94.12 105.66 +5.66/-5.88 2.5 6 94.92 104.92 +4.92/-5.08 2.0 7 95.52 104,35 +4.35/-4.48 1.5 8 96.00 103.90 +3.90/-4.00 1.5 9 96.39 103.53 +3.53/-3.61 1.5 10 96.70 103.23 +3.23/-3.30 1.0 226 atmega640/1280/1281/2560/2561 2549k?avr?01/07 multi-processor communication mode setting the multi-processor communicati on mode (mpcmn) bit in ucsrna enables a filtering function of incoming frames received by the usart receiver. frames that do not contain address in formation will be ignored and not put into the receive buffer. this effectively reduces the number of incomi ng frames that has to be handled by the cpu, in a system with multiple mcus that comm unicate via the same serial bus. the trans- mitter is unaffected by the mpcmn setting, bu t has to be used differently when it is a part of a system utilizing the mu lti-processor communication mode. if the receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop bit indicates if the frame contains data or address information. if the receiver is set up for frames with nine data bits, then the ninth bit (rxb8n) is used for identifying address and data frames. w hen the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. w hen the frame type bit is zero the frame is a data frame. the multi-processor communication mode enables several slave mcus to receive data from a master mcu. this is done by first decoding an address frame to find out which mcu has been addressed. if a particular slav e mcu has been addressed, it will receive the following data frames as normal, while the ot her slave mcus will ignore the received frames until another address frame is received. using mpcmn for an mcu to act as a master mcu, it can use a 9-bit character frame format (ucszn = 7). the ninth bit (txb8n) must be set when an address frame (txb8n = 1) or cleared when a data frame (txb = 0) is being transmitted. the slave mcus must in this case be set to use a 9-bit character frame format. the following procedure should be used to exchange data in multi-processor communi- cation mode: 1. all slave mcus are in multi-processo r communication mode (mpcmn in ucs- rna is set). 2. the master mcu sends an address frame, and all slaves receive and read this frame. in the slave mcus, the rxcn fl ag in ucsrna will be set as normal. 3. each slave mcu reads the udrn regist er and determines if it has been selected. if so, it clears the mpcmn bit in ucsrna, otherwise it waits for the next address byte and keeps the mpcmn setting. 4. the addressed mcu will rece ive all data frames until a new address frame is received. the other slave mcus, which st ill have the mpcmn bit set, will ignore the data frames. 5. w hen the last data frame is received by the addressed mcu, the addressed mcu sets the mpcmn bit and waits for a new address frame from master. the process then repeats from 2. using any of the 5- to 8-bit character frame formats is possible, but impractical since the receiver must change between using n and n+1 character frame formats. this makes full-duplex operation difficult since the transmitter and receiver uses the same charac- ter size setting. if 5- to 8-bit character frames are used, the transmitter must be set to use two stop bit (usbsn = 1) since the first st op bit is used for indi cating the frame type. do not use read-modify- w rite instructions (sbi and cbi) to set or clear the mpcmn bit. the mpcmn bit shares the same i/o location as the txcn flag and this might acciden- tally be cleared when using sbi or cbi instructions. 227 atmega640/1280/1281/2560/2561 2549k?avr?01/07 register description the following section describes the usart?s registers. udrn ? usart i/o data register n the usart transmit data buffer register and usart receive data buffer registers share the same i/o address referred to as usart data register or udrn. the trans- mit data buffer register (txb) will be t he destination for data written to the udrn register location. reading the udrn register location will return the contents of the receive data buffer register (rxb). for 5-, 6-, or 7-bit characters the upper unus ed bits will be ignored by the transmitter and set to zero by the receiver. the transmit buffer can only be written w hen the udren flag in the ucsrna register is set. data written to udrn when the udren flag is not set, will be ignored by the usart transmitter. w hen data is written to the transmit buffer, and the transmitter is enabled, the transmitter will lo ad the data into the transm it shift register when the shift register is empty. then the data will be serially transmitted on the txdn pin. the receive buffer consists of a two level fifo. the fifo will change its state whenever the receive buffer is accessed. due to this behavior of the receive buffer, do not use read-modify- w rite instructions (sbi and cbi) on this location. be careful when using bit test instructions (sbic and sbis), since these also will ch ange the state of the fifo. ucsrna ? usart control and status register a ? bit 7 ? rxcn: usart receive complete this flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread data). if the receiver is dis- abled, the receive buffer will be flushed and consequently the rxcn bit will become zero. the rxcn flag can be used to generate a receive complete interrupt (see description of the rxcien bit). ? bit 6 ? txcn: usart transmit complete this flag bit is set when the entire frame in the transmit shift register has been shifted out and there are no new data currently present in the transmit buffer (udrn). the txcn flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. the txcn flag can generate a transmit complete interrupt (see description of the txcien bit). ? bit 5 ? udren: usart data register empty the udren flag indicates if the transmit bu ffer (udrn) is ready to receive new data. if udren is one, the buffer is empty, and therefore ready to be written. the udren flag can generate a data register empty interrupt (see description of the udrien bit). udren is set after a reset to indicate that the transmitter is ready. bit 76543210 rxb[7:0] udrn (read) txb[7:0] udrn (write) read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 rxcn txcn udren fen dorn upen u2xn mpcmn ucsrna read/ w rite r r/ w rrrrr/ w r/ w initial value00100000 228 atmega640/1280/1281/2560/2561 2549k?avr?01/07 ? bit 4 ? fen: frame error this bit is set if the next character in the receive buffer had a frame error when received. i.e., when the first stop bit of the next character in the receive buffer is zero. this bit is valid until the receive buffer (u drn) is read. the fen bit is zero when the stop bit of received data is one. always set th is bit to zero when writing to ucsrna. ? bit 3 ? dorn: data overrun this bit is set if a data overrun condition is detected. a data overrun occurs when the receive buffer is full (two char acters), it is a new characte r waiting in the receive shift register, and a new start bit is detected. this bit is valid until the receive buffer (udrn) is read. always set this bit to zero when writing to ucsrna. ? bit 2 ? upen: usart parity error this bit is set if the next character in the receive buffer had a parity error when received and the parity checking was enabled at that point (upmn1 = 1). this bit is valid until the receive buffer (udrn) is re ad. always set this bit to zero when writing to ucsrna. ? bit 1 ? u2xn: double the usart transmission speed this bit only has effect for the asynchronous operation. w rite this bit to zero when using synchronous operation. w riting this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effec- tively doubling the transfer rate for asynchronous communication. ? bit 0 ? mpcmn: multi-processor communication mode this bit enables the multi-processor communication mode. w hen the mpcmn bit is writ- ten to one, all the incoming frames received by the usart receiver that do not contain address information will be ignored. the transmitter is unaffected by the mpcmn set- ting. for more detailed information see ?multi-processor communication mode? on page 226. ucsrnb ? usart control and status register n b ? bit 7 ? rxcien: rx complete interrupt enable n w riting this bit to one enables interrupt on the rxcn flag. a usart receive complete interrupt will be generat ed only if the rxcien bit is wr itten to one, t he global interrupt flag in sreg is written to one an d the rxcn bit in ucsrna is set. ? bit 6 ? txcien: tx complete interrupt enable n w riting this bit to one enables interrupt on the txcn flag. a usart transmit complete interrupt will be generated only if the txcien bit is written to one, the global interrupt flag in sreg is written to one and the txcn bit in ucsrna is set. bit 76543210 rxcien txcien udrien rxenn txenn ucszn2 rxb8n txb8n ucsrnb read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w rr/ w initial value 0 0 0 0 0 0 0 0 229 atmega640/1280/1281/2560/2561 2549k?avr?01/07 ? bit 5 ? udrien: usart data register empty interrupt enable n w riting this bit to one enables interrupt on the udren flag. a data register empty interrupt will be generated only if the udrien bit is written to one, the global interrupt flag in sreg is written to one and the udren bit in ucsrna is set. ? bit 4 ? rxenn: receiver enable n w riting this bit to one enables the usart receiver. the receiver will override normal port operation for the rxdn pin when enabled. disabling the receiver will flush the receive buffer invalidating the fen, dorn, and upen flags. ? bit 3 ? txenn: transmitter enable n w riting this bit to one enables the usart transmitter. the trans mitter will override nor- mal port operation for the txdn pin when enabled. the disabling of the transmitter (writing txe n n to zero) will not become effective until ongoing and pending transmis- sions are completed, i.e., when the transmit shift register and transmit buffer register do not contain data to be transmitted. w hen disabled, the tran smitter will no longer override the txdn port. ? bit 2 ? ucszn2: character size n the ucszn2 bits combined with the ucszn1:0 bit in ucsrnc sets the number of data bits (character size) in a frame the receiver and transmitter use. ? bit 1 ? rxb8n: receive data bit 8 n rxb8n is the ninth data bit of the received character when operating with serial frames with nine data bits. must be read before reading the low bits from udrn. ? bit 0 ? txb8n: transmit data bit 8 n txb8n is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. must be written before writing the low bits to udrn. ucsrnc ? usart control and status register n c ? bits 7:6 ? umseln1:0 usart mode select these bits select the mode of operation of the usartn as shown in table 104. n ote: 1. see ?usart in spi mode? on page 236 fo r full description of the master spi mode (mspim) operation bit 7 6 5 4 3 2 1 0 umseln1 umseln0 upmn1 upmn0 usbsn ucszn1 ucszn0 ucpoln ucsrnc read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 1 1 0 table 104. umseln bits settings umseln1 umseln0 mode 0 0 asynchronous usart 0 1 synchronous usart 1 0 (reserved) 1 1 master spi (mspim) (1) 230 atmega640/1280/1281/2560/2561 2549k?avr?01/07 ? bits 5:4 ? upmn1:0: parity mode these bits enable and set type of parity generation and check. if enabled, the transmit- ter will automatically generate and send th e parity of the transmitted data bits within each frame. the receiver will generate a parity value for the incoming data and com- pare it to the upmn setting. if a mismatch is detected, the upen flag in ucsrna will be set. ? bit 3 ? usbsn: stop bit select this bit selects the number of stop bits to be inserted by the transmitter. the receiver ignores this setting. ? bit 2:1 ? ucszn1:0: character size the ucszn1:0 bits combined with the ucszn2 bit in ucsrnb sets the number of data bits (character size) in a frame the receiver and transmitter use. table 105. upmn bits settings upmn1 upmn0 parity mode 0 0 disabled 01reserved 1 0 enabled, even parity 1 1 enabled, odd parity table 106. usbs bit settings usbsn stop bit(s) 01-bit 12-bit table 107. ucszn bits settings ucszn2 ucszn1 ucszn0 character size 0005-bit 0016-bit 0107-bit 0118-bit 100reserved 101reserved 110reserved 1119-bit 231 atmega640/1280/1281/2560/2561 2549k?avr?01/07 ? bit 0 ? ucpoln: clock polarity this bit is used for synchronous mode only. w rite this bit to zero when asynchronous mode is used. the ucpoln bit sets the relationship between data output change and data input sample, and the synchronous clock (xckn). ubrrnl and ubrrnh ? usart baud rate registers ? bit 15:12 ? reserved bits these bits are reserved for future use. fo r compatibility with future devices, these bit must be written to zero when ubrrh is written. ? bit 11:0 ? ubrr11:0: usart baud rate register this is a 12-bit register which contains the usart baud rate. the ubrrh contains the four most significant bits, and the ubrrl contai ns the eight least significant bits of the usart baud rate. ongoing transmissions by the transmitter and receiver will be cor- rupted if the baud rate is changed. w riting ubrrl will trigger an immediate update of the baud rate prescaler. table 108. ucpoln bit settings ucpoln transmitted data changed (output of txdn pin) received data sampled (input on rxdn pin) 0 rising xckn edge falling xckn edge 1 falling xckn edge rising xckn edge bit 151413121110 9 8 ???? ubrr[11:8] ubrrhn ubrr[7:0] ubrrln 76543210 read/ w riterrrrr/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 00000000 232 atmega640/1280/1281/2560/2561 2549k?avr?01/07 examples of baud rate setting for standard crystal and resonator frequencies, the most commonly used baud rates for asynchronous operation can be generated by using the ubrr settings in table 109 to table 112. ubrr values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table. higher error ratings are acceptable, but the receiver will have less noise resistance when the error rati ngs are high, especially for large serial frames (see ?asynchronous operational range? on page 224). the error values are calculated using the following equation: error[%] baudrate closest match baudrate -------------------------------------------------------- 1 ? ?? ?? 100% ? = table 109. examples of ubrrn settings for comm only used oscillator frequencies baud rate (bps) f osc = 1.0000 mhz f osc = 1.8432 mhz f osc = 2.0000 mhz u2xn = 0u2xn = 1u2xn = 0u2xn = 1u2xn = 0u2xn = 1 ubrr error ubrr error ubrr error ubrr error ubrr error ubrr error 2400 250.2%510.2%470.0%950.0%510.2%1030.2% 4800 120.2%250.2%230.0%470.0%250.2%510.2% 9600 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2% 14.4k 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 19.2k 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 28.8k 1 8.5% 3 8.5% 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 38.4k 1 -18.6% 2 8.5% 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 57.6k 0 8.5% 1 8.5% 1 0.0% 3 0.0% 1 8.5% 3 8.5% 76.8k ? ? 1 -18.6% 1 -25.0% 2 0.0% 1 -18.6% 2 8.5% 115.2k ? ? 0 8.5% 0 0.0% 1 0.0% 0 8.5% 1 8.5% 230.4k??????00.0%???? 250k??????????00.0% max. (1) 62.5 kbps 125 kbps 115.2 kbps 2 30.4 kbps 125 kbps 250 kbps 1. ubrr = 0, error = 0.0% 233 atmega640/1280/1281/2560/2561 2549k?avr?01/07 table 110. examples of ubrrn settings for commonly used oscillator fre quencies (continued) baud rate (bps) f osc = 3.6864 mhz f osc = 4.0000 mhz f osc = 7.3728 mhz u2xn = 0u2xn = 1u2xn = 0u2xn = 1u2xn = 0u2xn = 1 ubrr error ubrr error ubrr error ubrr error ubrr error ubrr error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 230.0%470.0%250.2%510.2%470.0%950.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0% 19.2k 11 0.0% 23 0.0% 12 0. 2% 25 0.2% 23 0.0% 47 0.0% 28.8k 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 15 0.0% 31 0.0% 38.4k 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 57.6k 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 76.8k 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 115.2k 1 0.0% 3 0.0% 1 8.5% 3 8.5% 3 0.0% 7 0.0% 230.4k 0 0.0% 1 0.0% 0 8.5% 1 8.5% 1 0.0% 3 0.0% 250k 0 -7.8% 1 -7.8% 0 0.0% 1 0.0% 1 -7.8% 3 -7.8% 0.5m ? ? 0 -7.8% ? ? 0 0.0% 0 -7.8% 1 -7.8% 1m ??????????0-7.8% max. (1) 230.4 kbps 460.8 kbps 250 kbps 0.5 mbps 460.8 kbps 921.6 kbps 1. ubrr = 0, error = 0.0% 234 atmega640/1280/1281/2560/2561 2549k?avr?01/07 table 111. examples of ubrrn settings for commonly used oscillator fre quencies (continued) baud rate (bps) f osc = 8.0000 mhz f osc = 11.0592 mhz f osc = 14.7456 mhz u2xn = 0u2xn = 1u2xn = 0u2xn = 1u2xn = 0u2xn = 1 ubrr error ubrr error ubrr error ubrr error ubrr error ubrr error 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0% 19.2k 25 0.2% 51 0.2% 35 0. 0% 71 0.0% 47 0.0% 95 0.0% 28.8k 16 2.1% 34 -0.8% 23 0.0% 47 0.0% 31 0.0% 63 0.0% 38.4k 12 0.2% 25 0.2% 17 0. 0% 35 0.0% 23 0.0% 47 0.0% 57.6k 8 -3.5% 16 2.1% 11 0.0% 23 0.0% 15 0.0% 31 0.0% 76.8k 6 -7.0% 12 0.2% 8 0.0% 17 0.0% 11 0.0% 23 0.0% 115.2k 3 8.5% 8 -3.5% 5 0.0% 11 0.0% 7 0.0% 15 0.0% 230.4k 1 8.5% 3 8.5% 2 0.0% 5 0.0% 3 0.0% 7 0.0% 250k 1 0.0% 3 0.0% 2 -7.8% 5 -7.8% 3 -7.8% 6 5.3% 0.5m 0 0.0% 1 0.0% ? ? 2 -7.8% 1 -7.8% 3 -7.8% 1m ? ? 0 0.0% ? ? ? ? 0 -7.8% 1 -7.8% max. (1) 0.5 mbps 1 mbps 691.2 kbps 1.3824 mbps 921.6 kbps 1.8432 mbps 1. ubrr = 0, error = 0.0% 235 atmega640/1280/1281/2560/2561 2549k?avr?01/07 table 112. examples of ubrrn settings for commonly used oscillator fre quencies (continued) baud rate (bps) f osc = 16.0000 mhz f osc = 18.4320 mhz f osc = 20.0000 mhz u2xn = 0u2xn = 1u2xn = 0u2xn = 1u2xn = 0u2xn = 1 ubrr error ubrr error ubrr error ubrr error ubrr error ubrr error 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2% 14.4k 68 0.6% 138 -0.1% 79 0.0% 159 0.0% 86 -0.2% 173 -0.2% 19.2k 51 0.2% 103 0.2% 59 0.0% 119 0.0% 64 0.2% 129 0.2% 28.8k 34 -0.8% 68 0.6% 39 0.0% 79 0.0% 42 0.9% 86 -0.2% 38.4k 25 0.2% 51 0.2% 29 0.0% 59 0.0% 32 -1.4% 64 0.2% 57.6k 16 2.1% 34 -0.8% 19 0.0% 39 0.0% 21 -1.4% 42 0.9% 76.8k 12 0.2% 25 0.2% 14 0.0% 29 0.0% 15 1.7% 32 -1.4% 115.2k 8 -3.5% 16 2.1% 9 0.0% 19 0.0% 10 -1.4% 21 -1.4% 230.4k 3 8.5% 8 -3.5% 4 0.0% 9 0.0% 4 8.5% 10 -1.4% 250k 3 0.0% 7 0.0% 4 -7.8% 8 2.4% 4 0.0% 9 0.0% 0.5m 1 0.0% 3 0.0% ? ? 4 -7.8% ? ? 4 0.0% 1m 0 0.0% 1 0.0% ? ? ? ? ? ? ? ? max. (1) 1 mbps 2 mbps 1.152 mbps 2.3 04 mbps 1.25 mbps 2.5 mbps 1. ubrr = 0, error = 0.0% 236 atmega640/1280/1281/2560/2561 2549k?avr?01/07 usart in spi mode the universal synchronous and asynchronous serial receiver and transmitter (usart) can be set to a master spi compliant mode of operation. the master spi mode (mspim) has the following features: ? full duplex, three-wire synchronous data transfer ? master operation ? supports all four spi modes of operation (mode 0, 1, 2, and 3) ? lsb first or msb first data tran sfer (configurable data order) ? queued operation (double buffered) ? high resolution baud rate generator ? high speed operatio n (fxckmax = fck/2) ? flexible interrupt generation overview setting both umseln1:0 bits to one enables the usart in mspim logic. in this mode of operation the spi master control logic takes direct control over the usart resources. these resources include the transmitter and receiver shift register and buffers, and the baud rate generator. the parity generator and checker, the data and clock recovery logic, and the rx and tx control logic is disabled. the usart rx and tx control logic is replaced by a common spi transfer control logic. however, the pin control logic and interrupt generation logic is identical in both modes of operation. the i/o register locations are the same in both modes. however, some of the functional- ity of the control registers changes when using mspim. usart mspim vs. spi the avr usart in mspim mode is fully compatible with the avr spi regarding: ? master mode timing diagram. ? the ucpoln bit functionality is identical to the spi cpol bit. ? the ucphan bit functionality is identical to the spi cpha bit. ? the udordn bit functionality is identical to the spi dord bit. however, since the usart in mspim mode reuses the usart resources, the use of the usart in mspim mode is somewhat different compared to the spi. in addition to differences of the control register bits, and that only master operation is supported by the usart in mspim mode, the following features differ between the two modules: ? the usart in mspim mode includes (double) buffering of the transmitter. the spi has no buffer. ? the usart in mspim mode receiver includes an additional buffer level. ? the spi w col ( w rite collision) bit is not incl uded in usart in mspim mode. ? the spi double speed mode (spi2x) bit is not included. however, the same effect is achieved by setting ubrrn accordingly. ? interrupt timing is not compatible. ? pin control differs due to the master only operation of the usart in mspim mode. a comparison of the usart in mspim mode and the spi pins is shown in table 116 on page 244 clock generation the clock generation logic generates the bas e clock for the transmitter and receiver. for usart mspim mode of operation only internal clock generation (i.e. master opera- tion) is supported. the data direction re gister for the xckn pin (ddr_xckn) must therefore be set to one (i.e. as output) for the usart in mspim to operate correctly. preferably the ddr_xckn should be set up before the usart in mspim is enabled (i.e. txe n n and rxe n n bit set to one). 237 atmega640/1280/1281/2560/2561 2549k?avr?01/07 the internal clock generation used in mspim mode is identical to the usart synchro- nous master mode. the baud rate or ubrrn setting can therefore be calculated using the same equations, see table 113: n ote: 1. the baud rate is defined to be the transfer rate in bit per second (bps) baud baud rate (in bits per second, bps) f osc system oscillator clock frequency ubrrn contents of the ubrrnh and ubrrnl registers, (0-4095) spi data modes and timing there are four combinations of xckn (sck) phase and polarity with respect to serial data, which are determined by control bits ucphan and ucpoln. the data transfer timing diagrams are shown in figure 89. data bits are shifted out and latched in on opposite edges of the xckn si gnal, ensuring sufficient time for data signals to stabilize. the ucpoln and ucphan functionality is summarized in table 114. n ote that chang- ing the setting of any of these bits will corrupt all ongoing communication for both the receiver and transmitter. table 113. equations for calculating baud rate register setting operating mode equation for calculating baud rate (1) equation for calculating ubrrn value synchronous master mode baud f osc 2 ubrr n 1 + () -------------------------------------- - = ubrr n f osc 2 baud -------------------- 1 ? = table 114. ucpoln and ucphan functionality- ucpoln ucphan spi mode leading edge trailing edge 0 0 0 sample (rising) setup (falling) 0 1 1 setup (rising) sample (falling) 1 0 2 sample (falling) setup (rising) 1 1 3 setup (falling) sample (rising) 238 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 89. ucphan and ucpoln data transfer timing diagrams. frame formats a serial frame for the mspim is defined to be one character of 8 data bits. the usart in mspim mode has two valid frame formats: ? 8-bit data with msb first ? 8-bit data with lsb first a frame starts with the least or most significant data bit. then the next data bits, up to a total of eight, are succeeding, ending with the most or least significant bit accordingly. w hen a complete frame is transmitted, a new frame can directly follow it, or the commu- nication line can be set to an idle (high) state. the udordn bit in ucsrnc sets the frame format used by the usart in mspim mode. the receiver and transmitter use the same setting. n ote that changing the set- ting of any of these bits will corrupt all on going communication for both the receiver and transmitter. 16-bit data transfer can be achieved by writing two data bytes to udrn. a uart trans- mit complete interrupt will th en signal that the 16-bit va lue has been shifted out. usart mspim initialization the usart in mspim mode has to be initialized before any communication can take place. the initialization process normally cons ists of setting the baud rate, setting mas- ter mode of operation (by setting ddr_xckn to one), setting frame format and enabling the transmitter and the receiver. only the transmitter can operate independently. for interrupt driven usart operation, the global interrupt flag should be cleared (and thus interrupts globally disabled) when doing the initialization. n ote: to ensure immediate initialization of th e xckn output the baud-rate register (ubrrn) must be zero at the time the transmitter is enabled. contrary to the normal mode usart operation the ubrrn must then be written to the desired value after the transmitter is enabled, but before the first transmission is started. setting ubrrn to zero before enabling the transmitter is not necessary if the initialization is done immediately after a reset since ubrrn is reset to zero. before doing a re-initialization with changed baud rate, data mode, or frame format, be sure that there is no ongoing transmissions during the period the registers are changed. the txcn flag can be used to check that the transmitter has completed all transfers, and the rxcn flag can be used to check that there are no unread data in the receive buffer. n ote that the txcn flag must be cleared before each transmission (before udrn is written) if it is used for this purpose. the following simple usart initialization code examples show one assembly and one c function that are equal in functionality. the examples assume polling (no interrupts xck data setup (txd) data sample (rxd) xck data setup (txd) data sample (rxd) xck data setup (txd) data sample (rxd) xck data setup (txd) data sample (rxd) ucpol=0 ucpol=1 ucpha=0 ucpha=1 239 atmega640/1280/1281/2560/2561 2549k?avr?01/07 enabled). the baud rate is given as a functi on parameter. for the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers. n ote: 1. see ?about code examples? on page 9. assembly code example (1) usart_init: clr r18 out ubrrnh,r18 out ubrrnl,r18 ; setting the xckn port pin as output, enables master mode. sbi xckn_ddr, xckn ; set mspi mode of operation and spi data mode 0. ldi r18, (1< 241 atmega640/1280/1281/2560/2561 2549k?avr?01/07 n ote: 1. see ?about code examples? on page 9. transmitter and receiver flags and interrupts the rxcn, txcn, and udren flags and corres ponding interrupts in usart in mspim mode are identical in function to the normal usart operation. however, the receiver error status flags (fe, dor, and pe) are not in use and is always read as zero. disabling the transmitter or receiver the disabling of the transmitter or receiver in usart in mspim mode is identical in function to the normal usart operation. assembly code example (1) usart_mspim_transfer: ; wait for empty transmit buffer sbis ucsrna, udren rjmp usart_mspim_transfer ; put data (r16) into buffer, sends the data out udrn,r16 ; wait for data to be received usart_mspim_wait_rxcn: sbis ucsrna, rxcn rjmp usart_mspim_wait_rxcn ; get and return received data from buffer in r16, udrn ret c code example (1) unsigned char usart_receive( void ) { /* wait for empty transmit buffer */ while ( !( ucsrna & (1< 243 atmega640/1280/1281/2560/2561 2549k?avr?01/07 ucsrnb ? usart mspim control and status register n b ? bit 7 - rxcien: rx complete interrupt enable w riting this bit to one enables interrupt on the rxcn flag. a usart receive complete interrupt will be generat ed only if the rxcien bit is wr itten to one, t he global interrupt flag in sreg is written to one an d the rxcn bit in ucsrna is set. ? bit 6 - txcien: tx complete interrupt enable w riting this bit to one enables interrupt on the txcn flag. a usart transmit complete interrupt will be generated only if the txcien bit is written to one, the global interrupt flag in sreg is written to one and the txcn bit in ucsrna is set. ? bit 5 - udrie: usart data re gister empty interrupt enable w riting this bit to one enables interrupt on the udren flag. a data register empty interrupt will be genera ted only if the udrie bit is wr itten to one, the global interrupt flag in sreg is written to one and the udren bit in ucsrna is set. ? bit 4 - rxenn: receiver enable w riting this bit to one enables the usart receiver in mspim mode. the receiver will override normal port operation for the rxdn pin when enabled. disabling the receiver will flush the receive buffer. only enabling the receiver in mspi mode (i.e. setting rxe n n=1 and txe n n=0) has no meaning since it is the transmitter that controls the transfer clock and since only master mode is supported. ? bit 3 - txenn: transmitter enable w riting this bit to one enables the usart transmitter. the trans mitter will override nor- mal port operation for the txdn pin when enabled. the disabling of the transmitter (writing txe n n to zero) will not become effective until ongoing and pending transmis- sions are completed, i.e., when the transmit shift register and transmit buffer register do not contain data to be transmitted. w hen disabled, the tran smitter will no longer override the txdn port. ? bit 2:0 - reserved bits in mspi mode w hen in mspi mode, these bits are reserved for future use. for compatibility with future devices, these bits must be written to zero when ucsrnb is written. bit 7 6543210 rxcien txcien udrie rxenn txenn - - - ucsrnb read/ w rite r/ w r/ w r/ w r/ w r/ w rrr initial value 0 0 0 0 0 1 1 0 244 atmega640/1280/1281/2560/2561 2549k?avr?01/07 ucsrnc ? usart mspim control and status register n c ? bit 7:6 - umseln1:0: usart mode select these bits select the mode of operation of the usart as shown in table 115. see ?ucsrnc ? usart control and status register n c? on page 229 for full description of the normal usart operation. the mspim is enabled when both umseln bits are set to one. the udordn, ucphan, and ucpoln can be set in the same write operation where the mspim is enabled. ? bit 5:3 - reserved bits in mspi mode w hen in mspi mode, these bits are reserved for future use. for compatibility with future devices, these bits must be written to zero when ucsrnc is written. ? bit 2 - udordn: data order w hen set to one the lsb of the data word is transmitted first. w hen set to zero the msb of the data word is transmitted first. refer to the frame formats section page 4 for details. ? bit 1 - ucphan: clock phase the ucphan bit setting determine if data is sampled on the leasing edge (first) or tailing (last) edge of xckn. refer to the spi data modes and timing section page 4 for details. ? bit 0 - ucpoln: clock polarity the ucpoln bit sets the polarity of the xckn clock. the combination of the ucpoln and ucphan bit settings determine the timing of the data transfer. refer to the spi data modes and timing section page 4 for details. ubrrnl and ubrrnh ? usart mspim baud rate registers the function and bit description of the baud rate registers in mspi mode is identical to normal usart operation. see ?ubrrnl an d ubrrnh ? usart baud rate registers? on page 231. bit 7 6 5 4 3 2 1 0 umseln1 umseln0 - - - udordn ucphan ucpoln ucsrnc read/ w rite r/ w r/ w rrr r/ w r/ w r/ w initial value 0 0 0 0 0 1 1 0 table 115. umseln bits settings umseln1 umseln0 mode 0 0 asynchronous usart 0 1 synchronous usart 1 0 (reserved) 1 1 master spi (mspim) table 116. comparison of usart in mspim mode and spi pins. usart_mspim spi comment txdn mosi master out only rxdn miso master in only xckn sck (functionally identical) ( n /a) ss n ot supported by usart in mspim 245 atmega640/1280/1281/2560/2561 2549k?avr?01/07 2-wire serial interface features ? simple yet powerful and flexible communication interface, only two bus lines needed ? both master and slave operation supported ? device can operate as transmitter or receiver ? 7-bit address space allows up to 128 different slave addresses ? multi-master arbitration support ? up to 400 khz data transfer speed ? slew-rate limited output drivers ? noise suppression circuitry rejects spikes on bus lines ? fully programmable slave address with general call support ? address recognition causes wake-up when avr is in sleep mode 2-wire serial interface bus definition the 2-wire serial interface (t w i) is ideally suited for typi cal microcontroller applications. the t w i protocol allows the systems designer to interconnect up to 128 different devices using only two bi-directional bus lines, one for clock (scl) and one for data (sda). the only external hardware needed to implement the bus is a single pull-up resistor for each of the t w i bus lines. all devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the t w i protocol. figure 90. t w i bus interconnection twi terminology the following definitions are frequently encountered in this section. the power reduction t w i bit, prt w i bit in ?prr0 ? power reduction register 0? on page 55 must be written to zero to enable the 2-wire serial interface. device 1 device 2 device 3 device n sda scl ........ r1 r2 v cc table 117. t w i terminology term description master the device that initiates and terminates a transmission. the master also generates the scl clock. slave the device addressed by a master. transmitter the device placing data on the bus. receiver the device reading data from the bus. 246 atmega640/1280/1281/2560/2561 2549k?avr?01/07 electrical interconnection as depicted in figure 90, both bus lines are connected to the positive supply voltage through pull-up resistors. the bus drivers of all t w i-compliant devices are open-drain or open-collector. this implements a wired-a n d function which is essential to the opera- tion of the interface. a low level on a t w i bus line is generated when one or more t w i devices output a zero. a high level is output when all t w i devices trim-state their out- puts, allowing the pull-up resistors to pull the line high. n ote that all avr devices connected to the t w i bus must be powered in order to allow any bus operation. the number of devices that can be connect ed to the bus is only limited by the bus capacitance limit of 400 pf and the 7-bit sl ave address space. a detailed specification of the electrical characteristics of the t w i is given in ?spi timing characteristics? on page 380. two different sets of specifications are presented there, one relevant for bus speeds below 100 khz, and one valid for bus speeds up to 400 khz. data transfer and frame format transferring bits each data bit transferred on the t w i bus is accompanied by a pulse on the clock line. the level of the data line must be stable when the clock line is high. the only exception to this rule is for generating start and stop conditions. figure 91. data validity start and stop conditions the master initiates and terminates a data transmission. the transmission is initiated when the master issues a start condition on the bus, and it is terminated when the master issues a stop condition. between a start and a stop condition, the bus is considered busy, and no other master should tr y to seize control of the bus. a special case occurs when a new start condition is issued between a start and stop con- dition. this is referred to as a repe ated start condition, and is used when the master wishes to initiate a new transfer without relinquishing control of the bus. after a repeated start, the bus is considered busy until the next stop. this is identical to the start behavior, and therefore start is used to describe both start and repeated start for the rema inder of this dat asheet, unless otherwise noted. as depicted below, start and stop conditions are signalled by changing the level of the sda line when the scl line is high. sda scl data stable data stable data change 247 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 92. start, repeated start and stop conditions address packet format all address packets transmitted on the t w i bus are 9 bits long, consisting of 7 address bits, one read/ w rite control bit and an acknowledge bit. if the read/ w rite bit is set, a read operation is to be performed, otherwise a write operation should be per- formed. w hen a slave recognizes that it is be ing addressed, it should acknowledge by pulling sda low in the ninth scl (ack) cycle. if the addressed slave is busy, or for some other reason can not service the master?s request, the sda line should be left high in the ack clock cycle. the master c an then transmit a st op condition, or a repeated start condition to initiate a ne w transmission. an address packet consist- ing of a slave address and a read or a w rite bit is called sla+r or sla+ w , respectively. the msb of the address byte is transmitted fi rst. slave addresses can freely be allo- cated by the designer, but the address 0000 000 is reserved for a general call. w hen a general call is issued, all slaves s hould respond by pulling the sda line low in the ack cycle. a general call is used when a master wishes to transmit the same mes- sage to several slaves in the system. w hen the general call address followed by a w rite bit is transmitted on the bus, all slaves set up to acknowledge the general call will pull the sda line low in the ack cycle. the followi ng data packets will then be received by all the slaves that acknowledged the general call. n ote that transmitting the general call address followed by a read bit is meaningless , as this would cause contention if several slaves started transmitting different data. all addresses of the format 1111 xxx should be reserved for future purposes. figure 93. address packet format sda scl start stop repeated start stop start sda scl start 12 789 addr msb addr lsb r/w ack 248 atmega640/1280/1281/2560/2561 2549k?avr?01/07 data packet format all data packets transmitted on the t w i bus are nine bits long, consisting of one data byte and an acknowledge bit. during a data transfer, the master generates the clock and the start and stop conditions, while the re ceiver is responsible for acknowledging the reception. an acknowledge (ack) is si gnalled by the receiver pulling the sda line low during the ninth scl cycle. if the receiver leaves the sda line high, a n ack is sig- nalled. w hen the receiver has received the last byte, or for some reason cannot receive any more bytes, it should inform the transmitter by sending a n ack after the final byte. the msb of the data byte is transmitted first. figure 94. data packet format combining address and data packets into a transmission a transmission basically consists of a start condition, a sla+r/ w , one or more data packets and a stop condition. an empty me ssage, consisting of a start followed by a stop condition, is illegal. n ote that the w ired-a n ding of the scl line can be used to implement handshaking between the master and the slave. the slave can extend the scl low period by pulling the scl line low. this is useful if the clock speed set up by the master is too fast for the slave, or t he slave needs extra time for processing between the data transmissions. the sl ave extending the scl low period will not affect the scl high period, which is determined by the master. as a consequence, the slave can reduce the t w i data transfer speed by prolonging the scl duty cycle. figure 95 shows a typical data transmission. n ote that several data bytes can be trans- mitted between the sla+r/ w and the stop condition, depending on the software protocol implemented by the application software. figure 95. typical data transmission 12 789 data msb data lsb ack aggregate sda sda from transmitter sda from receiver scl from master sla+r/w data byte stop, repeated start or next data byte 12 789 data byte data msb data lsb ack sda scl start 12 789 addr msb addr lsb r/w ack sla+r/w stop 249 atmega640/1280/1281/2560/2561 2549k?avr?01/07 multi-master bus systems, arbitration and synchronization the t w i protocol allows bus systems with several masters. special concerns have been taken in order to ensure that transmissi ons will proceed as normal, even if two or more masters initiate a transm ission at the same time. two problems arise in multi-mas- ter systems: ? an algorithm must be implemented allowing only one of the masters to complete the transmission. all other masters should cease transmission when they discover that they have lost the selection process. this selection process is called arbitration. w hen a contending master discovers that it has lost the arbitration process, it should immediately switch to slave mode to check whether it is being addressed by the winning master. the fact that multiple masters have started transmission at the same time should not be detectable to the slaves, i.e. the data being transferred on the bus must not be corrupted. ? different masters may use different scl frequencies. a scheme must be devised to synchronize the serial clocks from all masters, in order to let the transmission proceed in a lockstep fashion. this will facilitate the arbitration process. the wired-a n ding of the bus lines is used to solve both these problems. the serial clocks from all masters will be wired-a n ded, yielding a combined clock with a high period equal to the one from the master with the shortest high period. the low period of the combined clock is equal to the low period of the master with the longest low period. n ote that all masters listen to the scl line, effectively starting to count their scl high and low time-out periods when the combined scl line goes high or low, respectively. figure 96. scl synchronization between multiple masters arbitration is carried out by all masters continuously monitoring the sda line after out- putting data. if the value read from the sda line does not match the value the master had output, it has lost the arbitration. n ote that a master can only lose arbitration when it outputs a high sda value while another master outputs a low value. the losing master should immediately go to slave mode, checki ng if it is being addressed by the winning master. the sda line should be left high, but losing masters are allowed to generate a clock signal until the end of the current data or address packet. arbitration will continue until only one master remains, and this may take many bits. if several masters are trying to address the same slave, arbitrat ion will continue into the data packet. ta low ta high scl from master a scl from master b scl bus line tb low tb high masters start counting low period masters start counting high period 250 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 97. arbitration between two masters n ote that arbitration is not allowed between: ? a repeated start cond ition and a data bit. ? a stop condition and a data bit. ? a repeated start and a stop condition. it is the user software?s re sponsibility to ensure that th ese illegal arbitration conditions never occur. this implies that in multi-master systems, all data transfers must use the same composition of sla+r/ w and data packets. in other words: all transmissions must contain the same number of data packets, otherwise the result of the arbitration is undefined. sda from master a sda from master b sda line synchronized scl line start master a loses arbitration, sda a sda 251 atmega640/1280/1281/2560/2561 2549k?avr?01/07 overview of the twi module the t w i module is comprised of several submodules, as shown in figure 98. all regis- ters drawn in a thick line are accessible through the avr data bus. figure 98. overview of the t w i module scl and sda pins these pins interface the avr t w i with the rest of the mcu system. the output drivers contain a slew-rate limiter in order to conform to the t w i specification. the input stages contain a spike suppression unit removing spikes shorter than 50 ns. n ote that the inter- nal pull-ups in the avr pads can be enabled by setting the port bits corresponding to the scl and sda pins, as explained in the i/o port section. the internal pull-ups can in some systems eliminate the need for external ones. bit rate generator unit this unit controls the period of scl when operating in a master mode. the scl period is controlled by settings in the t w i bit rate register (t w br) and the prescaler bits in the t w i status register (t w sr). slave operation does not depend on bit rate or pres- caler settings, but the cpu clock frequency in the slave must be at least 16 times higher than the scl frequency. n ote that slaves may prolong the scl low period, thereby reducing the average t w i bus clock period. the scl frequency is generated according to the following equation: twi unit address register (twar) address match unit address comparator control unit control register (twcr) status register (twsr) state machine and status control scl slew-rate control spike filter sda slew-rate control spike filter bit rate generator bit rate register (twbr) prescaler bus interface unit start / stop control arbitration detection ack spike suppression address/data shift register (twdr) 252 atmega640/1280/1281/2560/2561 2549k?avr?01/07 ?t w br = value of the t w i bit rate register. ?t w ps = value of the prescaler bits in the t w i status register. n ote: pull-up resistor values should be selected according to the scl frequency and the capacitive bus line load. see ?2-wire serial interface characteristics? on page 379 for value of pull-up resistor. bus interface unit this unit contains the data and address shift register (t w dr), a start/stop con- troller and arbitration detection hardware. the t w dr contains the address or data bytes to be transmitted, or the address or data bytes received. in addition to the 8-bit t w dr, the bus interface unit also co ntains a register containing the ( n )ack bit to be transmitted or received. this ( n )ack register is not directly accessible by the applica- tion software. however, when receiving, it can be set or cleared by manipulating the t w i control register (t w cr). w hen in transmitter mode, the value of the received ( n )ack bit can be determined by the value in the t w sr. the start/stop controller is responsi ble for generation and detection of start, repeated start, and stop conditions. the start/stop controller is able to detect start and stop conditions even when the avr mcu is in one of the sleep modes, enabling the mcu to wake up if addressed by a master. if the t w i has initiated a transmission as master, the arbitration detection hardware continuously monitors the transmission trying to determine if arbitration is in process. if the t w i has lost an arbitration, the control unit is informed. correct action can then be taken and appropriate status codes generated. address match unit the address match unit checks if received address bytes match the seven-bit address in the t w i address register (t w ar). if the t w i general call recognition enable (t w gce) bit in the t w ar is written to one, all inco ming address bits will also be com- pared against the general call address. upon an address match, the control unit is informed, allowing correct action to be taken. the t w i may or may not acknowledge its address, depending on settings in the t w cr. the address match unit is able to com- pare addresses even when the avr mcu is in sleep mode, enabling the mcu to wake up if addressed by a master. if another interrupt (e.g., i n t0) occurs during t w i power- down address match and wakes up the cpu, the t w i aborts operation and return to it?s idle state. if this cause any problems, ensure that t w i address match is the only enabled interrupt when entering power-down. control unit the control unit monitors the t w i bus and generates responses corresponding to set- tings in the t w i control register (t w cr). w hen an event requiring the attention of the application occurs on the t w i bus, the t w i interrupt flag (t w i n t) is asserted. in the next clock cycle, the t w i status register (t w sr) is updated with a status code identify- ing the event. the t w sr only contains relevant status information when the t w i interrupt flag is asserted. at all other times, the t w sr contains a special status code indicating that no relevant status information is available. as long as the t w i n t flag is set, the scl line is held low. this allows the application software to complete its tasks before allowing the t w i transmission to continue. the t w i n t flag is set in th e following situations: ? after the t w i has transmitted a start/repeated start condition. ? after the t w i has transmitted sla+r/ w . scl frequency cpu clock frequency 16 2(t w br) 4 twps ? + ----------------------------------------------------------- = 253 atmega640/1280/1281/2560/2561 2549k?avr?01/07 ? after the t w i has transmitted an address byte. ? after the t w i has lost arbitration. ? after the t w i has been addressed by own slave address or general call. ? after the t w i has received a data byte. ? after a stop or repeated start has been received while still addressed as a slave. ? w hen a bus error has occurr ed due to an illegal start or stop condition. using the twi the avr t w i is byte-oriented and interrupt based. interrupts are issued after all bus events, like reception of a byte or transmis sion of a start condition. because the t w i is interrupt-based, the application software is free to carry on other operations during a t w i byte transfer. n ote that the t w i interrupt enable (t w ie) bit in t w cr together with the global interrupt enable bit in sreg a llow the application to decide whether or not assertion of the t w i n t flag should generate an interrupt request. if the t w ie bit is cleared, the application must poll the t w i n t flag in order to detect actions on the t w i bus. w hen the t w i n t flag is asserted, the t w i has finished an operation and awaits appli- cation response. in this case, the t w i status register (t w sr) contains a value indicating the current state of the t w i bus. the application software can then decide how the t w i should behave in the next t w i bus cycle by manipulating the t w cr and t w dr registers. figure 99 is a simple example of how the application can interface to the t w i hardware. in this example, a master wishes to transmit a single data byte to a slave. this descrip- tion is quite abstract, a more detailed explanation follows later in this section. a simple code example implementing the de sired behavior is also presented. figure 99. interfacing the application to the t w i in a typical transmission 1. the first step in a t w i transmission is to transmit a start condition. this is done by writing a specific value into t w cr, instructing the t w i hardware to transmit a start condition. w hich value to write is described later on. however, it is important that the t w i n t bit is set in the value written. w riting a one to t w i n t clears the flag. the t w i will not start any operation as long as the start sla+w a data a stop 1. application writes to twcr to initiate transmission of start 2. twint set. status code indicates start condition sent 4. twint set. status code indicates sla+w sent, ack received 6. twint set. status code indicates data sent, ack received 3. check twsr to see if start was sent. application loads sla+w into twdr, and loads appropriate control signals into twcr, makin sure that twint is written to one, and twsta is written to zero. 5. check twsr to see if sla+w was sent and ack received. application loads data into twdr, and loads appropriate control signals into twcr, making sure that twint is written to one 7. check twsr to see if data was sent and ack received. application loads appropriate control signals to send stop into twcr, making sure that twint is written to one twi bus indicates twint set application action twi hardware action 254 atmega640/1280/1281/2560/2561 2549k?avr?01/07 t w i n t bit in t w cr is set. immediately after the application has cleared t w i n t, the t w i will initiate transmission of the start condition. 2. w hen the start condition has been transmitted, the t w i n t flag in t w cr is set, and t w sr is updated with a status code indicating that the start condition has successfully been sent. 3. the application software should now examine the value of t w sr, to make sure that the start condition was successfully transmitted. if t w sr indicates other- wise, the application softwar e might take some special action, like calling an error routine. assuming that the status code is as expected, the application must load sla+ w into t w dr. remember that t w dr is used both for address and data. after t w dr has been loaded with the desired sla+ w , a specific value must be written to t w cr, instructing the t w i hardware to transmit the sla+ w present in t w dr. w hich value to write is described later on. however, it is important that the t w i n t bit is set in the value written. w riting a one to t w i n t clears the flag. the t w i will not start any operation as long as the t w i n t bit in t w cr is set. immediately after the application has cleared t w i n t, the t w i will initiate transmission of the address packet. 4. w hen the address packet has been transmitted, the t w i n t flag in t w cr is set, and t w sr is updated with a status code indicating that the address packet has successfully been sent. the status co de will also reflect whether a slave acknowledged the packet or not. 5. the application software should now examine the value of t w sr, to make sure that the address packet was successfully transmitted, and that the value of the ack bit was as expected. if t w sr indicates otherwise, the application software might take some special action, like callin g an error routine. assuming that the status code is as expected, the application must load a data packet into t w dr. subsequently, a specific value must be written to t w cr, instructing the t w i hardware to transmit the data packet present in t w dr. w hich value to write is described later on. however, it is important that the t w i n t bit is set in the value written. w riting a one to t w i n t clears the flag. the t w i will not start any opera- tion as long as the t w i n t bit in t w cr is set. immediately after the application has cleared t w i n t, t h e t w i will initiate transmissi on of the data packet. 6. w hen the data packet has been transmitted, the t w i n t flag in t w cr is set, and t w sr is updated with a status code indicating that the data packet has suc- cessfully been sent. the status co de will also reflect whether a slave acknowledged the packet or not. 7. the application software should now examine the value of t w sr, to make sure that the data packet was successfully transmitted, and that the value of the ack bit was as expected. if t w sr indicates otherwise, the application software might take some special action, like calling an er ror routine. assuming that the status code is as expected, the application must write a specific value to t w cr, instructing the t w i hardware to transmit a stop condition. w hich value to write is described later on. however, it is important that the t w i n t bit is set in the value written. w riting a one to t w i n t clears the flag. the t w i will not start any operation as long as the t w i n t bit in t w cr is set. immediately after the appli- cation has cleared t w i n t, t h e t w i will initiate transmission of the stop condition. n ote that t w i n t is n ot set after a stop condition has been sent. even though this example is simple, it sh ows the principles involved in all t w i transmis- sions. these can be summarized as follows: ? w hen the t w i has finished an operation and expects application response, the t w i n t flag is set. the scl line is pulled low until t w i n t is cleared. 255 atmega640/1280/1281/2560/2561 2549k?avr?01/07 ? w hen the t w i n t flag is set, the user must update all t w i registers with the value relevant for the next t w i bus cycle. as an example, t w dr must be loaded with the value to be transmitted in the next bus cycle. ? after all t w i register updates and other pending application software tasks have been completed, t w cr is written. w hen writing t w cr, the t w i n t bit should be set. w riting a one to t w i n t clears the flag. the t w i will then commence executing whatever operation was specified by the t w cr setting. in the following an assembly and c impl ementation of the example is given. n ote that the code below assumes that several definitions have been made, for example by using include-files. assembly code example c example comments 1 ldi r16, (1< 257 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 100. data transfer in master transmitter mode a start condition is sent by writing the following value to t w cr: t w e n must be set to enable the 2-wire serial interface, t w sta must be written to one to transmit a start condition and t w i n t must be written to one to clear the t w i n t flag. the t w i will then test the 2-wire serial bu s and generate a st art condition as soon as the bus becomes free. after a start condition has been transmitted, the t w i n t flag is set by hardware, and the status code in t w sr will be 0x08 (see table 118). in order to enter mt mode, sla+ w must be transmitted. this is done by writing sla+ w to t w dr. thereafter the t w i n t bit should be cleared (by writing it to one) to continue the transfer. this is accomplished by writing the following value to t w cr: w hen sla+ w have been transmitted and an acknowledgement bit has been received, t w i n t is set again and a number of status codes in t w sr are possible. possible sta- tus codes in master mode are 0x18, 0x20, or 0x38. the appropriate action to be taken for each of these status codes is detailed in table 118. w hen sla+ w has been successfully transmitted, a data packet should be transmitted. this is done by writing the data byte to t w dr. t w dr must only be written when t w i n t is high. if not, the access will be discarded, and the w rite collision bit (t ww c) will be set in the t w cr register. after updating t w dr, the t w i n t bit should be cleared (by writing it to one) to continue the transfer. this is acco mplished by writing the following value to t w cr: this scheme is repeated until the last byte has been sent and the transfer is ended by generating a stop condition or a repeated start condition. a stop condition is gen- erated by writing th e following value to t w cr: a repeated start condition is generated by writing the following value to t w cr: twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x00 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x00 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x01 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x device 1 master transmitter device 2 slave receiver device 3 device n sda scl ........ r1 r2 v cc 258 atmega640/1280/1281/2560/2561 2549k?avr?01/07 after a repeated start condition (state 0x10) the 2-wire serial interface can access the same slave again, or a new slave without transmitting a stop condition. repeated start enables the master to switch between slaves, master transmitter mode and master receiver mode without losing control of the bus. table 118. status codes for master transmitter mode status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hard- ware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0x08 a start condition has been transmitted load sla+w 0 0 1 x sla+w will be transmitted; ack or not ack will be received 0x10 a repeated start condition has been transmitted load sla+w or load sla+r 0 0 0 0 1 1 x x sla+w will be transmitted; ack or not ack will be received sla+r will be transmitted; logic will switch to master receiver mode 0x18 sla+w has been transmitted; ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x20 sla+w has been transmitted; not ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x28 data byte has been transmitted; ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x30 data byte has been transmitted; not ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x38 arbitration lost in sla+w or data bytes no twdr action or no twdr action 0 1 0 0 1 1 x x 2-wire serial bus will be released and not addressed slave mode entered a start condition will be transmitted when the bus be- comes free 259 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 101. formats and states in the master transmitter mode master receiver mode in the master receiver mode, a number of data bytes are received from a slave trans- mitter (slave see figure 102). in order to enter a master mode, a start condition must be transmitted. the format of the following address packet determines whether master transmitter or master receiver mode is to be entered. if sla+ w is transmitted, mt mode is entered, if sla+r is transmitted, mr mode is entered. all the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. s sla w a data a p $08 $18 $28 r sla w $10 ap $20 p $30 a or a $38 a other master continues a or a $38 other master continues r a $68 other master continues $78 $b0 to corresponding states in slave mode mt mr successfull transmission to a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address not acknowledge received after a data byte arbitration lost in slave address or data byte arbitration lost and addressed as slave data a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the prescaler bits are zero or masked to zero s 260 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 102. data transfer in ma ster receiver mode a start condition is sent by writing the following value to t w cr: t w e n must be written to one to enable the 2-wire serial interface, t w sta must be written to one to transmit a start condition and t w i n t must be set to clear the t w i n t flag. the t w i will then test the 2-wire serial bu s and generate a st art condition as soon as the bus becomes free. after a start condition has been transmitted, the t w i n t flag is set by hardware, and the status code in t w sr will be 0x08 (see table 118). in order to enter mr mode, sla+r must be transmitted. this is done by writing sla+r to t w dr. thereafter the t w i n t bit should be cleared (by writing it to one) to continue the transfer. this is accomplished by writing the following value to t w cr: w hen sla+r have been transmitted and an acknowledgement bit has been received, t w i n t is set again and a number of status codes in t w sr are possible. possible sta- tus codes in master mode are 0x38, 0x40, or 0x48. the appropriate action to be taken for each of these status codes is detailed in table 119. received data can be read from the t w dr register when the t w i n t flag is set high by hardware. this scheme is repeated until the last byte has been received. after the last byte has been received, the mr should inform the st by sending a n ack after the last received data byte. the transfer is ended by generating a stop c ondition or a repeated start condition. a stop condition is generated by writing the following value to t w cr: a repeated start condition is generated by writing the following value to t w cr: after a repeated start condition (state 0x10) the 2-wire serial interface can access the same slave again, or a new slave without transmitting a stop condition. repeated twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x00 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x01 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x device 1 master receiver device 2 slave transmitter device 3 device n sda scl ........ r1 r2 v cc 261 atmega640/1280/1281/2560/2561 2549k?avr?01/07 start enables the master to switch between slaves, master transmitter mode and master receiver mode without losing control over the bus. table 119. status codes for master receiver mode status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hard- ware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0x08 a start condition has been transmitted load sla+r 0 0 1 x sla+r will be transmitted ack or not ack will be received 0x10 a repeated start condition has been transmitted load sla+r or load sla+w 0 0 0 0 1 1 x x sla+r will be transmitted ack or not ack will be received sla+w will be transmitted logic will switch to master transmitter mode 0x38 arbitration lost in sla+r or not ack bit no twdr action or no twdr action 0 1 0 0 1 1 x x 2-wire serial bus will be released and not addressed slave mode will be entered a start condition will be transmitted when the bus becomes free 0x40 sla+r has been transmitted; ack has been received no twdr action or no twdr action 0 0 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x48 sla+r has been transmitted; not ack has been received no twdr action or no twdr action or no twdr action 1 0 1 0 1 1 1 1 1 x x x repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x50 data byte has been received; ack has been returned read data byte or read data byte 0 0 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x58 data byte has been received; not ack has been returned read data byte or read data byte or read data byte 1 0 1 0 1 1 1 1 1 x x x repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 262 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 103. formats and states in the master receiver mode slave receiver mode in the slave receiver mode, a number of data bytes are received from a master trans- mitter (see figure 104). all the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. figure 104. data transfer in slave receiver mode to initiate the slave receiver mode, t w ar and t w cr must be initialized as follows: s sla r a data a $08 $40 $50 sla r $10 ap $48 a or a $38 other master continues $38 other master continues w a $68 other master continues $78 $b0 to corresponding states in slave mode mr mt successfull reception from a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address arbitration lost in slave address or data byte arbitration lost and addressed as slave data a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the prescaler bits are zero or masked to zero p data a $58 a r s twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce value device?s own slave address device 3 device n sda scl ........ r1 r2 v cc device 2 master transmitter device 1 slave receiver 263 atmega640/1280/1281/2560/2561 2549k?avr?01/07 the upper 7 bits are the address to which the 2-wire serial interfac e will respond when addressed by a master. if the lsb is set, the t w i will respond to the general call address (0x00), otherwise it will ignore the general call address. t w e n must be written to one to enable the t w i. the t w ea bit must be written to one to enable the acknowledgement of the device?s own slave address or the general call address. t w sta and t w sto must be written to zero. w hen t w ar and t w cr have been initialized, the t w i waits until it is addressed by its own slave address (or the general call address if enabled) followed by the data direction bit. if the direction bit is ?0? (write), the t w i will operate in sr mode, otherwise st mode is entered. after its own slave address an d the write bit have been received, the t w i n t flag is set and a valid status code can be read from t w sr. the status code is used to determine the appropriate software action. the appropriate action to be taken for each status code is detailed in table 120. the slave receiver mode may also be entered if arbitration is lost while the t w i is in the master mode (see states 0x68 and 0x78). if the t w ea bit is reset during a transfer, the t w i will return a ? n ot acknowledge? (?1?) to sda after the next received data byte. this can be used to indicate that the slave is not able to receive any more bytes. w hile t w ea is zero, the t w i does not acknowledge its own slave address. however, the 2-wire se rial bus is still monitored and address rec- ognition may resume at any time by setting t w ea. this implie s that the t w ea bit may be used to temporarily isolate the t w i from the 2-wire serial bus. in all sleep modes other than idle mode, the clock system to the t w i is turned off. if the t w ea bit is set, the interface can still acknowledge its own sl ave address or the general call address by using the 2-wire serial bus clock as a clock source. the part will then wake up from sleep and the t w i will hold the scl clock low during the wake up and until the t w i n t flag is cleared (by writing it to one). further data re ception will be car- ried out as normal, with the avr clocks running as normal. observe that if the avr is set up with a long start-up time, the scl line may be held low for a long time, blocking other data transmissions. n ote that the 2-wire serial interface data register ? t w dr does not reflect the last byte present on the bus when waking up from these sleep modes. twcr twint twea twsta twsto twwc twen ? twie value 0 100 01 0 x 264 atmega640/1280/1281/2560/2561 2549k?avr?01/07 table 120. status codes for slave receiver mode status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0x60 own sla+w has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x68 arbitration lost in sla+r/w as master; own sla+w has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x70 general call address has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x78 arbitration lost in sla+r/w as master; general call address has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x80 previously addressed with own sla+w; data has been received; ack has been returned read data byte or read data byte x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x88 previously addressed with own sla+w; data has been received; not ack has been returned read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 0x90 previously addressed with general call; data has been re- ceived; ack has been returned read data byte or read data byte x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x98 previously addressed with general call; data has been received; not ack has been returned read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 0xa0 a stop condition or repeated start condition has been received while still addressed as slave no action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 265 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 105. formats and states in the slave receiver mode s sla w a data a $60 $80 $88 a $68 reception of the own slave address and one or more data bytes. all are acknowledged last data byte received is not acknowledged arbitration lost as master and addressed as slave reception of the general call address and one or more data bytes last data byte received is not acknowledged n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the prescaler bits are zero or masked to zero p or s data a $80 $a0 p or s a adataa $70 $90 $98 a $78 p or s data a $90 $a0 p or s a general call arbitration lost as master and addressed as slave by general call data a 266 atmega640/1280/1281/2560/2561 2549k?avr?01/07 slave transmitter mode in the slave transmitter mode, a number of data bytes are transmitted to a master receiver (see figure 106). all the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. figure 106. data transfer in slave transmitter mode to initiate the slav e transmitter mode, t w ar and t w cr must be initialized as follows: the upper seven bits are th e address to which the 2-wire serial interface will respond when addressed by a master. if the lsb is set, the t w i will respond to the general call address (0x00), otherwise it will ignore the general call address. t w e n must be written to one to enable the t w i. the t w ea bit must be written to one to enable the acknowledgement of the device?s own slave address or the general call address. t w sta and t w sto must be written to zero. w hen t w ar and t w cr have been initialized, the t w i waits until it is addressed by its own slave address (or the general call address if enabled) followed by the data direction bit. if the direction bit is ?1? (read), the t w i will operate in st mo de, otherwise sr mode is entered. after its own slave address an d the write bit have been received, the t w i n t flag is set and a valid status code can be read from t w sr. the status code is used to determine the appropriate software action. the appropriate action to be taken for each status code is detailed in table 121. the slave transmitter mode may also be entered if arbitration is lost while the t w i is in the master mode (see state 0xb0). if the t w ea bit is written to zero during a transfer, the t w i will transmit the last byte of the transfer. state 0xc0 or state 0xc8 will be entered, depending on wh ether the master receiver transmits a n ack or ack after the final byte. the t w i is switched to the not addressed slave mode, and will ignore the master if it continues the transfer. thus the master receiver receives all ?1? as serial data. state 0xc8 is entered if the master demands additional data bytes (by transmitting ack), even though the slave has trans- mitted the last byte (t w ea zero and expecting n ack from the master). w hile t w ea is zero, the t w i does not respond to its own slave address. however, the 2-wire serial bus is still monitored and address recognition may resume at any time by setting t w ea. this implies that the t w ea bit may be used to temporarily isolate the t w i from the 2-wire serial bus. twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce value device?s own slave address twcr twint twea twsta twsto twwc twen ? twie value 0 100 01 0 x device 3 device n sda scl ........ r1 r2 v cc device 2 master receiver device 1 slave transmitter 267 atmega640/1280/1281/2560/2561 2549k?avr?01/07 in all sleep modes other than idle mode, the clock system to the t w i is turned off. if the t w ea bit is set, the interface can still acknowledge its own sl ave address or the general call address by using the 2-wire serial bus clock as a clock source. the part will then wake up from sleep and the t w i will hold the scl clock will low during the wake up and until the t w i n t flag is cleared (by writing it to one). further data transmission will be carried out as normal, with the avr clocks running as normal. observe that if the avr is set up with a long start-up time, the scl line may be held low for a long time, blocking other data transmissions. n ote that the 2-wire serial interface data register ? t w dr does not reflect the last byte present on the bus when waking up from these sleep modes. table 121. status codes for slave transmitter mode status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0xa8 own sla+r has been received; ack has been returned load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be re- ceived 0xb0 arbitration lost in sla+r/w as master; own sla+r has been received; ack has been returned load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be re- ceived 0xb8 data byte in twdr has been transmitted; ack has been received load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be re- ceived 0xc0 data byte in twdr has been transmitted; not ack has been received no twdr action or no twdr action or no twdr action or no twdr action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 0xc8 last data byte in twdr has been transmitted (twea = ?0?); ack has been received no twdr action or no twdr action or no twdr action or no twdr action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 268 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 107. formats and states in the slave transmitter mode miscellaneous states there are two status codes that do not correspond to a defined t w i state, see table 122. status 0xf8 indicates that no relevant information is available because the t w i n t flag is not set. this occurs between other states, and when the t w i is not involved in a serial transfer. status 0x00 indicates that a bus error has occurred during a 2-wire serial bus transfer. a bus error occurs when a start or stop co ndition occurs at an illegal position in the format frame. examples of such illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. w hen a bus error occurs, t w i n t is set. to recover from a bus error, the t w sto flag must set and t w i n t must be cleared by writing a logic one to it. this causes the t w i to enter the not addressed slave mode and to clear the t w sto flag (no other bits in t w cr are affected). the sda and scl lines are released, and no stop condition is transmitted. s sla r a data a $a8 $b8 a $b0 reception of the own slave address and one or more data bytes last data byte transmitted. switched to not addressed slave (twea = '0') arbitration lost as master and addressed as slave n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the prescaler bits are zero or masked to zero p or s data $c0 data a a $c8 p or s all 1's a table 122. miscellaneous states status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hard- ware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0xf8 no relevant state information available; twint = ?0? no twdr action no twcr action wait or proceed current transfer 0x00 bus error due to an illegal start or stop condition no twdr action 0 1 1 x only the internal hardware is affected, no stop condi- tion is sent on the bus. in all cases, the bus is released and twsto is cleared. 269 atmega640/1280/1281/2560/2561 2549k?avr?01/07 combining several twi modes in some cases, several t w i modes must be combined in or der to complete the desired action. consider for example reading data from a serial eeprom. typically, such a transfer involves the following steps: 1. the transfer must be initiated. 2. the eeprom must be instructed what location should be read. 3. the reading must be performed. 4. the transfer must be finished. n ote that data is transmitted both from master to slave and vice versa. the master must instruct the slave what location it wants to read, requiring the use of the mt mode. sub- sequently, data must be read from the slave, implying the use of the mr mode. thus, the transfer direction must be changed. the master must keep control of the bus during all these steps, and the steps should be carried out as an atomical operation. if this prin- ciple is violated in a multimaster system, another master can alter the data pointer in the eeprom between steps 2 and 3, and the master will read the wrong data location. such a change in transfer direction is accomplished by transmitting a repeated start between the transmission of the address byte and reception of the data. after a repeated start, the master keeps ownership of the bus. the following figure shows the flow in this transfer. figure 108. combining several t w i modes to access a serial eeprom multi-master systems and arbitration if multiple masters are connected to the sa me bus, transmissions may be initiated simul- taneously by one or more of them. the t w i standard ensures that such situations are handled in such a way that one of the master s will be allowed to pr oceed with the trans- fer, and that no data will be lost in the process. an example of an arbitration situation is depicted below, where two masters are trying to transmit data to a slave receiver. figure 109. an arbitration example several different scenarios may arise during arbitration, as described below: master transmitter master receiver s = start rs = repeated start p = stop transmitted from master to slave transmitted from slave to master s sla+w a address a rs sla+r a data a p device 1 master transmitter device 2 master transmitter device 3 slave receiver device n sda scl ........ r1 r2 v cc 270 atmega640/1280/1281/2560/2561 2549k?avr?01/07 ? two or more masters are performing identical communication with the same slave. in this case, neither the slave nor an y of the masters will know about the bus contention. ? two or more masters are accessing the same slave with different data or direction bit. in this case, arbitration will occur, either in the read/ w rite bit or in the data bits. the masters trying to output a one on sda while another master outputs a zero will lose the arbitration. losing masters will switch to not addre ssed slave mode or wait until the bus is free and transmit a new start condition, depending on application software action. ? two or more masters are accessing differ ent slaves. in this case, arbitration will occur in the sla bits. masters trying to output a one on sda while another master outputs a zero will lose the arbitration. masters losing ar bitration in sla will switch to slave mode to check if they are being addressed by the winning master. if addressed, they will switch to sr or st mode, depending on the value of the read/ w rite bit. if they are no t being addressed, they will switch to not addressed slave mode or wait until the bus is free and transmit a new start condition, depending on application software action. this is summarized in figure 110. possible status values are given in circles. figure 110. possible status codes caused by arbitration own address / general call received arbitration lost in sla twi bus will be released and not addressed slave mode will be entered a start condition will be transmitted when the bus becomes free no arbitration lost in data direction ye s write data byte will be received and not ack will be returned data byte will be received and ack will be returned last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be received read b0 68/78 38 sla start data stop 271 atmega640/1280/1281/2560/2561 2549k?avr?01/07 register description twbr ? twi bit rate register ? bits 7:0 ? twi bit rate register t w br selects the division factor for the bit rate generator. the bit rate generator is a frequency divider which generates the scl clock frequency in the master modes. see ?bit rate generator unit? on page 251 for calculating bit rates. twcr ? twi control register the t w cr is used to control the operation of the t w i. it is used to enable the t w i, to initiate a master access by applying a start condition to the bus, to generate a receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the t w dr. it also indicates a write collision if data is attempted written to t w dr while the register is inaccessible. ? bit 7 ? twint: twi interrupt flag this bit is set by hardware when the t w i has finished its current job and expects appli- cation software response. if the i-bit in sreg and t w ie in t w cr are set, the mcu will jump to the t w i interrupt vector. w hile the t w i n t flag is set, the scl low period is stretched. the t w i n t flag must be cleared by software by writing a logic one to it. n ote that this flag is not automatically cleared by hardware when executing the interrupt rou- tine. also note that clearing this flag starts the operation of the t w i, so all accesses to the t w i address register (t w ar), t w i status register (t w sr), and t w i data regis- ter (t w dr) must be complete before clearing this flag. ? bit 6 ? twea: twi enable acknowledge bit the t w ea bit controls the generation of the acknowledge pulse. if the t w ea bit is writ- ten to one, the ack pulse is generated on the t w i bus if the following conditions are met: 1. the device?s own slave address has been received. 2. a general call has been received, while the t w gce bit in the t w ar is set. 3. a data byte has been received in master receiver or slave receiver mode. by writing the t w ea bit to zero, the device can be virtually disconnected from the 2-wire serial bus temporarily. address recognition can then be resumed by writing the t w ea bit to one again. ? bit 5 ? twsta: twi start condition bit the application writes the t w sta bit to one when it desires to become a master on the 2-wire serial bus. the t w i hardware checks if the bus is available, and generates a start condition on the bus if it is free. however, if the bus is not free, the t w i waits bit 76543210 (0xb8) twbr7 twbr6 twbr5 twbr4 twbr3 twbr2 twbr1 twbr0 twbr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 (0xbc) twint twea twsta twsto twwc twen ? twie twcr read/write r/w r/w r/w r/w r r/w r r/w initial value00000000 272 atmega640/1280/1281/2560/2561 2549k?avr?01/07 until a stop condition is detected, and then generates a new start condition to claim the bus master status. t w sta must be cleared by software when the start condition has been transmitted. ? bit 4 ? twsto: twi stop condition bit w riting the t w sto bit to one in master mode will g enerate a stop condition on the 2- wire serial bus. w hen the stop condition is executed on the bus, the t w sto bit is cleared automatically. in slave mode, setting the t w sto bit can be used to recover from an error condition. this will not generate a stop condition, but the t w i returns to a well-defined unaddressed slave mode and releases the scl and sda lines to a high impedance state. ? bit 3 ? twwc: twi write collision flag the t ww c bit is set when attempting to write to the t w i data register ? t w dr when t w i n t is low. this flag is cleared by writing the t w dr register when t w i n t is high. ? bit 2 ? twen: twi enable bit the t w e n bit enables t w i operation and activates the t w i interface. w hen t w e n is written to one, the t w i takes control over the i/o pins connected to the scl and sda pins, enabling the slew-rate limiters and spike filters. if this bit is written to zero, the t w i is switched off and all t w i transmissions are terminated, regardless of any ongoing operation. ? bit 1 ? res: reserved bit this bit is a reserved bit an d will always read as zero. ? bit 0 ? twie: twi interrupt enable w hen this bit is written to one, and the i-bit in sreg is set, the t w i interrupt request will be activated for as long as the t w i n t flag is high. twsr ? twi status register ? bits 7:3 ? tws: twi status these 5 bits reflect the status of the t w i logic and the 2-wire serial bus. the different status codes are described later in this section. n ote that the value read from t w sr contains both the 5-bit status value and the 2-bit prescaler value. the application designer should mask the prescaler bits to zero when checking the status bits. this makes status checking independent of prescaler setting. this approach is used in this datasheet, unless otherwise noted. ? bit 2 ? res: reserved bit this bit is reserved and will always read as zero. bit 76543210 (0xb9) tws7 tws6 tws5 tws4 tws3 ? twps1 twps0 twsr read/write r r r r r r r/w r/w initial value11111000 273 atmega640/1280/1281/2560/2561 2549k?avr?01/07 ? bits 1:0 ? twps: twi prescaler bits these bits can be read and written, and control the bit rate prescaler. to calculate bit rates, see ?bit rate generator unit? on page 251. the value of t w ps1:0 is used in the equation. twdr ? twi data register in transmit mode, t w dr contains the next byte to be transmitted. in receive mode, the t w dr contains the last byte receiv ed. it is writab le while the t w i is not in the process of shifting a byte. this occurs when the t w i interrupt flag (t w i n t) is set by hardware. n ote that the data register cannot be initialized by the user before the first interrupt occurs. the data in t w dr remains stable as long as t w i n t is set. w hile data is shifted out, data on the bus is simultaneously shifted in. t w dr always contains the last byte present on the bus, except after a wake up from a sleep mode by the t w i interrupt. in this case, the contents of t w dr is undefined. in the case of a lost bus arbitration, no data is lost in the transition from master to slave. handling of the ack bit is controlled automatically by the t w i logic, the cpu cannot access the ack bit directly. ? bits 7:0 ? twd: twi data register these eight bits constitute th e next data byte to be transmitted, or the latest data byte received on the 2-wire serial bus. twar ? twi (slave) address register the t w ar should be loaded with the 7-bit slave address (in the seven most significant bits of t w ar) to which the t w i will respond when programm ed as a slave transmitter or receiver, and not needed in the master modes. in multimaster systems, t w ar must be set in masters which can be addressed as slaves by other masters. the lsb of t w ar is used to enable recognition of the general call address (0x00). there is an associated address comparator that looks for the slave address (or general call address if enabled) in the received serial address. if a match is found, an interrupt request is generated. ? bits 7:1 ? twa: twi (slave) address register these seven bits constitute the slave address of the t w i unit. table 123. t w i bit rate prescaler twps1 twps0 prescaler value 001 014 1016 1164 bit 76543210 (0xbb) twd7 twd6 twd5 twd4 twd3 twd2 twd1 twd0 twdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value11111111 bit 76543210 (0xba) twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce twar read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value11111110 274 atmega640/1280/1281/2560/2561 2549k?avr?01/07 ? bit 0 ? twgce: twi general call recognition enable bit if set, this bit enables the recognition of a general call given over the 2-wire serial bus. twamr ? twi (slave) address mask register ? bits 7:1 ? twam: twi address mask the t w amr can be loaded with a 7-bit slave address mask. each of the bits in t w amr can mask (disable) the corresponding address bit in the t w i address register (t w ar). if the mask bit is set to one then the address match logic ignores the compare between the incoming address bit and the corresponding bit in t w ar. figure 111 shows the address match logic in detail. figure 111. t w i address match logic, block diagram ? bit 0 ? res: reserved bit this bit is reserved and will always read as zero. bit 76543210 (0xbd) twam[6:0] ? twamr read/write r/w r/w r/w r/w r/w r/w r/w r initial value00000000 address match address bit comparator 0 address bit comparator 6..1 twar0 twamr0 address bit 0 275 atmega640/1280/1281/2560/2561 2549k?avr?01/07 ac ? analog comparator the analog comparator compares the input values on the positive pin ai n 0 and nega- tive pin ai n 1. w hen the voltage on the positive pin ai n 0 is higher than the voltage on the negative pin ai n 1, the analog comparator output, aco, is set. the comparator?s output can be set to trigger the timer/counter1 input capture function. in addition, the comparator can trigger a separate interrupt, exclusive to the analog comparator. the user can select interrupt triggering on comparator output rise, fall or toggle. a block dia- gram of the comparator and its surrounding logic is shown in figure 112 . the power reduction adc bit, pradc, in ?prr0 ? power reduction register 0? on page 55 must be disabled by writing a logical zero to be able to use the adc input mux. figure 112. analog comparator block diagram (2) n otes: 1. see table 124 on page 276. 2. refer to figure 1 on page 2 and table 41 on page 92 for analog comparator pin placement. acbg bandgap reference adc multiplexer output acme aden (1) 276 atmega640/1280/1281/2560/2561 2549k?avr?01/07 analog comparator multiplexed input it is possible to select any of the adc15:0 pins to replace the negative input to the ana- log comparator. the adc multiple xer is used to select this input, and consequently, the adc must be switched off to utilize this feature. if the analog comparator multiplexer enable bit (acme in adcsrb) is set and the adc is switched off (ade n in adcsra is zero), mux5 and mux2:0 in admux select the input pin to replace the negative input to the analog comparator, as shown in table 124. if acme is cleared or ade n is set, ai n 1 is applied to the negative input to the analog comparator. table 124. analog comparator mulitiplexed input acme aden mux5 mux2:0 analog comparator negative input 0 x x xxx ai n 1 1 1 x xxx ai n 1 1 0 0 000 adc0 1 0 0 001 adc1 1 0 0 010 adc2 1 0 0 011 adc3 1 0 0 100 adc4 1 0 0 101 adc5 1 0 0 110 adc6 1 0 0 111 adc7 1 0 1 000 adc8 1 0 1 001 adc9 1 0 1 010 adc10 1 0 1 011 adc11 1 0 1 100 adc12 1 0 1 101 adc13 1 0 1 110 adc14 1 0 1 111 adc15 277 atmega640/1280/1281/2560/2561 2549k?avr?01/07 register description adcsrb ? adc control and status register b ? bit 6 ? acme: analog comparator multiplexer enable w hen this bit is written logic one and the adc is switched off (ade n in adcsra is zero), the adc multiplexer selects the negative input to the analog comparator. w hen this bit is written logic zero, ai n 1 is applied to the negative input of the analog compar- ator. for a detailed description of this bit, see ?analog comparator multiplexed input? on page 276. acsr ? analog comparator control and status register ? bit 7 ? acd: analog comparator disable w hen this bit is written logic one, the power to the analog comparator is switched off. this bit can be set at any time to turn o ff the analog comparator . this will reduce power consumption in active and idle mode. w hen changing the acd bit, the analog compar- ator interrupt must be disabled by clearing t he acie bit in acsr. otherwise an interrupt can occur when the bit is changed. ? bit 6 ? acbg: analog comparator bandgap select w hen this bit is set, a fixed bandgap reference voltage replaces the positive input to the analog comparator. w hen this bit is cleared, ai n 0 is applied to the positive input of the analog comparator. w hen the bandgap reference is used as input to the analog com- parator, it will take a certain time for the vo ltage to stabilize. if no t stabilized, the first conversion may give a wrong value. see ?internal voltage reference? on page 61. ? bit 5 ? aco: analog comparator output the output of the analog comparator is synchronized and then directly connected to aco. the synchronization introduces a delay of 1 - 2 clock cycles. ? bit 4 ? aci: analog comparator interrupt flag this bit is set by hardware when a comparator output event triggers the interrupt mode defined by acis1 and acis0. the analog comparator interrupt routine is executed if the acie bit is set and the i-bit in sreg is set. aci is cleared by hardware when execut- ing the corresponding interrupt handling vector. alternatively, aci is cleared by writing a logic one to the flag. ? bit 3 ? acie: analog comparator interrupt enable w hen the acie bit is written logic one and the i-bit in the status register is set, the ana- log comparator interrupt is activated. w hen written logic zero, the interrupt is disabled. bit 7 6543210 (0x7b) ? acme ? ? mux5 adts2 adts1 adts0 adcsrb read/ w rite r r/ w rrr/ w r/ w r/ w r/ w initial value0 0000000 bit 76543210 0x30 (0x50) acd acbg aco aci acie acic acis1 acis0 acsr read/ w rite r/ w r/ w rr/ w r/ w r/ w r/ w r/ w initial value 0 0 n /a00000 278 atmega640/1280/1281/2560/2561 2549k?avr?01/07 ? bit 2 ? acic: analog comparator input capture enable w hen written logic one, this bit enables the i nput capture function in timer/counter1 to be triggered by the analog comparator. the comparator output is in this case directly connected to the input capture front-end logic, making the comparator utilize the noise canceler and edge select features of the timer/counter1 input capture interrupt. w hen written logic zero, no connection between the analog comparator and the input capture function exists. to make the comparator tr igger the timer/counter1 input capture inter- rupt, the icie1 bit in the timer interrupt mask register (timsk1) must be set. ? bits 1, 0 ? acis1, acis0: analog comparator interrupt mode select these bits determine which comparator events that trigger the analog comparator inter- rupt. the different settings are shown in table 125. w hen changing the acis1/acis0 bits, the analog comparator interrupt must be dis- abled by clearing its interrupt enable bit in the acsr register. otherwise an interrupt can occur when the bits are changed. didr1 ? digital input disable register 1 ? bit 1, 0 ? ain1d, ain0d: ain1, ain0 digital input disable w hen this bit is written logic one, the digital input buffer on the ai n 1/0 pin is disabled. the corresponding pi n register bit will always read as zero when this bit is set. w hen an analog signal is applied to the ai n 1/0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. table 125. acis1/acis0 settings acis1 acis0 interrupt mode 0 0 comparator interrupt on output toggle. 01reserved 1 0 comparator interrupt on falling output edge. 1 1 comparator interrupt on rising output edge. bit 76543210 (0x7f) ? ? ? ? ? ? ain1d ain0d didr1 read/ w riterrrrrrr/ w r/ w initial value00000000 279 atmega640/1280/1281/2560/2561 2549k?avr?01/07 adc ? analog to digital converter features ? 10-bit resolution ? 1 lsb integral non-linearity ? 2 lsb absolute accuracy ? 13 - 260 s conversion time ? up to 76.9 ksps (up to 15 ksps at maximum resolution) ? 16 multiplexed single ended input channels ? 14 differential input channels ? 4 differential input channels with optional gain of 10x and 200x ? optional left adjustment for adc result readout ? 0 - v cc adc input voltage range ? 2.7 - v cc differential adc voltage range ? selectable 2.56v or 1.1v adc reference voltage ? free running or single conversion mode ? interrupt on adc co nversion complete ? sleep mode noise canceler the atmega640/1280/1281/2560/2561 features a 10-bit successive approximation adc. the adc is connected to an 8/16-channel analog multiplexer which allows eight/sixteen single-ended voltage inputs cons tructed from the pins of port a and port f. the single-ended voltage inputs refer to 0v (g n d). the device also supports 16/32 differential voltage input combinations. four of the dif- ferential inputs (adc1 & adc0, adc3 & adc2, adc9 & adc8 and adc11 & adc10) are equipped with a programmable gain stage, providing amplification steps of 0 db (1x), 20 db (10x) or 46 db (200x) on the differential input voltage before the adc con- version. the 16 channels are split in two sections of 8 channels where in each section seven differential analog input chann els share a common negative terminal (adc1/adc9), while any other adc input in that section can be selected as the positive input terminal. if 1x or 10x gain is used, 8 bit resolution can be expected. if 200x gain is used, 7 bit resolution can be expected. the adc contains a sample and hold circuit which ensures that the input voltage to the adc is held at a constant level during conv ersion. a block diagram of the adc is shown in figure 113. the adc has a separate analog supply voltage pin, avcc. avcc must not differ more than 0.3v from v cc . see the paragraph ?adc n oise canceler? on page 287 on how to connect this pin. internal reference voltages of nominally 1.1v, 2.56v or avcc are provided on-chip. the voltage reference may be externally decoupled at the aref pin by a capacitor for better noise performance. the power reduction adc bit, pradc, in ?prr0 ? power reduction register 0? on page 55 must be disabled by writing a logical zero to enable the adc. 280 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 113. analog to digital converter block schematic adc conversion complete irq 8-bit databus 15 0 adie adfr adsc aden adif adif mux[4:0] adps[2:0] sample & hold comparator internal reference (1.1v/2.56v) avcc refs[1:0] adlar channel selection adc[9:0] adc multiplexer output gain amplifie r aref bandgap (1.1v) reference gnd conversion logic adc ctrl & status register b (adcsrb) adc ctrl & status register a (adcsra) prescaler adc multiplexer select (admux) mux decoder diff / gain select adc data register (adch/adcl) adc[2:0] trigger select start interrupt flags adts[2:0] + - adc[15:0] + - 10-bit dac mux[5] adc[10:8] 281 atmega640/1280/1281/2560/2561 2549k?avr?01/07 operation the adc converts an analog input voltage to a 10-bit digital value through successive approximation. the minimum value represents g n d and the maximum value represents the voltage on the aref pin minus 1 lsb. optionally, avcc or an internal 1.1v or 2.56v reference voltage may be connected to the aref pin by writing to the refsn bits in the admux register. the internal voltage reference may thus be decoupled by an external capacitor at the aref pin to improve noise immunity. the analog input channel is selected by writing to the mux bits in admux and adc- srb. any of the adc input pins, as well as g n d and a fixed bandgap voltage reference, can be selected as single ended inputs to the adc. a selection of adc input pins can be selected as positive and negative inputs to the differential amplifier. if differential channels are selected, the voltage difference between the selected input channel pair then becomes the analog input to the adc. if single ended channels are used, the amplifier is bypassed altogether. the adc is enabled by setting the adc enable bit, ade n in adcsra. voltage refer- ence and input ch annel selections will not go into effect until ade n is set. the adc does not consume power when ade n is cleared, so it is recommended to switch off the adc before entering power saving sleep modes. the adc generates a 10-bit result which is presented in the adc data registers, adch and adcl. by default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the adlar bit in admux. if the result is left adjusted and no more than 8-bit precision is requir ed, it is sufficient to read adch. otherwise, adcl must be read fi rst, then adch, to en sure that the content of the data registers belongs to the same conversion. once adcl is read, adc access to data registers is blocked. this means that if adcl has been read, and a conversion completes before adch is read, neither register is updated and the result from the con- version is lost. w hen adch is read, adc access to the adch and adcl registers is re-enabled. the adc has its own interrupt which can be triggered when a conversion completes. w hen adc access to the data registers is prohibited between reading of adch and adcl, the interrupt will trigger even if t he result is lost. starting a conversion a single conversion is started by writing a logical one to the adc start conversion bit, adsc. this bit stays high as long as the co nversion is in progress and will be cleared by hardware when the conversion is completed. if a different data channel is selected while a conversion is in progress, the adc will fi nish the current conver sion before performing the channel change. alternatively, a conversion can be triggered automatically by various sources. auto trig- gering is enabled by setting the adc auto trigger enable bit, adate in adcsra. the trigger source is selected by setting t he adc trigger select bits, adts in adcsrb (see description of the adts bits for a list of the trigger sources). w hen a positive edge occurs on the selected trigger signal, the adc prescaler is reset and a conversion is started. this provides a method of starting c onversions at fixed intervals. if the trigger signal still is set when the conversion comple tes, a new conversion will not be started. if another positive edge occurs on the trigger signal during conversion, the edge will be ignored. n ote that an interrupt flag will be set even if the specific interrupt is disabled or the global interrupt enable bit in sreg is cleared. a conversion can thus be triggered without causing an interrupt. however, the interrupt flag must be cleared in order to trig- ger a new conversion at the next interrupt event. 282 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 114. adc auto trigger logic using the adc interrupt flag as a trigger source makes the adc start a new conversion as soon as the ongoing conversion has finished. the adc then operates in free run- ning mode, constantly sampling and updating the adc data register. the first conversion must be started by writing a logical one to the adsc bit in adcsra. in this mode the adc will perform successive c onversions independently of whether the adc interrupt flag, adif is cleared or not. if auto triggering is enabled, single conversions can be started by writing adsc in adcsra to one. adsc can also be used to determine if a conversion is in progress. the adsc bit will be read as one during a conversion, indep endently of how the conver- sion was started. prescaling and conversion timing figure 115. adc prescaler by default, the successive approximation circuitry requires an input clock frequency between 50 khz and 200 khz. if a lower resolution than 10 bits is needed, the input clock frequency to the adc can be as high as 1000 khz to get a higher sample rate. the adc module contains a prescaler, which generates an acceptable adc clock fre- quency from any cpu frequency above 100 khz. the prescaling is set by the adps bits in adcsra. the prescaler starts counting from the moment the adc is switched on by adsc adif source 1 source n adts[2:0] conversion logic prescaler start clk adc . . . . edge detector adate 7-bit adc prescaler adc clock source ck adps0 adps1 adps2 ck/128 ck/2 ck/4 ck/8 ck/16 ck/32 ck/64 reset aden start 283 atmega640/1280/1281/2560/2561 2549k?avr?01/07 setting the ade n bit in adcsra. the prescaler keeps running for as long as the ade n bit is set, and is continuously reset when ade n is low. w hen initiating a single ended conversion by setting the adsc bit in adcsra, the con- version starts at the following rising edge of the adc clock cycle. a normal conversion takes 13 adc clock cycl es. the first conversion after the adc is switched on (ade n in adcsra is set) takes 25 adc cl ock cycles in order to initialize the analog circuitry. w hen the bandga p reference voltage is used as input to the adc, it will take a certain time for the voltage to stabilize. if not stabilized, the first valu e read after the first conver- sion may be wrong. the actual sample-and-hold takes place 1.5 adc clock cycles after the start of a normal conversion and 13.5 adc clock cycles a fter the start of an first conversion. w hen a con- version is complete, the result is written to the adc data registers, and adif is set. in single conversion mode, adsc is cleared simultaneously. the software may then set adsc again, and a new conver sion will be initiated on the fi rst rising adc clock edge. w hen auto triggering is used, the prescaler is reset when the trigger event occurs. this assures a fixed delay from the trigger event to the start of conversion. in this mode, the sample-and-hold takes place two adc clock cycl es after the rising edge on the trigger source signal. three additional cpu clock cycles are used for synchronization logic. in free running mode, a new co nversion will be started im mediately afte r the conver- sion completes, while adsc remains high. for a summary of conversion times, see table 126. figure 116. adc timing diagram, first conversion (single conversion mode) sign and msb of result lsb of result adc clock adsc sample & hold adif adch adcl cycle number aden 1 212 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 first conversion next conversion 3 mux and refs update mux and refs update conversion complete 284 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 117. adc timing diagram, single conversion figure 118. adc timing diagram, auto triggered conversion figure 119. adc timing diagram, free running conversion 1 2 3 4 5 6 7 8 9 10 11 12 13 sign and msb of result lsb of result adc clock adsc adif adch adcl cycle number 12 one conversion next conversion 3 sample & hold mux and refs update conversion complete mux and refs update 1 2 3 4 5 6 7 8 9 10 11 12 13 sign and msb of result lsb of result adc clock trigger source adif adch adcl cycle number 12 one conversion next conversion conversion complete prescaler reset adate prescaler reset sample & hold mux and refs update 11 12 13 sign and msb of result lsb of result adc clock adsc adif adch adcl cycle number 12 one conversion next conversion 34 conversion complete sample & hold mux and refs update 285 atmega640/1280/1281/2560/2561 2549k?avr?01/07 differential channels w hen using differential channels, certain aspects of the conversion need to be taken into consideration. differential conversions are synchronized to the internal clock ck adc2 equal to half the adc clock. this synchronization is done automat ically by the adc interface in such a way that the sample-and-hold occurs at a specific phase of ck adc2 . a conversion initi- ated by the user (i.e., all single conversi ons, and the first free running conversion) when ck adc2 is low will take the same amount of time as a single ended conversion (13 adc clock cycles from the next prescaled clock cycle). a conversion initiated by the user when ck adc2 is high will take 14 adc clock cycl es due to the synch ronization mecha- nism. in free running mode, a new conversion is initiated immediately after the previous conversion completes, and since ck adc2 is high at this time, all automatically started (i.e., all but the first) free running conver sions will take 14 adc clock cycles. if differential channels are used and conversions are started by auto triggering, the adc must be switched off between conversions. w hen auto triggering is used, the adc prescaler is reset before the conversion is started. since the stage is dependent of a stable adc clock prior to the conversion, th is conversion will not be valid. by disabling and then re-enabling the adc between each conversion (writing ade n in adcsra to ?0? then to ?1?), only extended conversions are performed. the result from the extended conversions will be valid. see ?prescaling and conversion timing? on page 282 for tim- ing details. table 126. adc conversion time condition sample & hold (cycles from start of conversion) conversion time (cycles) first conversion 13.5 25 n ormal conversions, single ended 1.5 13 auto triggered conversions 2 13.5 n ormal conversions, differential 1.5/2.5 13/14 286 atmega640/1280/1281/2560/2561 2549k?avr?01/07 changing channel or reference selection the muxn and refs1:0 bits in the admux register are single buffered through a tem- porary register to which the cpu has random access. this ensures that the channels and reference selection only takes place at a safe point during the conversion. the channel and reference selection is continuously updated until a conversion is started. once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the adc. c ontinuous updating resumes in the last adc clock cycle before the conversion comp letes (adif in adcsra is set). n ote that the conversion starts on the following rising adc clock edge after adsc is written. the user is thus advised not to write new channel or reference selection values to admux until one adc clock cycle after adsc is written. if auto triggering is used, the exact time of the triggering event can be indeterministic. special care must be taken when updating the admux register, in order to control which conversion will be affe cted by the new settings. if both adate and ade n is written to one, an interrupt event can occur at any time. if the admux register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. admux can be safely updated in the following ways: 1. w hen adate or ade n is cleared. 2. during conversion, minimum one adc clock cycle after the trigger event. 3. after a conversion, before the interrupt flag used as trigger source is cleared. w hen updating admux in one of these conditions, the new settings will affect the next adc conversion. special care should be taken when changing differential channels. once a differential channel has been selected, the stage may take as much as 125 s to stabilize to the new value. thus conversions should not be started within the first 125 s after selecting a new differential channel. alter natively, conversion results obtained within this period should be discarded. the same settling time should be observed for the first differential conversion after changing adc reference (by changi ng the refs1:0 bits in admux). adc input channels w hen changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: in single conversion mode, always select the channel before starting the conversion. the channel selection may be changed one adc clock cycle af ter writing one to adsc. however, the simplest method is to wait for the conversion to complete before changing the channel selection. in free running mode, always select the channel before starting the first conversion. the channel selection may be changed one adc clock cycle af ter writing one to adsc. however, the simplest method is to wait for the first conversion to complete, and then change the channel selection. since the next conversion has already started automati- cally, the next result will reflect the previo us channel selection. subsequent conversions will reflect the new channel selection. w hen switching to a differential gain channel, the first conversion result may have a poor accuracy due to the required settling time for the automatic offset cancellation cir- cuitry. the user should preferably disregard the first conversion result. 287 atmega640/1280/1281/2560/2561 2549k?avr?01/07 adc voltage reference the reference voltage for the adc (v ref ) indicates the conversion range for the adc. single ended channels that exceed v ref will result in codes close to 0x3ff. v ref can be selected as either avcc, internal 1.1v reference, internal 2.56v reference or external aref pin. avcc is connected to the adc through a pass ive switch. the internal 1.1v reference is generated from the internal bandgap reference (vbg) through an internal amplifier. in either case, the external aref pin is dire ctly connected to the adc, and the reference voltage can be made more immune to noise by connecting a capacitor between the aref pin and ground. v ref can also be measured at the aref pin with a high impedant voltmeter. n ote that v ref is a high impedant source, and only a capacitive load should be connected in a system. the internal 2.56v reference is generated from the 1.1v reference. if the user has a fixed voltage source connected to the aref pin, the user may not use the other reference voltage options in the application, as they will be shorted to the external voltage. if no external voltage is applied to the aref pin, the user may switch between avcc, 1.1v and 2.56v as reference selection. the first adc conversion result after switching reference voltage source may be inaccurate, and the user is advised to discard this result. if differential channels are used, the select ed reference should not be closer to avcc than indicated in ?adc characteristics ? preliminary data? on page 382. adc noise canceler the adc features a noise canceler that enables conversion during sleep mode to reduce noise induced from the cpu core and other i/o peripherals. the noise canceler can be used with adc n oise reduction and idle mode. to make use of this feature, the following procedure should be used: 1. make sure that the adc is enabled and is not busy converting. single con- version mode must be selected and the adc conversion complete interrupt must be enabled. 2. enter adc n oise reduction mode (or idle mode). the adc will start a con- version once the cpu has been halted. 3. if no other interrupts occur before the adc conversion completes, the adc interrupt will wake up the cpu and ex ecute the adc conversion complete interrupt routine. if another interrupt wakes up the cpu before the adc con- version is complete, that interrupt will be executed, and an adc conversion complete interrupt request will be generated when the adc conversion completes. the cpu will remain in acti ve mode until a new sleep command is executed. n ote that the adc will not be au tomatically turned off when entering other sleep modes than idle mode and adc n oise reduction mode. the user is advised to write zero to ade n before entering such sleep modes to avoid excessive power consumption. if the adc is enabled in such sleep modes and the user wants to perform differential conversions, the user is advised to switch the adc off and on after waking up from sleep to prompt an extended conversion to get a valid result. 288 atmega640/1280/1281/2560/2561 2549k?avr?01/07 analog input circuitry the analog input circuitry for single ended channels is illust rated in figure 120. an ana- log source applied to adcn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the adc. w hen the chan- nel is selected, the source must drive the s/h capacitor through the series resistance (combined resistance in the input path). the adc is optimized for analog signals with an output impedance of approximately 10 k or less. if such a source is used, the sampling time will be negligible. if a source with higher impedance is used, the sampling time will depend on how long time the source needs to charge the s/h capacitor, which can vary widely. the user is recom- mended to only use low impedant sources wit h slowly varying signals, since this minimizes the required charge transfer to the s/h capacitor. signal components higher than the n yquist frequency (f adc /2) should not be present for either kind of channels, to avoid distortion from unpredictable signal convolution. the user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the adc. figure 120. analog input circuitry analog noise canceling techniques digital circuitry inside and outside the device generates emi which might affect the accuracy of analog measurements. if conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. keep analog signal paths as short as possible. make sure analog tracks run over the ground plane, and keep them well away from high-speed switching digital tracks. 2. the avcc pin on the device should be connected to the digital v cc supply voltage via an lc network as shown in figure 121. 3. use the adc noise canceler function to reduce induced noise from the cpu. 4. if any adc port pins are used as digital outputs, it is essential that these do not switch while a conversion is in progress. adcn i ih 1..100 k c s/h = 14 pf v cc /2 i il 289 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 121. adc power connections, atmega1281/2561. figure 122. adc power connections, atmega640/1280/2560 vcc g n d 100nf ground plane (adc0) pf0 (adc7) pf7 (adc1) pf1 (adc2) pf2 (adc3) pf3 (adc4) pf4 (adc5) pf5 (adc6) pf6 aref g n d avcc 52 53 54 55 56 57 58 59 60 61 61 62 62 63 63 64 64 1 51 pg5 pa0 10 ? 100nf ground plane 100 (oc0b) pg5 10 ? 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 pj7 vcc g n d (adc15/pci n t23) pk7 (adc14/pci n t22) pk6 (adc13/pci n t21) pk5 (adc12/pci n t20) pk4 (adc11/pci n t19) pk3 (adc10/pci n t18) pk2 (adc9/pci n t17) pk1 (adc8/pci n t16) pk0 (adc7/tdi) pf7 (adc6/tdo) pf6 (adc5/tms) pf5 (adc4/tck) pf4 (adc3) pf3 (adc2) pf2 (adc1) pf1 (adc0) pf0 aref g n d avcc 290 atmega640/1280/1281/2560/2561 2549k?avr?01/07 offset compensation schemes the stage has a built-in offset cancellation circui try that nulls the offset of differential measurements as much as possible. the remaining offset in the analog path can be measured directly by selecting the same channe l for both differential inputs. this offset residue can be then subtracted in software from the measurement results. using this kind of software based offset correction, offset on any channel can be reduced below one lsb. adc accuracy definitions an n-bit single-ended adc converts a voltage linearly between g n d and v ref in 2 n steps (lsbs). the lowest code is read as 0, and the highest code is read as 2 n -1. several parameters describe the deviation from the ideal behavior: ? offset: the deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 lsb). ideal value: 0 lsb. figure 123. offset error ? gain error: after adjusting for offset, the gain error is found as the deviation of the last transition (0x3fe to 0x3ff) compared to the ideal transition (at 1.5 lsb below maximum). ideal value: 0 lsb figure 124. gain error output code v ref input voltage ideal adc actual adc offset error output code v ref input voltage ideal adc actual adc gain error 291 atmega640/1280/1281/2560/2561 2549k?avr?01/07 ?integral n on-linearity (i n l): after adjusting for offset and gain error, the i n l is the maximum deviation of an actual transition compared to an ideal transition for any code. ideal value: 0 lsb. figure 125. integral n on-linearity (i n l) ? differential n on-linearity (d n l): the maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 lsb). ideal value: 0 lsb. figure 126. differential n on-linearity (d n l) ? quantization error: due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 l sb wide) will code to the same value. always 0.5 lsb. ? absolute accuracy: the maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. this is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. ideal value: 0.5 lsb. output code v ref input voltage ideal adc actual adc inl output code 0x3ff 0x000 0 v ref input voltage dnl 1 lsb 292 atmega640/1280/1281/2560/2561 2549k?avr?01/07 adc conversion result after the conversion is complete (adif is high), the conversion result can be found in the adc result registers (adcl, adch). for single ended conversion, the result is where v i n is the voltage on the selected input pin and v ref the selected voltage refer- ence (see table 128 on page 294 and table 129 on page 295). 0x000 represents analog ground, and 0x3ff represents the selected reference voltage minus one lsb. if differential channels are used, the result is where v pos is the voltage on the positive input pin, v n eg the voltage on the negative input pin, and v ref the selected voltage reference. the result is presented in two?s com- plement form, from 0x200 (-512d) through 0x1ff (+511d). n ote that if the user wants to perform a quick polarity check of the result, it is sufficient to read the msb of the result (adc9 in adch). if the bit is one, the result is negative, and if this bit is zero, the result is positive. figure 127 shows the decoding of the differential input range. table 127 shows the resulting output codes if the differential input channel pair (adcn - adcm) is selected with a gain of gai n and a reference voltage of v ref . figure 127. differential measurement range adc v in 1024 ? v ref -------------------------- = adc v pos v neg ? () 512 ? v ref ---------------------------------------------------- - = 0 output code 0x1ff 0x000 v ref differential input voltage (volts) 0x3ff 0x200 - v ref 293 atmega640/1280/1281/2560/2561 2549k?avr?01/07 example: admux = 0xfb (adc3 - adc2, 10x gain, 2.56v reference, left adjusted result) voltage on adc3 is 300 mv, voltage on adc2 is 500 mv. adcr = 512 * 10 * (300 - 500) / 2560 = -400 = 0x270. adcl will thus read 0x00, and adch will read 0x9c. w riting zero to adlar right adjusts the result: adcl = 0x70, adch = 0x02. table 127. correlation between input voltage and output codes v adcn read code correspondi ng decimal value v adcm + v ref / gai n 0x1ff 511 v adcm + 0.999 v ref / gai n 0x1ff 511 v adcm + 0.998 v ref / gai n 0x1fe 510 ... ... ... v adcm + 0.001 v ref / gai n 0x001 1 v adcm 0x000 0 v adcm - 0.001 v ref / gai n 0x3ff -1 ... ... ... v adcm - 0.999 v ref / gai n 0x201 -511 v adcm - v ref / gai n 0x200 -512 294 atmega640/1280/1281/2560/2561 2549k?avr?01/07 register description admux ? adc multiplexer selection register ? bit 7:6 ? refs1:0: reference selection bits these bits select the voltage reference for th e adc, as shown in table 128. if these bits are changed during a co nversion, the change will not go in effect until this conversion is complete (adif in adcsra is set). the internal voltage reference options may not be used if an external reference voltage is being applied to the aref pin. n ote: 1. if 10x or 200x gain is selected, only 2.56 v should be used as internal voltage refer- ence. for differential conversion, only 1. 1v cannot be used as internal voltage reference. ? bit 5 ? adlar: adc left adjust result the adlar bit affects the presentation of the adc conversion result in the adc data register. w rite one to adlar to left adjust the result. otherwise, the result is right adjusted. changing the adlar bit will affe ct the adc data register immediately, regardless of any ongoing conversions. for a complete description of this bit, see ?adcl and adch ? the adc data register? on page 298. ? bits 4:0 ? mux4:0: analog channel and gain selection bits the value of these bits selects which combination of analog inputs are connected to the adc. see table 129 for details. if these bits are changed during a conversion, the change will not go in ef fect until this conversion is co mplete (adif in adcsra is set) bit 76543210 (0x7c) refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 admux read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 table 128. voltage reference selections for adc refs1 refs0 voltage reference selection (1) 0 0 aref, internal v ref turned off 0 1 avcc with external capacitor at aref pin 1 0 internal 1.1v voltage reference wit h external capacitor at aref pin 1 1 internal 2.56v voltage reference with external capacitor at aref pin 295 atmega640/1280/1281/2560/2561 2549k?avr?01/07 adcsrb ? adc control and status register b ? bit 3 ? mux5: analog channel and gain selection bit this bit is used together with mux4:0 in ad mux to select which co mbination in of ana- log inputs are connected to the adc. see tabl e 129 for details. if this bit is changed during a conversion, th e change will not go in effect until this conversion is complete. this bit is not valid for atmega1281/2561. bit 76543210 (0x7b) ? acme ? ?mux5 adts2 adts1 adts0 adcsrb read/ w rite r r/ w rrr/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 table 129. input channel selections mux5:0 single ended input positive differential input negative differential input gain 000000 adc0 n /a 000001 adc1 000010 adc2 000011 adc3 000100 adc4 000101 adc5 000110 adc6 000111 adc7 001000 (1) n /a adc0 adc0 10x 001001 (1) adc1 adc0 10x 001010 (1) adc0 adc0 200x 001011 (1) adc1 adc0 200x 001100 (1) adc2 adc2 10x 001101 (1) adc3 adc2 10x 001110 (1) adc2 adc2 200x 001111 (1) adc3 adc2 200x 010000 adc0 adc1 1x 010001 adc1 adc1 1x 010010 adc2 adc1 1x 010011 adc3 adc1 1x 010100 adc4 adc1 1x 010101 adc5 adc1 1x 010110 adc6 adc1 1x 010111 adc7 adc1 1x 011000 adc0 adc2 1x 011001 adc1 adc2 1x 296 atmega640/1280/1281/2560/2561 2549k?avr?01/07 011010 n /a adc2 adc2 1x 011011 adc3 adc2 1x 011100 adc4 adc2 1x 011101 adc5 adc2 1x 011110 1.1v (v bg ) n /a 011111 0v (g n d) 100000 adc8 n /a 100001 adc9 100010 adc10 100011 adc11 100100 adc12 100101 adc13 100110 adc14 100111 adc15 101000 (1) n /a adc8 adc8 10x 101001 (1) adc9 adc8 10x 101010 (1) adc8 adc8 200x 101011 (1) adc9 adc8 200x 101100 (1) adc10 adc10 10x 101101 (1) adc11 adc10 10x 101110 (1) adc10 adc10 200x 101111 (1) adc11 adc10 200x 110000 adc8 adc9 1x 110001 adc9 adc9 1x 110010 adc10 adc9 1x 110011 adc11 adc9 1x 110100 adc12 adc9 1x 110101 adc13 adc9 1x 110110 adc14 adc9 1x 110111 adc15 adc9 1x 111000 adc8 adc10 1x 111001 adc9 adc10 1x 111010 adc10 adc10 1x 111011 adc11 adc10 1x 111100 adc12 adc10 1x table 129. input channel selections (continued) mux5:0 single ended input positive differential input negative differential input gain 297 atmega640/1280/1281/2560/2561 2549k?avr?01/07 n ote: 1. to reach the given accuracy, 10x or 200x gain should not be used for operating volt- age below 2.7v adcsra ? adc control and status register a ? bit 7 ? aden: adc enable w riting this bit to one enables the adc. by writing it to zero, the adc is turned off. turn- ing the adc off while a conversion is in progress, will terminate this conversion. ? bit 6 ? adsc: adc start conversion in single conversion mode, write this bit to one to start each conversion. in free run- ning mode, write this bit to one to start th e first conversion. the first conversion after adsc has been written after the adc has been enabled, or if adsc is written at the same time as the adc is enabled, will take 25 adc clock cycles instead of the normal 13. this first conversion performs initialization of the adc. adsc will read as one as long as a conversion is in progress. w hen the conversion is complete, it returns to zero. w riting zero to this bit has no effect. ? bit 5 ? adate: adc auto trigger enable w hen this bit is written to on e, auto triggering of the ad c is enabled. the adc will start a conversion on a positive edge of the selected trigger signal. the trigger source is selected by setting the adc trigge r select bits, adts in adcsrb. ? bit 4 ? adif: adc interrupt flag this bit is set when an adc conversion completes and the data registers are updated. the adc conversion complete interrupt is executed if the adie bit and the i-bit in sreg are set. adif is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, adif is cleared by writing a logical one to the flag. beware that if doing a read-modify- w rite on adcsra, a pending interrupt can be dis- abled. this also applies if the sbi and cbi instructions are used. ? bit 3 ? adie: adc interrupt enable w hen this bit is written to one and the i-bit in sreg is set, the adc conversion com- plete interrupt is activated. ? bits 2:0 ? adps2:0: adc prescaler select bits these bits determine the division factor between the xtal frequency and the input clock to the adc. 111101 n /a adc13 adc10 1x 111110 reserved n /a 111111 reserved n /a table 129. input channel selections (continued) mux5:0 single ended input positive differential input negative differential input gain bit 76543210 (0x7a) aden adsc adate adif adie adps2 adps1 adps0 adcsra read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 298 atmega640/1280/1281/2560/2561 2549k?avr?01/07 adcl and adch ? the adc data register adlar = 0 adlar = 1 w hen an adc conversion is complete, the result is found in these two registers. if differ- ential channels are used, the result is presented in two?s complement form. w hen adcl is read, the adc data register is not updated until adch is read. conse- quently, if the result is left adjusted and no more than 8-bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read adch. otherwise, adcl must be read first, then adch. the adlar bit in admux, and the muxn bits in admux affect the way the result is read from the registers. if adlar is set, the result is left adjusted. if adlar is cleared (default), the result is right adjusted. ? adc9:0: adc conversion result these bits represent the result from the conversion, as detailed in ?adc conversion result? on page 292. table 130. adc prescaler selections adps2 adps1 adps0 division factor 0002 0012 0104 0118 10016 10132 11064 111128 bit 151413121110 9 8 (0x79) ? ? ? ? ? ? adc9 adc8 adch (0x78) adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 adcl 76543210 read/ w riterrrrrrrr rrrrrrrr initial value00000000 00000000 bit 151413121110 9 8 (0x79) adc9 adc8 adc7 adc6 adc5 adc4 adc3 adc2 adch (0x78) adc1 adc0 ? ????? adcl 76543210 read/ w riterrrrrrrr rrrrrrrr initial value00000000 00000000 299 atmega640/1280/1281/2560/2561 2549k?avr?01/07 adcsrb ? adc control and status register b ? bit 7 ? res: reserved bit this bit is reserved for future use. to ensure compatibility with future devices, this bit must be written to zero when adcsrb is written. ? bit 2:0 ? adts2:0: adc auto trigger source if adate in adcsra is written to one, the value of these bits se lects which source will trigger an adc conversion. if adate is cleared, the adts2:0 settings will have no effect. a conversion will be triggered by the rising edge of the selected interrupt flag. n ote that switching from a trigger source that is cleared to a trigger source that is set, will generate a positive edge on the trigger signal. if ade n in adcsra is set, this will start a conversion. switching to free runn ing mode (adts[2:0]=0 ) will not cause a trig- ger event, even if the adc interrupt flag is set . n ote: free running mode cannot be used for diff erential channels. (see chapter ?differential channels? on page 285) bit 76543210 (0x7b) ? acme ? ? mux5 adts2 adts1 adts0 adcsrb read/ w rite r r/ w rrr/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 table 131. adc auto trigger source selections adts2 adts1 adts0 trigger source 0 0 0 free running mode 0 0 1 analog comparator 0 1 0 external interrupt request 0 0 1 1 timer/counter0 compare match a 1 0 0 timer/counter0 overflow 1 0 1 timer/counter1 compare match b 1 1 0 timer/counter1 overflow 1 1 1 timer/counter1 capture event 300 atmega640/1280/1281/2560/2561 2549k?avr?01/07 didr0 ? digital input disable register 0 ? bit 7:0 ? adc7d:adc0d: adc7 :0 digital input disable w hen this bit is written logic one, the digital input buffer on the corresponding adc pin is disabled. the corresponding pi n register bit will always read as zero when this bit is set. w hen an analog signal is applied to the adc7:0 pin and the digital input from this pin is not needed, this bit should be writt en logic one to reduce power consumption in the digital input buffer. didr2 ? digital input disable register 2 ? bit 7:0 ? adc15d:adc8d: adc15:8 digital input disable w hen this bit is written logic one, the digital input buffer on the corresponding adc pin is disabled. the corresponding pi n register bit will always read as zero when this bit is set. w hen an analog signal is applied to the adc15:8 pin and the digital input from this pin is not needed, this bit should be writt en logic one to reduce power consumption in the digital input buffer. bit 76543210 (0x7e) adc7d adc6d adc5d adc4d adc3d adc2d adc1d adc0d didr0 read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 (0x7d) adc15d adc14d adc13d adc12d adc11d adc10d adc9d adc8d didr2 read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 301 atmega640/1280/1281/2560/2561 2549k?avr?01/07 jtag interface and on-chip debug system features ? jtag (ieee std. 1149.1 compliant) interface ? boundary-scan capabilities according to the ieee std. 1149.1 (jtag) standard ? debugger access to: ? all internal peripheral units ? internal and external ram ? the internal register file ?program counter ? eeprom and flash memories ? extensive on-chip debug support for break conditions, including ? avr break instruction ? break on change of program memory flow ? single step break ? program memory break points on single address or address range ? data memory break points on single address or address range ? programming of flash, eeprom , fuses, and lock bits through the jtag interface ? on-chip debugging supported by avr studio ? overview the avr ieee std. 1149.1 compliant jtag interface can be used for ? testing pcbs by using the jtag boundary-scan capability ? programming the non-volatile memories, fuses and lock bits ? on-chip debugging a brief description is given in the following sections. detailed descriptions for program- ming via the jtag interface, and using the boundary-scan chain can be found in the sections ?programming via the jtag interface? on page 361 and ?ieee 1149.1 (jtag) boundary-scan? on page 308 , respectively. the on-chip debug support is considered being private jtag instructions, and distributed within atmel and to selected third party vendors only. figure 128 shows a block diagram of the jtag interface and the on-chip debug sys- tem. the tap controller is a state machine controlled by the tck and tms signals. the tap controller selects either the jtag instru ction register or one of several data reg- isters as the scan chain (shift register) between the tdi ? input and tdo ? output. the instruction register holds jtag instructions controlling the behavior of a data register. the id-register, bypass register, and the boundary-scan chain are the data registers used for board-level testing. the jtag programming interface (actually consisting of several physical and virtual data registers) is used for serial programming via the jtag interface. the internal scan chain and br eak point scan chain are used for on-chip debugging only. 302 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 128. block diagram tap controller tdi tdo tck tms flash memory avr cpu digital peripheral units jtag / avr core communication interface breakpoint unit flow control unit ocd status and control internal scan chain m u x instruction register id register bypass register jtag programming interface pc instruction address data breakpoint scan chain address decoder analog peripherial units i/o port 0 i/o port n boundary scan chain analog inputs control & clock lines device boundary 303 atmega640/1280/1281/2560/2561 2549k?avr?01/07 tap - test access port the jtag interface is accessed through four of the avr?s pins. in jtag terminology, these pins constitute the test ac cess port ? tap. these pins are: ? tms: test mode select. this pin is used for navigating through the tap-controller state machine. ? tck: test clock. jtag operation is synchronous to tck. ? tdi: test data in. serial input data to be shifted in to the instruction register or data register (scan chains). ? tdo: test data out. serial output data from instruction register or data register. the ieee std. 1149.1 also sp ecifies an optional tap si gnal; trst ? test reset ? which is not provided. w hen the jtage n fuse is unprogrammed, these four tap pins are normal port pins, and the tap controller is in reset. w hen programmed, the input tap signals are inter- nally pulled high and the jtag is enabled for boundary-scan and programming. the device is shipped with this fuse programmed. for the on-chip debug system, in addition to the jtag interface pins, the reset pin is monitored by the debugger to be able to detect external reset sources. the debugger can also pull the reset pin low to reset the whole syst em, assuming only open collec- tors on the reset line are used in the application. figure 129. tap controller state diagram test-logic-reset run-test/idle shift-dr exit1-dr pause-dr exit2-dr update-dr select-ir scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select-dr scan capture-dr 0 1 0 11 1 00 00 11 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 1 1 304 atmega640/1280/1281/2560/2561 2549k?avr?01/07 tap controller the tap controller is a 16-state finite stat e machine that controls the operation of the boundary-scan circuitry, jtag programming circuitry, or on-chip debug system. the state transitions depicted in figure 129 depend on the signal present on tms (shown adjacent to each state transition) at the time of the rising edge at tck. the initial state after a power-on reset is test-logic-reset. as a definition in this document, the lsb is shifted in and out first for all shift registers. assuming run-test/idle is the present state, a typical scenario for using the jtag inter- face is: ? at the tms input, apply the sequence 1, 1, 0, 0 at the rising edges of tck to enter the shift instruction register ? shift-ir state. w hile in this state, shift the four bits of the jtag instructions into the jtag instruction register from the tdi input at the rising edge of tck. the tms input must be held low during input of the 3 lsbs in order to remain in the shift-ir state. the msb of the instruction is shifted in when this state is left by setting tms high. w hile the instruction is shifted in from the tdi pin, the captured ir-state 0x01 is shifted out on the tdo pin. the jtag instruction selects a particular data register as path between tdi and tdo and controls the circuitry surrounding the selected data register. ? apply the tms sequence 1, 1, 0 to re-enter the run-test/idle state. the instruction is latched onto the parallel output from the shift register path in the update-ir state. the exit-ir, pause-ir, and exit2-ir states are only used for navigating the state machine. ? at the tms input, apply the sequence 1, 0, 0 at the rising edges of tck to enter the shift data register ? shift-dr state. w hile in this state, up load the selected data register (selected by the present jtag instruction in the jtag instruction register) from the tdi input at the rising edge of tck. in order to remain in the shift-dr state, the tms input must be held low during input of all bits except the msb. the msb of the data is shifted in when this state is left by setting tms high. w hile the data register is shifted in from the tdi pin, the parallel inputs to the data register captured in the capture-dr state is shifted out on the tdo pin. ? apply the tms sequence 1, 1, 0 to re-enter the run-test/idle state. if the selected data register has a latched parallel-output, the latching takes place in the update- dr state. the exit-dr, pause-dr, and exit2- dr states are only used for navigating the state machine. as shown in the state diagram, the run-test/idle state need not be entered between selecting jtag instruction and using data re gisters, and some jtag instructions may select certain functions to be performed in the run-test/idle, making it unsuitable as an idle state. n ote: independent of the initial state of the tap controller, the test-logic-reset state can always be entered by holding tms high for five tck clock periods. for detailed information on the jtag specificati on, refer to the literature listed in ?bibli- ography? on page 306. 305 atmega640/1280/1281/2560/2561 2549k?avr?01/07 using the boundary- scan chain a complete description of the boundary-scan capabilities are given in the section ?ieee 1149.1 (jtag) boundary-scan? on page 308. using the on-chip debug system as shown in figure 128, the hardware support for on-chip debugging consists mainly of ? a scan chain on the interface between the internal avr cpu and the internal peripheral units. ? break point unit. ? communication interface betw een the cpu and jtag system. all read or modify/write operations needed for implementing the debugger are done by applying avr instructions via the internal avr cpu scan chain. the cpu sends the result to an i/o memory mapped location which is part of the communication interface between the cpu and the jtag system. the break point unit implements break on change of program flow, single step break, two program memory break points, and two combined break points. together, the four break points can be configured as either: ? 4 single program memory break points. ? 3 single program memory break point + 1 single data memory break point. ? 2 single program memory break points + 2 single data memory break points. ? 2 single program memory break points + 1 program memory break point with mask (?range break point?). ? 2 single program memory break points + 1 data memory break point with mask (?range break point?). a debugger, like the avr studio, may however use one or more of these resources for its internal purpose, leaving le ss flexibility to the end-user. a list of the on-chip debug specific jtag inst ructions is given in ?on-chip debug spe- cific jtag instructions? on page 306. the jtage n fuse must be programmed to enable the jtag test access port. in addi- tion, the ocde n fuse must be programmed and no lock bits must be set for the on- chip debug system to work. as a security feature, the on-chip debug system is disabled when either of the lb1 or lb2 lock bits are set. otherwise, the on-chip debug system would have provided a back-door into a secured device. the avr studio enables the user to fully control execution of programs on an avr device with on-chip debug capability, avr in -circuit emulator, or the built-in avr instruction set simulator. avr studio ? supports source level execution of assembly programs assembled with atmel corporation?s avr assembler and c programs com- piled with third part y vendors? compilers. avr studio runs under microsoft ? w indows ? 95/98/2000 and microsoft w indows n t ? . for a full description of the avr studio, please refer to the avr studio user guide. only highlights are presented in this document. all necessary execution commands are available in avr studio, both on source level and on disassembly level. the user can execute the program, single step through the code either by tracing into or stepping over functions, step out of functions, place the cursor on a statement and execute until the statement is reached, stop the execution, and reset the execution target. in addition, the user can have an unlimited number of code break points (using the break instru ction) and up to two data memory break points, alternatively combined as a mask (range) break point. 306 atmega640/1280/1281/2560/2561 2549k?avr?01/07 on-chip debug specific jtag instructions the on-chip debug support is considered being private jtag instructions, and distrib- uted within atmel and to selected third party vendors only. instruction opcodes are listed for reference. private0; 0x8 private jtag instruction for accessing on-chip debug system. private1; 0x9 private jtag instruction for accessing on-chip debug system. private2; 0xa private jtag instruction for accessing on-chip debug system. private3; 0xb private jtag instruction for accessing on-chip debug system. using the jtag programming capabilities programming of avr parts via jtag is performed via the 4-pin jtag port, tck, tms, tdi, and tdo. these are the only pins that need to be controlled/observed to perform jtag programming (in addition to power pins). it is not required to apply 12v externally. the jtage n fuse must be programmed and the jtd bit in the mcucr register must be cleared to enable the jtag test access port. the jtag programmi ng capability supports: ? flash programming and verifying. ? eeprom programming and verifying. ? fuse programming and verifying. ? lock bit programming and verifying. the lock bit security is exactly as in paralle l programming mode. if the lock bits lb1 or lb2 are programmed, the ocde n fuse cannot be programmed unless first doing a chip erase. this is a security feature that ensures no back-door exists for reading out the content of a secured device. the details on programming through the jtag interface and programming specific jtag instructions are given in the section ?programming via the jtag interface? on page 361. bibliography for more information about general boundary-scan, the following literature can be consulted: ? ieee: ieee std. 1149. 1-1990. ieee standard test access port and boundary-scan architecture, ieee, 1993. ? colin maunder: the board designers guide to testable logic circuits, addison- w esley, 1992. 307 atmega640/1280/1281/2560/2561 2549k?avr?01/07 on-chip debug related register in i/o memory ocdr ? on-chip debug register the ocdr register provides a communication channel from the running program in the microcontroller to the debugger. the cpu can transfer a byte to the debugger by writing to this location. at the same time, an internal flag; i/o debug register dirty ? idrd ? is set to indicate to the debugger that the register has been written. w hen the cpu reads the ocdr register the 7 lsb will be from the ocdr register, while the msb is the idrd bit. the debugger clears the idrd bit when it has read the information. in some avr devices, this register is shared with a standard i/o location. in this case, the ocdr register can only be accessed if the ocde n fuse is programmed, and the debugger enables access to the ocdr register. in all other cases, the standard i/o location is accessed. refer to the debugger documentation for further information on how to use this register. bit 7 6543210 0x31 (0x51) msb/idrd lsb ocdr read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 308 atmega640/1280/1281/2560/2561 2549k?avr?01/07 ieee 1149.1 (jtag) boundary-scan features ? jtag (ieee std. 1149.1 compliant) interface ? boundary-scan capabilities acco rding to the jtag standard ? full scan of all port functions as well as analog circuitry having off-chip connections ? supports the optional idcode instruction ? additional public avr_reset instruction to reset the avr system overview the boundary-scan chain has th e capability of driving and observing the logic levels on the digital i/o pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connec tions. at system level, all ics having jtag capabilities are connected serially by the tdi/tdo signals to form a long shift register. an external controller sets up the devices to drive values at their output pins, and observe the input values received from other devices. the controller compares the received data with the expected result. in this way, boundary-scan provides a mechanism for testing intercon- nections and integrity of components on print ed circuits boards by using the four tap signals only. the four ieee 1149.1 defin ed mandatory jtag instru ctions idcode, bypass, sam- ple/preload, and extest, as well as the avr specific public jtag instruction avr_reset can be used for testing the printe d circuit board. initial scanning of the data register path will show the id-code of the device, since idcode is the default jtag instruction. it may be desirable to have the avr device in reset during test mode. if not reset, inputs to the device may be determined by the scan operations, and the internal software may be in an undetermined state when exiting the test mode. entering reset, the outputs of any port pin will instantly enter the high impedance state, making the highz instruction redundant. if needed, the bypass instruction can be issued to make the shortest possible scan chain through the device. the device can be set in the reset state either by pulling the external reset pin low, or issuing the avr_reset instruction with appropriate setting of the reset data register. the extest instruction is used for sampling external pins and loading output pins with data. the data from the output latch will be driven out on the pins as soon as the extest instruction is loaded into the jtag ir-register. therefore, the sample/pre- load should also be used for setting initial values to the scan ring, to avoid damaging the board when issuing the extest instruct ion for the first time. sample/preload can also be used for taking a snapshot of the external pins during normal operation of the part. the jtage n fuse must be programmed and the jtd bit in the i/o register mcucr must be cleared to enable the jtag test access port. w hen using the jtag interface for boundary-scan, using a jtag tck clock frequency higher than the internal chip frequency is po ssible. the chip clock is not required to run. data registers the data registers relevant for boundary-scan operations are: ? bypass register ? device identification register ? reset register ? boundary-scan chain 309 atmega640/1280/1281/2560/2561 2549k?avr?01/07 bypass register the bypass register consists of a single shift register stage. w hen the bypass regis- ter is selected as path between tdi and tdo, the register is reset to 0 when leaving the capture-dr controller state. the bypass register can be used to shorten the scan chain on a system when the other devices are to be tested. device identification register figure 130 shows the structure of the device identification register. figure 130. the format of the device identification register version version is a 4-bit number identifying the revision of the component. the jtag version number follows the revision of the device. revi sion a is 0x0, revision b is 0x1 and so on. part number the part number is a 16-bit code identifying the component. the jtag part n umber for atmega640/1280/1281/2560/2561 is listed in table 154 on page 345. manufacturer id the manufacturer id is a 11-bit code identifying the manufacturer. the jtag manufac- turer id for atmel is listed in table 154 on page 345. reset register the reset register is a test data register used to reset the part. since the avr tri- states port pins when reset, the reset regi ster can also replace the function of the unimplemented optional jtag instruction highz. a high value in the reset register corresponds to pulling the external reset low. the part is reset as long as there is a high value present in the reset register. depending on the fuse settings for the clock options, the part will remain reset for a reset time-out period (see ?clock sources? on page 39) after releasing the reset register. the output from this data register is not latched, so the reset will take place immediately, as shown in figure 131. figure 131. reset register msb lsb bit 31 28 27 12 11 1 0 device id version part number manufacturer id 1 4 bits 16 bits 11 bits 1-bit dq from tdi clockdr avr_reset to tdo from other internal and external reset sources internal reset 310 atmega640/1280/1281/2560/2561 2549k?avr?01/07 boundary-scan chain the boundary-scan chain has th e capability of driving and ob serving the logic levels on the digital i/o pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. see ?boundary-scan chain? on page 311 for a complete description. boundary-scan specific jtag instructions the instruction register is 4-bit wide, supporting up to 16 instructions. listed below are the jtag instructions useful for boundary-scan operation. n ote that the optional highz instruction is not implemented, but all outputs with tri-state capability c an be set in high- impedant state by using the avr_reset instruction, since the initial state for all port pins is tri-state. as a definition in this datasheet, the lsb is shifted in and out first for all shift registers. the opcode for each instruction is shown behind the instruction name in hex format. the text describes which data register is selected as path between tdi and tdo for each instruction. extest; 0x0 mandatory jtag instruction for selecting the boundary-scan chain as data register for testing circuitry external to the avr pack age. for port-pins, pull-up disable, output control, output data, and input data are all accessible in the scan chain. for analog cir- cuits having off-chip connecti ons, the interface between the analog and the digital logic is in the scan chain. the contents of the latched outputs of the boundary-scan chain is driven out as soon as the jtag ir-register is loaded with the extest instruction. the active states are: ? capture-dr: data on the external pins are sampled into the boundary-scan chain. ? shift-dr: the internal scan chain is shifted by the tck input. ? update-dr: data from the scan chain is applied to output pins. idcode; 0x1 optional jtag instruction selecting the 32 bit id-register as data register. the id- register consists of a version number, a device number and the manufacturer code chosen by jedec. this is the default instruction after power-up. the active states are: ? capture-dr: data in the idcode register is sampled into the boundary-scan chain. ? shift-dr: the idcode scan chain is shifted by the tck input. sample_preload; 0x2 mandatory jtag instruction for pre-loading the output latches and taking a snap-shot of the input/output pins without affecting the system operation. however, the output latches are not connected to the pins. the boundary-scan chain is selected as data register. the active states are: ? capture-dr: data on the external pins are sampled into the boundary-scan chain. ? shift-dr: the boundary-scan chain is shifted by the tck input. ? update-dr: data from the boundary-scan chain is applied to the output latches. however, the output latches are not connected to the pins. avr_reset; 0xc the avr specific public jtag instruction for forcing the avr device into the reset mode or releasing the jtag reset source. the tap controller is not reset by this instruc- tion. the one bit reset register is selected as data register. n ote that the reset will be active as long as there is a logic ?one? in the reset chain. the output from this chain is not latched. 311 atmega640/1280/1281/2560/2561 2549k?avr?01/07 the active states are: ? shift-dr: the reset register is shifted by the tck input. bypass; 0xf mandatory jtag instruction selecting the bypass register for data register. the active states are: ? capture-dr: loads a logic ?0? into the bypass register. ? shift-dr: the bypass register cell between tdi and tdo is shifted. boundary-scan chain the boundary-scan chain has th e capability of driving and observing the logic levels on the digital i/o pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connection. scanning the digital port pins figure 132 shows the boundary-scan cell for a bi-directional port pin. the pull-up func- tion is disabled during boundary-scan when the jtag ic contains extest or sample_preload. the cell consists of a bi -directional pin cell that combines the three signals output control - ocxn, output data - odxn, and input data - idxn, into only a two-stage shift register. the port and pin indexes are not used in the following description the boundary-scan logic is not included in the figures in the datasheet. figure 133 shows a simple digital port pin as described in the section ?i/o-ports? on page 83. the boundary-scan details from figure 132 re places the dashed box in figure 133. w hen no alternate port function is present, the input data - id - corresponds to the pi n xn register value (but id has no synchronizer), output data corresponds to the port register, output control corresponds to the data direction - dd register, and the pull-up enable - puexn - corresponds to logic expression pud ddxn portxn. digital alternate port functions are connec ted outside the dotted box in figure 133 to make the scan chain read the actual pin value. for analog function, there is a direct con- nection from the external pin to the anal og circuit. there is no scan chain on the interface between the digital and the analog circuitry, but some digital control signal to analog circuitry are turned off to avoid driving contention on the pads. w hen jtag ir contains extest or sample_p reload the clock is not sent out on the port pins even if the ckout fuse is programmed. even though the clock is output when the jtag ir contains sample_prelo ad, the clock is not sampled by the boundary scan. 312 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 132. boundary-scan cell for bi-directional port pin with pull-up function. dq dq g 0 1 0 1 dq dq g 0 1 0 1 0 1 port pin (pxn) vcc extest to next cell shiftdr output control (oc) output data (od) input data (id) from last cell updatedr clockdr ff1 ld1 ld0 ff0 0 1 pull-up enable (pue) 313 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 133. general port pin schematic diagram scanning the reset pin the reset pin accepts 5v active low logic for standard reset operation, and 12v active high logic for high voltage pa rallel programming. an observe-only cell as shown in fig- ure 134 is inserted for the 5v reset signal. figure 134. observe-only cell clk rpx rrx wrx rdx wdx pud synchronizer wdx: write ddrx wrx: write portx rrx: read portx register rpx: read portx pin pud: pullup disable clk : i/o clock rdx: read ddrx d l q q reset reset q q d q q d clr portxn q q d clr ddxn pinxn data bus sleep sleep: sleep control pxn i/o i/o see boundary-scan description for details! puexn ocxn odxn idxn puexn: pullup enable for pin pxn ocxn: output control for pin pxn odxn: output data to pin pxn idxn: input data from pin pxn 0 1 dq from previous cell clockdr shiftdr to next cell from system pin to system logic ff1 314 atmega640/1280/1281/2560/2561 2549k?avr?01/07 boundary-scan related register in i/o memory mcucr ? mcu control register the mcu control register contains control bits for general mcu functions. ? bits 7 ? jtd: jtag interface disable w hen this bit is zero, the jtag interface is enabled if the jtage n fuse is programmed. if this bit is one, the jtag interface is disabled. in order to avoid unintentional disabling or enabling of the jtag interface, a timed sequence must be followed when changing this bit: the application software must write this bit to the desired value twice within four cycles to change its value. n ote that this bit must not be altered when using the on-chip debug system. mcusr ? mcu status register the mcu status register provides information on which reset source caused an mcu reset. ? bit 4 ? jtrf: jtag reset flag this bit is set if a reset is being caus ed by a logic one in the jtag reset register selected by the jtag instru ction avr_reset. this bit is re set by a power-on reset, or by writing a logic zero to the flag. bit 76543210 0x35 (0x55) jtd ? ? pud ? ? ivsel ivce mcucr read/ w rite r/ w rrr/ w rrr/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x34 (0x54) ? ? ?jtrf wdrf borf extrf porf mcusr read/ w rite r r r r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 see bit description 315 atmega640/1280/1281/2560/2561 2549k?avr?01/07 atmega640/1280/1281/25 60/2561 boundary-scan order table 132 shows the scan order between td i and tdo when the boundary-scan chain is selected as data path. bit 0 is the lsb; the first bit scanned in, and the first bit scanned out. the scan order follows the pin-out order as far as possible. therefore, the bits of port a and port k is scanned in the opposite bit order of the other ports. excep- tions from the rules are the scan chains for the analog circuits, which constitute the most significant bits of the scan chain r egardless of which physical pin they are con- nected to. in figure 132, pxn. data corr esponds to ff0, pxn. control corresponds to ff1, pxn. bit 4, 5, 6 and 7 of port f is not in the scan chain, since these pins constitute the tap pins when the jtag is enabled. boundary-scan description language files boundary-scan description language (bsdl) files describe boundary-scan capable devices in a standard format used by automated test-generation software. the order and function of bits in the boundary-scan data register are included in this description. bsdl files are available for atmega1281/2561 and atmega640/1280/2560. table 132. atmega640/1280/2560 boundary-scan order bit number signal name module 164 pg5.data port g 163 pg5.control 162 pe0.data port e 161 pe0.control 160 pe1.data 159 pe1.control 158 pe2.data 157 pe2.control 156 pe3.data 155 pe3.control 154 pe4.data 153 pe4.control 152 pe5.data 151 pe5.control 150 pe6.data 149 pe6.control 148 pe7.data 147 pe7.control 146 ph0.data port h 145 ph0.control 144 ph1.data 143 ph1.control 142 ph2.data 141 ph2.control 316 atmega640/1280/1281/2560/2561 2549k?avr?01/07 140 ph3.data 139 ph3.control 138 ph4.data 137 ph4.control 136 ph5.data 135 ph5.control 134 ph6.data 133 ph6.control 132 pb0.data port b 131 pb0.control 130 pb1.data 129 pb1.control 128 pb2.data 127 pb2.control 126 pb3.data 125 pb3.control 124 pb4.data 123 pb4.control 122 pb5.data 121 pb5.control 120 pb6.data 119 pb6.control 118 pb7.data 117 pb7.control 116 ph7.data port h 115 ph7.control 114 pg3.data port g 113 pg3.control 112 pg4.data 111 pg4.control 110 rstt reset logic (observe only) 109 pl0.data port l 108 pl0.control 107 pl1.data 106 pl1.control 105 pl2.data table 132. atmega640/1280/2560 boundary-scan order (continued) bit number signal name module 317 atmega640/1280/1281/2560/2561 2549k?avr?01/07 104 pl2.control 103 pl3.data 102 pl3.control 101 pl4.data 100 pl4.control 99 pl5.data 98 pl5.control 97 pl6.data 96 pl6.control 95 pl7.data 94 pl7.control 93 pd0.data port d 92 pd0.control 91 pd1.data 90 pd1.control 89 pd2.data 88 pd2.control 87 pd3.data 86 pd3.control 85 pd4.data 84 pd4.control 83 pd5.data 82 pd5.control 81 pd6.data 80 pd6.control 79 pd7.data 78 pd7.control 77 pg0.data port g 76 pg0.control 75 pg1.data 74 pg1.control 73 pc0.data port c 72 pc0.control 71 pc1.data 70 pc1.control 69 pc2.data table 132. atmega640/1280/2560 boundary-scan order (continued) bit number signal name module 318 atmega640/1280/1281/2560/2561 2549k?avr?01/07 68 pc2.control 67 pc3.data 66 pc3.control 65 pc4.data 64 pc4.control 63 pc5.data 62 pc5.control 61 pc6.data 60 pc6.control 59 pc7.data 58 pc7.control 57 pj0.data port j 56 pj0.control 55 pj1.data 54 pj1.control 53 pj2.data 52 pj2.control 51 pj3.data 50 pj3.control 49 pj4.data 48 pj4.control 47 pj5.data 46 pj5.control 45 pj6.data 44 pj6.control 43 pg2.data port g 42 pg2.control 41 pa7.data port a 40 pa7.control 39 pa6.data 38 pa6.control 37 pa5.data 36 pa5.control 35 pa4.data 34 pa4.control 33 pa3.data table 132. atmega640/1280/2560 boundary-scan order (continued) bit number signal name module 319 atmega640/1280/1281/2560/2561 2549k?avr?01/07 32 pa3.control 31 pa2.data 30 pa2.control 29 pa1.data 28 pa1.control 27 pa0.data 26 pa0.control 25 pj7.data port j 24 pj7.control 23 pk7.data port k 22 pk7.control 21 pk6.data 20 pk6.control 19 pk5.data 18 pk5.control 17 pk4.data 16 pk4.control 15 pk3.data 14 pk3.control 13 pk2.data 12 pk2.control 11 pk1.data 10 pk1.control 9 pk0.data 8 pk0.control 7pf3.data port f 6 pf3.control 5pf2.data 4 pf2.control 3pf1.data 2 pf1.control 1pf0.data 0 pf0.control table 132. atmega640/1280/2560 boundary-scan order (continued) bit number signal name module 320 atmega640/1280/1281/2560/2561 2549k?avr?01/07 table 133. atmega1281/2561 boundary-scan order bit number signal name module 100 pg5.data port g 99 pg5.control 98 pe0.data port e 97 pe0.control 96 pe1.data 95 pe1.control 94 pe2.data 93 pe2.control 92 pe3.data 91 pe3.control 90 pe4.data 89 pe4.control 88 pe5.data 87 pe5.control 86 pe6.data 85 pe6.control 84 pe7.data 83 pe7.control 82 pb0.data port b 81 pb0.control 80 pb1.data 79 pb1.control 78 pb2.data 77 pb2.control 76 pb3.data 75 pb3.control 74 pb4.data 73 pb4.control 72 pb5.data 71 pb5.control 70 pb6.data 69 pb6.control 68 pb7.data 67 pb7.control 66 pg3.data port g 321 atmega640/1280/1281/2560/2561 2549k?avr?01/07 65 pg3.control 64 pg4.data 63 pg4.control 62 rstt reset logic (observe only) 61 pd0.data port d 60 pd0.control 59 pd1.data 58 pd1.control 57 pd2.data 56 pd2.control 55 pd3.data 54 pd3.control 53 pd4.data 52 pd4.control 51 pd5.data 50 pd5.control 49 pd6.data 48 pd6.control 47 pd7.data 46 pd7.control 45 pg0.data port g 44 pg0.control 43 pg1.data 42 pg1.control 41 pc0.data port c 40 pc0.control 39 pc1.data 38 pc1.control 37 pc2.data 36 pc2.control 35 pc3.data 34 pc3.control 33 pc4.data 32 pc4.control 31 pc5.data 30 pc5.control table 133. atmega1281/2561 boundary-scan order (continued) bit number signal name module 322 atmega640/1280/1281/2560/2561 2549k?avr?01/07 29 pc6.data 28 pc6.control 27 pc7.data 26 pc7.control 25 pg2.data port g 24 pg2.control 23 pa7.data port a 22 pa7.control 21 pa6.data 20 pa6.control 19 pa5.data 18 pa5.control 17 pa4.data 16 pa4.control 15 pa3.data 14 pa3.control 13 pa2.data 12 pa2.control 11 pa1.data 10 pa1.control 9pa0.data 8 pa0.control 7pf3.data port f 6 pf3.control 5pf2.data 4 pf2.control 3pf1.data 2 pf1.control 1pf0.data 0 pf0.control table 133. atmega1281/2561 boundary-scan order (continued) bit number signal name module 323 atmega640/1280/1281/2560/2561 2549k?avr?01/07 boot loader support ? read-while-write self-programming the boot loader support provides a real read- w hile- w rite self-programming mecha- nism for downloading and uploading program code by the mcu itself. this feature allows flexible application software updates controlled by the mc u using a flash-resi- dent boot loader program. the boot loader program can use any available data interface and associated protocol to read code and write (program) that code into the flash memory, or read the code from the program memory. the program code within the boot loader sectio n has the capability to write into the entire flash, including the boot loader memory. the boot loader can t hus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. the size of the boot loader memory is configurable with fuses and the boot loader has two separate sets of boot lock bits which can be se t independently. this gives th e user a unique flexibility to select different levels of protection. boot loader features ? read-while-write self-programming ? flexible boot memory size ? high security (separate boot lock bits for a flexible protection) ? separate fuse to select reset vector ? optimized page (1) size ? code efficien t algorithm ? efficient read-mod ify-write support n ote: 1. a page is a section in the flash consisting of several bytes (see table 155 on page 345) used during programming. the page organization does not affect normal operation. application and boot loader flash sections the flash memory is organized in two main sections, the application section and the boot loader section (see figure 136). the size of the different sections is configured by the bootsz fuses as shown in table 140 on page 335 and figure 136. these two sections can have different level of protection since they have different sets of lock bits. application section the application section is the section of the flash that is used for storing the application code. the protection level for the application section can be selected by the application boot lock bits (boot lock bits 0), see table 135 on page 327. the application section can never store any boot loader code since the spm instruction is disabled when exe- cuted from the application section. bls ? boot loader section w hile the application section is used for storing the application code, the the boot loader software must be located in the bls since the spm instruction can initiate a pro- gramming when executing from the bls only. the spm instruction can access the entire flash, including the bls itself. the protection level for the boot loader section can be selected by the boot loader lock bits (boot lock bits 1), see table 136 on page 327. read-while-write and no read-while-write flash sections w hether the cpu supports read- w hile- w rite or if the cpu is halted during a boot loader software update is dependent on which address that is being programmed. in addition to the two sections that are conf igurable by the bootsz fuses as described above, the flash is also divided into two fixed sections, the read- w hile- w rite (r ww ) section and the n o read- w hile- w rite ( n r ww ) section. the limit between the r ww - and n r ww sections is given in table 134 and figure 135 on page 325. the main differ- ence between the two sections is: ? w hen erasing or writing a page located inside the r ww section, the n r ww section can be read during the operation. 324 atmega640/1280/1281/2560/2561 2549k?avr?01/07 ? w hen erasing or writing a page located inside the n r ww section, the cpu is halted during the entire operation. n ote that the user software can never read any code that is located inside the r ww section during a boot loader software operation. the syntax ?read- w hile- w rite sec- tion? refers to which section that is being programmed (erased or written), not which section that actually is being read during a boot loader software update. rww ? read-while-write section if a boot loader software update is programming a page inside the r ww section, it is possible to read code from the flash, but only code that is located in the n r ww sec- tion. during an on-going programming, the software must ensure that the r ww section never is being read. if the user software is trying to read code that is located inside the r ww section (i.e., by load program memory, ca ll, or jump instruct ions or an interrupt) during programming, the software might end up in an unknown state. to avoid this, the interrupts should either be disabled or moved to the boot loader section. the boot loader section is always located in the n r ww section. the r ww section busy bit (r ww sb) in the store program memory contro l and status register (spmcsr) will be read as logical one as long as the r ww section is blocked for reading. after a program- ming is completed, the r ww sb must be cleared by software before reading code located in the r ww section. see ?spmcsr ? store program memory control and sta- tus register? on page 340. for details on how to clear r ww sb. nrww ? no read-while-write section the code located in the n r ww section can be read when the boot loader software is updating a page in the r ww section. w hen the boot loader code updates the n r ww section, the cpu is halted during the entire page erase or page w rite operation. table 134. read- w hile- w rite features which section does the z-pointer address during the programming? which section can be read during programming? cpu halted? read-while-write supported? r ww section n r ww section n oyes n r ww section n one yes n o 325 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 135. read- w hile- w rite vs. n o read- w hile- w rite read-while-write (rww) section no read-while-write (nrww) section z-pointer addresses rww section z-pointer addresses nrww section cpu is halted during the operation code located in nrww section can be read during the operation 326 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 136. memory sections n ote: 1. the parameters in the figure above are given in table 140 on page 335. boot loader lock bits if no boot loader ca pability is needed, the entire flash is availabl e for application code. the boot loader has two separate sets of boot lock bits which can be set indepen- dently. this gives the user a unique flexibility to select different le vels of protection. the user can select: ? to protect the entire flash from a software update by the mcu. ? to protect only the boot loader flash section from a software update by the mcu. ? to protect only the application flash sect ion from a software update by the mcu. ? allow software update in the entire flash. see table 135 and table 136 for further details . the boot lock bits can be set in soft- ware and in serial or parallel programming mode, but they can be cleared by a chip erase command only. the general w rite lock (lock bit mode 2) does not control the programming of the flash memory by spm instruction. similarly, the general read/ w rite lock (lock bit mode 1) does not control reading nor writing by (e)lpm/spm, if it is attempted. 0x0000 flashend program memory bootsz = '11' application flash section boot loader flash section flashend program memory bootsz = '10' 0x0000 program memory bootsz = '01' program memory bootsz = '00' application flash section boot loader flash section 0x0000 flashend application flash section flashend end rww start nrww application flash section boot loader flash section boot loader flash section end rww start nrww end rww start nrww 0x0000 end rww, end application start nrww, start boot loader application flash section application flash section application flash section read-while-write section no read-while-write section read-while-write section no read-while-write section read-while-write section no read-while-write section read-while-write section no read-while-write section end application start boot loader end application start boot loader end application start boot loader 327 atmega640/1280/1281/2560/2561 2549k?avr?01/07 n ote: 1. ?1? means unprogrammed, ?0? means programmed n ote: 1. ?1? means unprogrammed, ?0? means programmed entering the boot loader program entering the boot loader takes place by a jump or call from the application program. this may be initiated by a trigger such as a command received via usart, or spi inter- face. alternatively, the boot reset fuse can be programmed so that the reset vector is pointing to the boot flash start address after a reset. in this case, the boot loader is started after a reset. after the application code is loaded, the program can start execut- ing the application code. n ote that the fuses cannot be changed by the mcu itself. this means that once the boot reset fuse is programmed, the reset vector will always point to the boot loader reset and the fuse can only be changed through the serial or parallel programming interface. n ote: 1. ?1? means unprogrammed, ?0? means programmed table 135. boot lock bit0 protection modes (application section) (1) blb0 mode blb02 blb01 protection 111 n o restrictions for spm or (e)lpm accessing the application section. 2 1 0 spm is not allowed to write to the application section. 3 0 0 spm is not allowed to write to the application section, and (e)lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. 4 0 1 (e)lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. table 136. boot lock bit1 protection modes (boot loader section) (1) blb1 mode blb12 blb11 protection 111 n o restrictions for spm or (e)lpm accessing the boot loader section. 2 1 0 spm is not allowed to write to the boot loader section. 3 0 0 spm is not allowed to write to the boot loader section, and (e)lpm executing from t he application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. 4 0 1 (e)lpm executing from the application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. table 137. boot reset fuse (1) bootrst reset address 1 reset vector = application reset (address 0x0000) 0 reset vector = boot loader reset (see table 140 on page 335) 328 atmega640/1280/1281/2560/2561 2549k?avr?01/07 addressing the flash during self- programming the z-pointer is used to address the spm commands. the z pointer consists of the z- registers zl and zh in the register file, and rampz in the i/o space. the number of bits actually used is implementation dependent. n ote that the rampz register is only imple- mented when the program space is larger than 64k bytes. since the flash is organized in pages (see table 155 on page 345), the program counter can be treated as having two different sections. one section, consisting of the least significant bits, is addressing the wo rds within a page, while the most significant bits are addressing the pages. this is shown in figure 137. n ote that the page erase and page w rite operations are addressed independently. therefore it is of major impor- tance that the boot loader software addresses the same page in both the page erase and page w rite operation. once a programming operation is initiated, the address is latched and the z-pointer can be used for other operations. the (e)lpm instruction use the z-pointer to store the address. since this instruction addresses the flash byte-by-byte, also bit z0 of the z-pointer is used. figure 137. addressing the flash during spm (1) n ote: 1. the different variables used in figur e 137 are listed in table 142 on page 335. self-programming the flash the program memory is updated in a page by page fashion. before programming a page with the data stored in the temporary page buffer, the page must be erased. the temporary page buffer is filled one word at a time using spm and the buffer can be filled either before the page erase command or between a page erase and a page w rite operation: bit 2322212019181716 15 14 13 12 11 10 9 8 rampz rampz7 rampz6 rampz5 rampz4 rampz3 rampz2 rampz1 rampz0 zh (r31) z15 z14 z13 z12 z11 z10 z9 z8 zl (r30)z7z6z5z4z3z2z1z0 76543210 program memory 0 1 15 z - register bit 0 zpagemsb word address within a page page address within the flash zpcmsb instruction word pag e pcword[pagemsb:0]: 00 01 02 pageend pag e pcword pcpage pcmsb pagemsb program counter 329 atmega640/1280/1281/2560/2561 2549k?avr?01/07 alternative 1, fill the bu ffer before a page erase ? fill temporary page buffer ? perform a page erase ? perform a page w rite alternative 2, fill the bu ffer after page erase ? perform a page erase ? fill temporary page buffer ? perform a page w rite if only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary page buffer) before the erase, and then be rewritten. w hen using alternative 1, the boot loader provides an effective read-modify- w rite feature which allows the user software to first read the page, do the necessary changes, and then write back the modified data. if alternativ e 2 is used, it is not possible to read the old data while loading since the page is already erased. the temporary page buffer can be accessed in a random sequence. it is essential that the page address used in both the page erase and page w rite operation is addressing the same page. see ?simple assembly code example for a boot loader? on page 333 for an assembly code example. performing page erase by spm to execute page erase, set up the address in the z-pointer, write ?x0000011? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 and r0 is ignored. the page address must be written to pcpage in the z-register. other bits in the z-pointer will be ignored during this operation. ? page erase to the r ww section: the n r ww section can be read during the page erase. ? page erase to the n r ww section: the cpu is halted during the operation. filling the temporary buffer (page loading) to write an instruction word, set up the addre ss in the z-pointer and data in r1:r0, write ?00000001? to spmcsr and execute spm within four clock cycles after writing spmcsr. the content of pc w ord in the z-register is used to address the data in the temporary buffer. the temporary buffer will auto-erase after a page w rite operation or by writing the r ww sre bit in spmcsr. it is also erased after a system reset. n ote that it is not possible to write more than one time to each address without erasing the tempo- rary buffer. if the eeprom is written in th e middle of an spm page load operation, a ll data loaded is still buffered. performing a page write to execute page w rite, set up the address in the z-pointer, write ?x0000101? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 and r0 is ignored. the page address must be written to pcpage. other bits in the z-pointer must be written to zero during this operation. ? page w rite to the r ww section: the n r ww section can be read during the page w rite. ? page w rite to the n r ww section: the cpu is halted during the operation. using the spm interrupt if the spm interrupt is enabled, the spm interrupt will generate a constant interrupt when the spme n bit in spmcsr is cleared. this means that the interrupt can be used instead of polling the spmcs r register in software. w hen using the spm interrupt, the interrupt vectors should be moved to the bls section to avoid that an interrupt is 330 atmega640/1280/1281/2560/2561 2549k?avr?01/07 accessing the r ww section when it is blocked for reading. how to move the interrupts is described in ?interrupts? on page 69. consideration while updating bls special care must be taken if the user allows the boot loader section to be updated by leaving boot lock bit11 unprogrammed. an accidental write to the boot loader itself can corrupt the entire boot loader, and further software updates might be impossible. if it is not necessary to change the boot loader software itself, it is recommended to program the boot lock bit11 to protect the boot loader software from any internal software changes. prevent reading the rww section during self- programming during self-programming (either page erase or page w rite), the r ww section is always blocked for reading. the user software itself must prevent that this section is addressed during the self programming operation. the r ww sb in the spmcsr will be set as long as the r ww section is busy. during self-programming the interrupt vector table should be moved to the bls as described in ?interrupts? on page 69, or the inter- rupts must be disabled. before addressing the r ww section after the programming is completed, the user software must clear the r ww sb by writing the r ww sre. see ?simple assembly code example for a bo ot loader? on page 333 for an example. setting the boot loader lock bits by spm to set the boot loader lock bits and general lock bits, write the desired data to r0, write ?x0001001? to spmcsr and execute sp m within four clock cycles after writing spmcsr. see table 135 and table 136 for how the different settings of the boot loader bits affect the flash access. if bits 5:0 in r0 are cleared (zero), the corres ponding lock bit will be programmed if an spm instruction is executed within four cycles after blbset and spme n are set in spmcsr. the z-pointer is don?t care during this operation, but for future compatibility it is recommended to load the z-pointer with 0x0001 (same as used for reading the lo ck bits). for future compatibility it is also recommended to set bi ts 7 and 6 in r0 to ?1? when writing the lock bits. w hen programming the lock bits the entire flash can be read dur- ing the operation. eeprom write prevents writing to spmcsr n ote that an eeprom write operation will block all software programming to flash. reading the fuses and lock bits from software will al so be prevented during the eeprom write operation. it is recommended that th e user checks the status bit (eepe) in the eecr register and verifies that the bit is cleared before writing to the spmcsr register. bit 76543210 r0 1 1 blb12 blb11 blb02 blb01 lb2 lb1 331 atmega640/1280/1281/2560/2561 2549k?avr?01/07 reading the fuse and lock bits from software it is possible to read both the fuse and lock bits from software. to read the lock bits, load the z-pointer with 0x0001 and set the blbset and spme n bits in spmcsr. w hen an (e)lpm instruction is executed within three cpu cycles after the blbset and spme n bits are set in spmcsr, the value of t he lock bits will be loaded in the destina- tion register. th e blbset and spme n bits will auto-clear upon completion of reading the lock bits or if no (e)lpm instruction is executed within three cpu cycles or no spm instruction is executed within four cpu cycles. w hen blbset and spme n are cleared, (e)lpm will work as described in the instruction set manual. the algorithm for reading the fuse low byte is similar to the one described above for reading the lock bits. to read the fuse low byte, load the z-pointer with 0x0000 and set the blbset and spme n bits in spmcsr. w hen an (e)lpm instruction is executed within three cycles af ter the blbset and spme n bits are set in the spmcsr, the value of the fuse low byte (flb) will be loaded in the destination register as shown below. refer to table 153 on page 344 for a detailed description and mapping of the fuse low byte. similarly, when reading the fuse high byte, load 0x0003 in the z-pointer. w hen an (e)lpm instruction is executed within three cycles after the blbset and spme n bits are set in the spmcsr, the value of the fu se high byte (fhb) will be loaded in the des- tination register as shown below. refer to table 152 on page 344 for detailed description and mapping of the fuse high byte. w hen reading the extended fuse byte, load 0x0002 in the z-pointer. w hen an (e)lpm instruction is executed within three cycles a fter the blbset and spme n bits are set in the spmcsr, the value of the extended fuse byte (efb) will be loaded in the destina- tion register as shown below. refer to table 151 on page 343 for detailed description and mapping of the extended fuse byte. fuse and lock bits that are programmed, will be read as zero. fuse and lock bits that are unprogrammed, will be read as one. reading the signature row from software to read the signature row from software, load the z-pointer with the signature byte address given in table 138 on page 332 and set the sigrd and spme n bits in spmcsr. w hen an lpm instruction is executed within three cpu cycles after the sigrd and spme n bits are set in spmcsr, the si gnature byte valu e will be loaded in the destination register. the sigrd and spme n bits will auto-clear upon completion of reading the signature row lock bits or if no lpm instruction is executed within three bit 76543210 rd ? ? blb12 blb11 blb02 blb01 lb2 lb1 bit 76543210 rd flb7 flb6 flb5 flb4 flb3 flb2 flb1 flb0 bit 76543210 rd fhb7 fhb6 fhb5 fhb4 fhb3 fhb2 fhb1 fhb0 bit 76543210 rd ? ? ? ? ? efb2efb1efb0 332 atmega640/1280/1281/2560/2561 2549k?avr?01/07 cpu cycles. w hen sigrd and spme n are cleared, lpm will work as described in the instruction set manual. n ote: all other addresses are reserved for future use. preventing flash corruption during periods of low v cc , the flash program can be corrupted because the supply volt- age is too low for the cpu and the flash to operate properly. these issues are the same as for board level systems using the flash, and the same design solutions should be applied. a flash program corruption can be caused by two situations when the voltage is too low. first, a regular write sequence to the flash requires a minimum voltage to operate cor- rectly. secondly, the cpu itself can execute in structions incorrectly, if the supply voltage for executing instructions is too low. flash corruption can easily be avoided by following these design recommendations (one is sufficient): 1. if there is no need for a boot loade r update in the system, program the boot loader lock bits to prevent any boot loader software updates. 2. keep the avr reset active (low) during periods of insufficient power supply voltage. this can be done by enabling the internal brown-out detector (bod) if the operating voltage matches the detection level. if not, an external low v cc reset protection circuit can be used. if a reset occurs while a write operation is in progress, the write operation will be comp leted provided that the power supply voltage is sufficient. 3. keep the avr core in power-down sleep mode during periods of low v cc . this will prevent the cpu from attempting to de code and execute instructions, effec- tively protecting the spmcsr register and thus the flash from unintentional writes. programming time for flash when using spm the calibrated rc oscillator is used to time flash accesses. table 139 shows the typi- cal programming time for flash accesses from the cpu. table 138. signature row addressing signature byte z-pointer address device signature byte 1 0x0000 device signature byte 2 0x0002 device signature byte 3 0x0004 rc oscillator calibration byte 0x0001 table 139. spm programming time symbol min programming time max programming time flash write (page erase, page w rite, and write lock bits by spm) 3.7 ms 4.5 ms 333 atmega640/1280/1281/2560/2561 2549k?avr?01/07 simple assembly code example for a boot loader ;-the routine writes one page of data from ram to flash ; the first data location in ram is pointed to by the y pointer ; the first data location in flash is pointed to by the z-pointer ;-error handling is not included ;-the routine must be placed inside the boot space ; (at least the do_spm sub routine). only code inside nrww section can ; be read during self-programming (page erase and page write). ;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24), ; loophi (r25), spmcrval (r20) ; storing and restoring of registers is not included in the routine ; register usage can be optimized at the expense of code size ;-it is assumed that either the interrupt table is moved to the boot ; loader section or that the interrupts are disabled. .equ pagesizeb = pagesize*2 ;pagesizeb is page size in bytes, not words .org smallbootstart write_page: ; page erase ldi spmcrval, (1< 336 atmega640/1280/1281/2560/2561 2549k?avr?01/07 n otes: 1. z0: should be zero for all spm command s, byte select for t he (e)lpm instruction. 2. see ?addressing the flash during self-programming? on page 328 for details about the use of z-pointer during self-programming. atmega1280/1281 boot loader parameters in table 143 through table 144, the parameters used in the description of the self-pro- gramming are given. n ote: 1. the different bootsz fuse conf igurations are shown in figure 136. pagemsb 6 most significant bit which is used to address the words within one page (128 words in a page requires seven bits pc [6:0]). zpcmsb z15 bit in z-pointer that is mapped to pcmsb. because z0 is not used, the zpcmsb equals pcmsb + 1. zpagems b z7 bit in z-pointer that is mapped to pcmsb. because z0 is not used, the zpagemsb equals pagemsb + 1. pcpage pc[14:7] z15:z8 program counter page address: page select, for page erase and page w rite pc w ord pc[6:0] z7:z1 program counter word address: w ord select, for filling temporary buffer (must be zero during page w rite operation) table 142. explanation of different variables used in figure 137 and the mapping to the z-pointer, atmega640 variable corresponding z-value (2) description (1) table 143. boot size configuration, atmega1280/1281 (1) bootsz1 bootsz0 boot size pages appli-cation flash section boot loader flash section end application section boot reset address (start boot loader section) 11 512 words 4 0x0000 - 0xfdff 0xfe00 - 0xffff 0xfdff 0xfe00 10 1024 words 8 0x0000 - 0xfbff 0xfc00 - 0xffff 0xfbff 0xfc00 01 2048 words 16 0x0000 - 0xf7ff 0xf800 - 0xffff 0xf7ff 0xf800 00 4096 words 32 0x0000 - 0xefff 0xf000 - 0xffff 0xefff 0xf000 337 atmega640/1280/1281/2560/2561 2549k?avr?01/07 n ote: 1. for details about t hese two section, see ? n r ww ? n o read- w hile- w rite section? on page 324 and ?r ww ? read- w hile- w rite section? on page 324. n otes: 1. z0: should be zero for all spm command s, byte select for t he (e)lpm instruction. 2. see ?addressing the flash during self-programming? on page 328 for details about the use of z-pointer during self-programming. 3. the z-register is only 16 bits wide. bit 16 is located in the rampz register in the i/o map. table 144. read- w hile- w rite limit, atmega1280/1281 section (1) pages address read- w hile- w rite section (r ww ) 480 0x0000 - 0xefff n o read- w hile- w rite section ( n r ww ) 32 0xf000 - 0xffff table 145. explanation of different variables used in figure 137 and the mapping to the z-pointer, atmega1280/1281 variable corresponding z-value (2) description (1) pcmsb 15 most significant bit in the program counter. (the program counter is 16 bits pc[15:0]) pagemsb 6 most significant bit which is used to address the words within one page (128 words in a page requires seven bits pc [6:0]). zpcmsb z16 (3) bit in z-pointer that is mapped to pcmsb. because z0 is not used, the zpcmsb equals pcmsb + 1. zpagemsb z7 bit in z-pointer that is mapped to pcmsb. because z0 is not used, the zpagemsb equals pagemsb + 1. pcpage pc[15:7] z16 (3) :z8 program counter page address: page select, for page erase and page w rite pc w ord pc[6:0] z7:z1 program counter word address: w ord select, for filling temporary buffer (must be zero during page w rite operation) 338 atmega640/1280/1281/2560/2561 2549k?avr?01/07 atmega2560/2561 boot loader parameters in table 146 through table 148, the parameters used in the description of the self-pro- gramming are given. n ote: 1. the different bootsz fuse conf igurations are shown in figure 136. n ote: 1. for details about t hese two section, see ? n r ww ? n o read- w hile- w rite section? on page 324 and ?r ww ? read- w hile- w rite section? on page 324. table 146. boot size configuration, atmega2560/2561 (1) bootsz1 bootsz0 boot size pages appli-cation flash section boot loader flash section end application section boot reset address (start boot loader section) 11 512 words 4 0x00000 - 0x1fdff 0x1fe00 - 0x1ffff 0x1fdff 0x1fe00 10 1024 words 8 0x00000 - 0x1fbff 0x1fc00 - 0x1ffff 0x1fbff 0x1fc00 01 2048 words 16 0x00000 - 0x1f7ff 0x1f800 - 0x1ffff 0x1f7ff 0x1f800 00 4096 words 32 0x00000 - 0x1efff 0x1f000 - 0x1ffff 0x1efff 0x1f000 table 147. read- w hile- w rite limit, atmega2560/2561 section (1) pages address read- w hile- w rite section (r ww ) 992 0x00000 - 0x1efff n o read- w hile- w rite section ( n r ww ) 32 0x1f000 - 0x1ffff 339 atmega640/1280/1281/2560/2561 2549k?avr?01/07 n otes: 1. z0: should be zero for all spm command s, byte select for t he (e)lpm instruction. 2. see ?addressing the flash during self-programming? on page 328 for details about the use of z-pointer during self-programming. 3. the z-register is only 16 bits wide. bit 16 is located in the rampz register in the i/o map. table 148. explanation of different variables used in figure 137 and the mapping to the z-pointer, atmega2560/2561 variable corresponding z-value (2) description (1) pcmsb 16 most significant bit in the program counter. (the program counter is 17 bits pc[16:0]) pagemsb 6 most significant bit which is used to address the words within one page (128 words in a page requires seven bits pc [6:0]). zpcmsb z17:z16 (3) bit in z-pointer that is mapped to pcmsb. because z0 is not used, the zpcmsb equals pcmsb + 1. zpagemsb z7 bit in z-pointer that is mapped to pcmsb. because z0 is not used, the zpagemsb equals pagemsb + 1. pcpage pc[16:7] z17 (3) :z8 program counter page address: page select, for page erase and page w rite pc w ord pc[6:0] z7:z1 program counter word address: w ord select, for filling temporary buffer (must be zero during page w rite operation) 340 atmega640/1280/1281/2560/2561 2549k?avr?01/07 register description spmcsr ? store program memory control and status register the store program memory control and status register contains the control bits needed to control the boot loader operations. ? bit 7 ? spmie: spm interrupt enable w hen the spmie bit is written to one, and the i-bit in the status register is set (one), the spm ready interrupt will be enabled. the sp m ready interrupt will be executed as long as the spme n bit in the spmcsr register is cleared. ? bit 6 ? rwwsb: read-while-write section busy w hen a self-programming (page erase or page w rite) operation to the r ww section is initiated, the r ww sb will be set (one) by hardware. w hen the r ww sb bit is set, the r ww section cannot be accessed. the r ww sb bit will be cleared if the r ww sre bit is written to one after a self-programming operation is completed. alternatively the r ww sb bit will automatically be cleared if a page load operation is initiated. ? bit 5 ? sigrd: signature row read if this bit is written to one at the same time as spme n , the next lpm instruction within three clock cycles will read a byte from the signature row into the destination register. see ?reading the signature row from software? on page 331 for details. an spm instruction within four cycl es after sigrd and spme n are set will have no effect. this operation is reserved for future use and should not be used. ? bit 4 ? rwwsre: read-while-write section read enable w hen programming (page erase or page w rite) to the r ww section, the r ww section is blocked for reading (the r ww sb will be set by hardware). to re-enable the r ww section, the user software must wait until the programming is completed (spme n will be cleared). then, if the r ww sre bit is written to one at the same time as spme n , the next spm instruction within four clock cycles re-enables the r ww section. the r ww section cannot be re-enabled while the flash is busy with a page erase or a page w rite (spme n is set). if the r ww sre bit is written while the flash is being loaded, the flash load operation will abort and th e data loaded will be lost. ? bit 3 ? blbset: boot lock bit set if this bit is written to one at the same time as spme n , the next spm instruction within four clock cycles sets boot lock bits, acco rding to the data in r0. the data in r1 and the address in the z-pointer are ignored. the blbset bit will automatically be cleared upon completion of the lock bit set, or if no spm instruction is executed within four clock cycles. an (e)lpm instruction within three cycles after blbset and spme n are set in the spmcsr register, will read either the lock bits or the fuse bits (depending on z0 in the z-pointer) into the destination register. see ?reading the fuse and lock bits from software? on page 331 for details. bit 765 4 3 210 0x37 (0x57) spmie rwwsb sigrd rwwsre blbset pgwrt pgers spmen spmcsr read/ w rite r/ w rr/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 341 atmega640/1280/1281/2560/2561 2549k?avr?01/07 ? bit 2 ? pgwrt: page write if this bit is written to one at the same time as spme n , the next spm instruction within four clock cycles executes page w rite, with the data stored in the temporary buffer. the page address is taken from the high part of the z-pointer. the data in r1 and r0 are ignored. the pg w rt bit will auto-clear upon completion of a page w rite, or if no spm instruction is executed within four clock cycles. the cpu is halted during the entire page w rite operation if the n r ww section is addressed. ? bit 1 ? pgers: page erase if this bit is written to one at the same time as spme n , the next spm instruction within four clock cycles executes page erase. the page address is taken from the high part of the z-pointer. the data in r1 and r0 are ignored. the pg ers bit will auto-clear upon completion of a page erase, or if no spm instruction is executed within four clock cycles. the cpu is halted during the entire page w rite operation if the n r ww section is addressed. ? bit 0 ? spmen: store program memory enable this bit enables the spm instruction for the next four clock cycles. if written to one together with either r ww sre, blbset, pg w rt? or pgers, the following spm instruction will have a spec ial meaning, see description above. if only spme n is written, the following spm instruction will store the va lue in r1:r0 in the temporary page buffer addressed by the z-pointer. the lsb of the z-pointer is ignored. the spme n bit will auto-clear upon completion of an spm instruction, or if no spm instruction is executed within four clock cycles . during page erase and page w rite, the spme n bit remains high until the operation is completed. w riting any other combination than ?10001?, ?01001?, ?00101?, ?00011? or ?00001? in the lower five bits will have no effect. n ote: only one spm instruction should be active at any time. 342 atmega640/1280/1281/2560/2561 2549k?avr?01/07 memory programming program and data memory lock bits the atmega640/1280/1281/2560/2561 provides six lock bits which can be left unpro- grammed (?1?) or can be programmed (?0?) to obtain the additional features listed in table 150. the lock bits can only be erased to ?1? with the chip erase command. n ote: 1. ?1? means unprogrammed, ?0? means programmed table 149. lock bit byte (1) lock bit byte bit no de scription default value 7 ? 1 (unprogrammed) 6 ? 1 (unprogrammed) blb12 5 boot lock bit 1 (unprogrammed) blb11 4 boot lock bit 1 (unprogrammed) blb02 3 boot lock bit 1 (unprogrammed) blb01 2 boot lock bit 1 (unprogrammed) lb2 1 lock bit 1 (unprogrammed) lb1 0 lock bit 1 (unprogrammed) table 150. lock bit protection modes (1)(2) memory lock bits protection type lb mode lb2 lb1 111 n o memory lock features enabled. 210 further programming of the flash and eeprom is disabled in parallel and serial programming mode. the fuse bits are locked in both serial and parallel programming mode. (1) 300 further programming and verification of the flash and eeprom is disabled in parall el and serial programming mode. the boot lock bits and fuse bits are locked in both serial and parallel programming mode. (1) blb0 mode blb02 blb01 111 n o restrictions for spm or (e)lpm accessing the application section. 2 1 0 spm is not allowed to write to the application section. 300 spm is not allowed to write to the application section, and (e)lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. 401 (e)lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. 343 atmega640/1280/1281/2560/2561 2549k?avr?01/07 n otes: 1. program the fuse bits and boot lock bits before programming the lb1 and lb2. 2. ?1? means unprogrammed, ?0? means programmed fuse bits the atmega640/1280/1281/2560/2561 has three fuse bytes. table 151 - table 153 describe briefly the functionality of all the fuses and how they are mapped into the fuse bytes. n ote that the fuses are read as logical zero, ?0?, if they are programmed. n ote: 1. see table 27 on page 60 for bodlevel fuse decoding. blb1 mode blb12 blb11 111 n o restrictions for spm or (e)lpm accessing the boot loader section. 2 1 0 spm is not allowed to write to the boot loader section. 300 spm is not allowed to write to the boot loader section, and (e)lpm executing from t he application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. 401 (e)lpm executing from the application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. table 150. lock bit protection modes (1)(2) (continued) memory lock bits protection type table 151. extended fuse byte fuse low byte bit no description default value ?7? 1 ?6? 1 ?5? 1 ?4? 1 ?3? 1 bodlevel2 (1) 2 brown-out detector trigger level 1 (unprogrammed) bodlevel1 (1) 1 brown-out detector trigger level 1 (unprogrammed) bodlevel0 (1) 0 brown-out detector trigger level 1 (unprogrammed) 344 atmega640/1280/1281/2560/2561 2549k?avr?01/07 n ote: 1. the spie n fuse is not accessible in serial programming mode. 2. the default value of bootsz1:0 results in maximum boot size. see table 140 on page 335 for details. 3. see ? w dtcsr ? w atchdog timer control register? on page 66 for details. 4. n ever ship a product with the ocde n fuse programmed regardless of the setting of lock bits and jtage n fuse. a programmed ocde n fuse enables some parts of the clock system to be running in all sleep modes. this may increase the power consumption. n ote: 1. the default value of sut1:0 results in maximum start-up time for the default clock source. see table 26 on page 58 for details. 2. the default setting of cksel3:0 results in internal rc oscillator @ 8 mhz. see table 10 on page 39 for details. 3. the ckout fuse allow the system clock to be output on port e7. see ?clock out- put buffer? on page 46 for details. 4. see ?system clock prescaler? on page 47 for details. the status of the fuse bits is not affected by chip erase. n ote that the fuse bits are locked if lock bit1 (lb1) is programmed. program the fuse bits before programming the lock bits. table 152. fuse high byte fuse high byte bit no description default value ocde n (4) 7 enable ocd 1 (unprogrammed, ocd disabled) jtage n 6 enable jtag 0 (programmed, jtag enabled) spie n (1) 5 enable serial program and data downloading 0 (programmed, spi prog. enabled) w dto n (3) 4 w atchdog timer always on 1 (unprogrammed) eesave 3 eeprom memory is preserved through the chip erase 1 (unprogrammed, eeprom not preserved) bootsz1 2 select boot size (see table 157 for details) 0 (programmed) (2) bootsz0 1 select boot size (see table 157 for details) 0 (programmed) (2) bootrst 0 select reset vector 1 (unprogrammed) table 153. fuse low byte fuse low byte bit no description default value ckdiv8 (4) 7 divide clock by 8 0 (programmed) ckout (3) 6 clock output 1 (unprogrammed) sut1 5 select start-up time 1 (unprogrammed) (1) sut0 4 select start-up time 0 (programmed) (1) cksel3 3 select clock source 0 (programmed) (2) cksel2 2 select clock source 0 (programmed) (2) cksel1 1 select clock source 1 (unprogrammed) (2) cksel0 0 select clock source 0 (programmed) (2) 345 atmega640/1280/1281/2560/2561 2549k?avr?01/07 latching of fuses the fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves programming mode. this does not apply to the eesave fuse which will take effect once it is programmed. the fuses are also latched on power-up in n ormal mode. signature bytes all atmel microcontrollers have a three-byte signature code which identifies the device. this code can be read in both serial and parallel mode, also when the device is locked. the three bytes reside in a separate address space. for the atmega640/1280/1281/2560/2561 the signature bytes are given in table 154. calibration byte the atmega640/1280/1281/2560/2561 has a byte calibration value for the internal rc oscillator. this byte resides in the high byte of address 0x000 in the signature address space. during reset, this byte is automa tically written into the osccal register to ensure correct fre quency of the calibrated rc oscillator. page size parallel programming paramete rs, pin mapping, and commands this section describes how to parallel program and verify flash program memory, eeprom data memory, memory lock bits, and fuse bits in the atmega640/1280/1281/2560/2561. pulses are assumed to be at least 250 ns unless otherwise noted. signal names in this section, some pins of the atmega640/1280/1281/2560/2561 are referenced by signal names describing their functionality during parallel programming, see figure 138 and table 157. pins not described in the following table are referenced by pin names. the xa1/xa0 pins determine the action executed when the xtal1 pin is given a posi- tive pulse. the bit coding is shown in table 160. table 154. device and jtag id part signature bytes address jtag 0x000 0x001 0x002 part number manufacture id atmega640 0x1e 0x96 0x08 9608 0x1f atmega1280 0x1e 0x97 0x03 9703 0x1f atmega1281 0x1e 0x97 0x04 9704 0x1f atmega2560 0x1e 0x98 0x01 9801 0x1f atmega2561 0x1e 0x98 0x02 9802 0x1f table 155. n o. of w ords in a page and n o. of pages in the flash flash size page size pcword no. of pages pcpage pcmsb 128k words (256k bytes) 128 words pc[6:0] 1024 pc[16:7] 16 table 156. n o. of w ords in a page and n o. of pages in the eeprom eeprom size page size pcword no. of pages pcpage eeamsb 4k bytes 8 bytes eea[2:0] 512 eea[11:3] 11 346 atmega640/1280/1281/2560/2561 2549k?avr?01/07 w hen pulsing w r or oe , the command loaded determines the action executed. the dif- ferent commands are shown in table 161. figure 138. parallel programming (1) n ote: 1. unused pins should be left floating. table 157. pin n ame mapping signal name in programming mode pin name i/o function rdy/bsy pd1 o 0: device is busy programming, 1: device is ready for new command. oe pd2 i output enable (active low). w r pd3 i w rite pulse (active low). bs1 pd4 i byte select 1. xa0 pd5 i xtal action bit 0 xa1 pd6 i xtal action bit 1 pagel pd7 i program memory and eeprom data page load. bs2 pa0 i byte select 2. data pb7-0 i/o bi-directional data bus (output when oe is low). table 158. bs2 and bs1 encoding bs2 bs1 flash / eeprom address flash data loading / reading fuse programming reading fuse and lock bits 0 0 low byte low byte low byte fuse low byte vcc +5v gnd xtal1 pd1 pd2 pd3 pd4 pd5 pd6 pb7 - pb0 data reset pd7 +12 v bs1 xa0 xa1 oe rdy/bsy pagel pa0 wr bs2 avcc +5v 347 atmega640/1280/1281/2560/2561 2549k?avr?01/07 , 0 1 high byte high byte high byte lockbits 1 0 extended high byte reserved extended byte extended fuse byte 1 1 reserved reserved reserved fuse high byte table 159. pin values used to enter programming mode pin symbol value pagel prog_enable[3] 0 xa1 prog_enable[2] 0 xa0 prog_enable[1] 0 bs1 prog_enable[0] 0 table 160. xa1 and xa0 enoding xa1 xa0 action when xtal1 is pulsed 0 0 load flash or eeprom addre ss (high or low address byte determined by bs2 and bs1). 0 1 load data (high or low data byte for flash determined by bs1). 1 0 load command 11 n o action, idle table 161. command byte bit encoding command byte command executed 1000 0000 chip erase 0100 0000 w rite fuse bits 0010 0000 w rite lock bits 0001 0000 w rite flash 0001 0001 w rite eeprom 0000 1000 read signature bytes and calibration byte 0000 0100 read fuse and lock bits 0000 0010 read flash 0000 0011 read eeprom table 158. bs2 and bs1 encoding bs2 bs1 flash / eeprom address flash data loading / reading fuse programming reading fuse and lock bits 348 atmega640/1280/1281/2560/2561 2549k?avr?01/07 parallel programming enter programming mode the following algorithm puts the device in parallel programming mode: 1. apply 4.5 - 5.5v between v cc and g n d. 2. set reset to ?0? and toggle xtal1 at least six times. 3. set the prog_enable pins listed in table 159 on page 347 to ?0000? and wait at least 100 ns. 4. apply 11.5 - 12.5v to reset . any activity on prog_enable pins within 100 ns after +12v has been applied to reset , will cause the device to fail entering pro- gramming mode. 5. w ait at least 50 s before sending a new command. considerations for efficient programming the loaded command and address are retained in the device during programming. for efficient programming, the following should be considered. ? the command needs only be loaded once when writing or reading multiple memory locations. ? skip writing the data value 0xff, that is the contents of the entire eeprom (unless the eesave fuse is programmed) and flash after a chip erase. ? address high byte needs only be loaded before programming or reading a new 256 word window in flash or 256 byte eeprom . this consideration also applies to signature bytes reading. chip erase the chip erase will er ase the flash and eeprom (1) memories plus lock bits. the lock bits are not reset until the program memory has been completely erased. the fuse bits are not changed. a chip erase must be performed before the flash and/or eeprom are reprogrammed. n ote: 1. the eeprpom memory is preserved du ring chip erase if the eesave fuse is programmed. load command ?chip erase? 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?1000 0000?. this is the command for chip erase. 4. give xtal1 a positive pulse. this loads the command. 5. give w r a negative pulse. this starts the chip erase. rdy/bsy goes low. 6. w ait until rdy/bsy goes high before loading a new command. programming the flash the flash is organized in pages, see table 155 on page 345. w hen programming the flash, the program data is latched into a page buffer. this allows one page of program data to be programmed simultaneously. the following procedure describes how to pro- gram the entire flash memory: a. load command ? w rite flash? 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?0001 0000?. this is the command for w rite flash. 4. give xtal1 a positive pulse. this loads the command. b. load address low byte (address bits 7:0) 349 atmega640/1280/1281/2560/2561 2549k?avr?01/07 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs2, bs1 to ?00?. this selects the address low byte. 3. set data = address low byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the address low byte. c. load data low byte 1. set xa1, xa0 to ?01?. this enables data loading. 2. set data = data low byte (0x00 - 0xff). 3. give xtal1 a positive pulse. this loads the data byte. d. load data high byte 1. set bs1 to ?1?. this selects high data byte. 2. set xa1, xa0 to ?01?. this enables data loading. 3. set data = data high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the data byte. e. latch data 1. set bs1 to ?1?. this selects high data byte. 2. give pagel a positive pulse. this latches the data bytes. (see figure 140 for signal waveforms) f. repeat b through e until the entire buffer is filled or until all data within the page is loaded. w hile the lower bits in the address are mapped to words within the page, the higher bits address the pages with in the flash. this is illustrate d in figure 139 on page 350. n ote that if less than eight bits are required to address words in the page (pagesize < 256), the most significant bit(s) in the address low byte are used to address the page when performing a page w rite. g. load address high byte (address bits15:8) 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs2, bs1 to ?01?. this selects the address high byte. 3. set data = address high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the address high byte. h. load address extended high byte (address bits 23:16) 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs2, bs1 to ?10?. this selects the address extended high byte. 3. set data = address extended high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the address high byte. i. program page 1. set bs2, bs1 to ?00? 2. give w r a negative pulse. this starts programming of the entire page of data. rdy/bsy goes low. 3. w ait until rdy/bsy goes high (see figure 140 for signal waveforms). j. repeat b through i until the entire flash is programmed or until all data has been programmed. k. end page programming 350 atmega640/1280/1281/2560/2561 2549k?avr?01/07 1. 1. set xa1, xa0 to ?10?. this enables command loading. 2. set data to ?0000 0000?. this is the command for n o operation. 3. give xtal1 a positive pulse. this loads the command, and the internal write sig- nals are reset. figure 139. addressing the flash w hich is organized in pages (1) n ote: 1. pcpage and pc w ord are listed in table 155 on page 345. figure 140. programming the flash w aveforms (1) n ote: 1. ?xx? is don?t care. the letters refer to the programming description above. programming the eeprom the eeprom is organized in pages, see table 156 on page 345. w hen programming the eeprom, the program data is latched into a page buffer . this allows one page of data to be programmed simultaneously. the programming algorithm for the eeprom data memory is as follows (refer to ?programming the flash? on page 348 for details on command, address and data loading): program memory word address within a page page address within the flash instruction word pag e pcword[pagemsb:0]: 00 01 02 pageend pag e pcword pcpage pcmsb pagemsb program counter rdy/bsy wr oe reset +12v pagel bs2 0x10 addr. low addr. high data data low data high addr. low data low data high xa1 xa0 bs1 xtal1 xx xx xx abcdeb cdeg f addr. ext.h h i 351 atmega640/1280/1281/2560/2561 2549k?avr?01/07 1. a: load command ?0001 0001?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. c: load data (0x00 - 0xff). 5. e: latch data (give pagel a positive pulse). k: repeat 3 through 5 until the entire buffer is filled. l: program eeprom page 1. set bs2, bs1 to ?00?. 2. give w r a negative pulse. this starts programming of the eeprom page. rdy/bsy goes low. 3. w ait until to rdy/bsy goes high before programming the next page (see figure 141 for signal waveforms). figure 141. programming the eeprom w aveforms reading the flash the algorithm for reading the flash memory is as follows (refer to ?programming the flash? on page 348 for details on command and address loading): 1. a: load command ?0000 0010?. 2. h: load address extended byte (0x00- 0xff). 3. g: load address high byte (0x00 - 0xff). 4. b: load address low byte (0x00 - 0xff). 5. set oe to ?0?, and bs1 to ?0?. the flash word low byte can now be read at data. 6. set bs to ?1?. the flash word high byte can now be read at data. 7. set oe to ?1?. reading the eeprom the algorithm for readi ng the eeprom memory is as follows (refer to ?programming the flash? on page 348 for details on command and address loading): 1. a: load command ?0000 0011?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). rdy/bsy wr oe reset +12v pagel bs2 0x11 addr. high data addr. low data addr. low data xx xa1 xa0 bs1 xtal1 xx agbceb c el k 352 atmega640/1280/1281/2560/2561 2549k?avr?01/07 4. set oe to ?0?, and bs1 to ?0?. the eeprom data byte can now be read at data. 5. set oe to ?1?. programming the fuse low bits the algorithm for programming the fuse low bits is as follows (refer to ?programming the flash? on page 348 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. give w r a negative pulse and wait for rdy/bsy to go high. programming the fuse high bits the algorithm for programming the fuse high bits is as follows (refer to ?programming the flash? on page 348 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. set bs2, bs1 to ?01?. this selects high data byte. 4. give w r a negative pulse and wait for rdy/bsy to go high. 5. set bs2, bs1 to ?00?. this selects low data byte. programming the extended fuse bits the algorithm for programming the extended fuse bits is as follows (refer to ?program- ming the flash? on page 348 for details on command and data loading): 1. 1. a: load command ?0100 0000?. 2. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. 3. set bs2, bs1 to ?10?. this selects extended data byte. 4. 4. give w r a negative pulse and wait for rdy/bsy to go high. 5. 5. set bs2, bs1 to ?00?. this selects low data byte. figure 142. programming the fuses w aveforms rdy/bsy wr oe reset +12v pagel 0x40 data data xx xa1 xa0 bs1 xtal1 ac 0x40 data xx ac write fuse low byte write fuse high byte 0x40 data xx ac write extended fuse byte bs2 353 atmega640/1280/1281/2560/2561 2549k?avr?01/07 programming the lock bits the algorithm for programming the lock bits is as follows (refer to ?programming the flash? on page 348 for details on command and data loading): 1. a: load command ?0010 0000?. 2. c: load data low byte. bit n = ?0? programs the lock bit. if lb mode 3 is pro- grammed (lb1 and lb2 is programmed), it is not possible to program the boot lock bits by any external programming mode. 3. give w r a negative pulse and wait for rdy/bsy to go high. the lock bits can only be cleared by executing chip erase. reading the fuse and lock bits the algorithm for reading the fuse and lock bits is as follows (refer to ?programming the flash? on page 348 for details on command loading): 1. a: load command ?0000 0100?. 2. set oe to ?0?, and bs2, bs1 to ?00?. the status of the fuse low bits can now be read at data (?0? means programmed). 3. set oe to ?0?, and bs2, bs1 to ?11?. the status of the fuse high bits can now be read at data (?0? means programmed). 4. set oe to ?0?, and bs2, bs1 to ?10?. the status of the extended fuse bits can now be read at data (?0? means programmed). 5. set oe to ?0?, and bs2, bs1 to ?01?. the status of the lock bits can now be read at data (?0? means programmed). 6. set oe to ?1?. figure 143. mapping between bs1, bs2 and the fuse and lock bits during read reading the signature bytes the algorithm for reading the signature bytes is as follows (refer to ?programming the flash? on page 348 for details on command and address loading): 1. a: load command ?0000 1000?. 2. b: load address low byte (0x00 - 0x02). 3. set oe to ?0?, and bs to ?0?. the selected signature byte can now be read at data. 4. set oe to ?1?. lock bits 0 1 bs2 fuse high byte 0 1 bs1 data fuse low byte 0 1 bs2 extended fuse byte 354 atmega640/1280/1281/2560/2561 2549k?avr?01/07 reading the calibration byte the algorithm for reading the calibration byte is as follows (refer to ?programming the flash? on page 348 for details on command and address loading): 1. a: load command ?0000 1000?. 2. b: load address low byte, 0x00. 3. set oe to ?0?, and bs1 to ?1?. the calibration byte can now be read at data. 4. set oe to ?1?. parallel programming characteristics figure 144. parallel programming timing, including some general timing requirements figure 145. parallel programming timing, loading sequence with timing requirements (1) n ote: 1. the timing requirements shown in figure 144 (i.e., t dvxh , t xhxl , and t xldx ) also apply to loading operation. data & contol (data, xa0/1, bs1, bs2) xtal1 t xhxl t wlwh t dvxh t xldx t plwl t wlrh wr rdy/bsy pagel t phpl t plbx t bvph t xlwl t wlbx t bvwl wlrl xtal1 pagel t plxh xlxh t t xlph addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data bs1 xa0 xa1 load address (low byte) load data (low byte) load data (high byte) load data load address (low byte) 355 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 146. parallel programming timing, reading sequence (within the same page) with timing requirements (1) n ote: 1. the timing requirements shown in figure 144 (i.e., t dvxh , t xhxl , and t xldx ) also apply to reading operation. table 162. parallel programming characteristics, v cc = 5v 10% symbol parameter min typ max units v pp programming enable voltage 11.5 12.5 v i pp programming enable current 250 a t dvxh data and control valid before xtal1 high 67 ns t xlxh xtal1 low to xtal1 high 200 ns t xhxl xtal1 pulse w idth high 150 ns t xldx data and control hold after xtal1 low 67 ns t xl w l xtal1 low to w r low 0 ns t xlph xtal1 low to pagel high 0 ns t plxh pagel low to xtal1 high 150 ns t bvph bs1 valid before pagel high 67 ns t phpl pag e l p u l s e w idth high 150 ns t plbx bs1 hold after pagel low 67 ns t w lbx bs2/1 hold after w r low 67 ns t pl w l pagel low to w r low 67 ns t bv w l bs2/1 valid to w r low 67 ns t w l w h w r pulse w idth low 150 ns t w lrl w r low to rdy/bsy low 0 1 s t w lrh w r low to rdy/bsy high (1) 3.7 4.5 ms t w lrh_ce w r low to rdy/bsy high for chip erase (2) 7.5 9 ms t xlol xtal1 low to oe low 0 ns xtal1 oe addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data bs1 xa0 xa1 load address (low byte) read data (low byte) read data (high byte) load address (low byte) t bvdv t oldv t xlol t ohdz 356 atmega640/1280/1281/2560/2561 2549k?avr?01/07 n otes: 1. t w lrh is valid for the w rite flash, w rite eeprom, w rite fuse bits and w rite lock bits commands. 2. t w lrh_ce is valid for the chip erase command. serial downloading both the flash and eeprom memory arrays ca n be programmed usin g a serial pro- gramming bus while reset is pulled to g n d. the serial programming interface consists of pins sck, pdi (in put) and pdo (output). after reset is set low, the pro- gramming enable instruction needs to be executed first before program/erase operations can be executed. n ote, in table 163 on page 356, the pin mapping for serial programming is listed. n ot all packages use the spi pins dedicated for the internal serial peripheral interface - spi. serial programming pin mapping figure 147. serial programming and verify (1) n otes: 1. if the device is clocked by the internal oscillator, it is no need to connect a clock source to the xtal1 pin. 2. v cc - 0.3v < avcc < v cc + 0.3v, however, avcc should always be within 1.8 - 5.5v t bvdv bs1 valid to data valid 0 250 ns t oldv oe low to data valid 250 ns t ohdz oe high to data tri-stated 250 ns table 162. parallel programming characteristics, v cc = 5v 10% (continued) symbol parameter min typ max units table 163. pin mapping serial programming symbol pins (tqfp-100) pins (tqfp-64) i/o description pdi pb2 pe0 i serial data in pdo pb3 pe1 o serial data out sck pb1 pb1 i serial clock vcc g n d xtal1 sck pdo pdi reset +1.8 - 5.5v avcc +1.8 - 5.5v (2) 357 atmega640/1280/1281/2560/2561 2549k?avr?01/07 w hen programming the eeprom, an auto-erase cycle is built into the self-timed pro- gramming operation (in the serial mode o n ly) and there is no need to first execute the chip erase instruction. the chip erase operation turns the content of every memory location in both the program and eeprom arrays into 0xff. depending on cksel fuses, a valid clock must be present. the minimum low and high periods for the serial clock (sck) input are defined as follows: low:> 2 cpu clock cycles for f ck < 12 mhz, 3 cpu clock cycles for f ck >= 12 mhz high:> 2 cpu clock cycles for f ck < 12 mhz, 3 cpu clock cycles for f ck >= 12 mhz serial programming algorithm w hen writing serial data to the atmega640/1280/1281/2560/2561, data is clocked on the rising edge of sck. w hen reading data from the atmega640/1280/1281/2560/2561, data is clocked on the falling edge of sck. see figu re 149 for timing details. to program and verify the atmega640/1280/1281/2560/2561 in the serial programming mode, the following sequence is recommended (see four byte instruction formats in table 165 on page 359 ): 1. power-up sequence: apply power between v cc and g n d while reset and sck are set to ?0?. in some systems, the programmer can not guarantee that sck is held low during power-up. in this case, reset must be given a positive pulse of at least two cpu clock cycles duration after sck has been set to ?0?. 2. w ait for at least 20 ms and enable serial programming by sending the program- ming enable serial instruction to pin pdi. 3. the serial programming instructions will not work if the communication is out of synchronization. w hen in sync. the second by te (0x53), will echo back when issuing the third byte of the programming enable instruction. w hether the echo is correct or not, all four bytes of the instruction must be transmitted. if the 0x53 did not echo back, give reset a positive pulse and issue a new programming enable command. 4. the flash is programmed one page at a time. the memory page is loaded one byte at a time by supplying the 7 lsb of the address and data together with the load program memory page instruction. to ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. the program memory page is stored by loading the w rite program memory page instruction with the addre ss lines 15:8. before issuing this com- mand, make sure the instruction load extended address byte has been used to define the msb of the address. the extended address byte is stored until the command is re-issued, i.e., the command needs only be issued for the first page, and when crossing the 64k w ord boundary. if polling ( rdy/bsy ) is not used, the user must wait at least t w d_flash before issuing the next page. (see table 164.) accessing the serial programming interface before the flash write operation completes can result in incorrect programming. 5. the eeprom array is programmed one byte at a time by supplying the address and data together with the appropriate w rite instruction. an eeprom memory location is first automatically erased bef ore new data is written. if polling is not used, the user must wait at least t w d_eeprom before issuing the next byte. (see table 164.) in a chip erased device, no 0xffs in the data file(s) need to be programmed. 6. any memory location can be verified by using the read instruction which returns the content at the selected address at serial output pdo. w hen reading the 358 atmega640/1280/1281/2560/2561 2549k?avr?01/07 flash memory, use the instruction load extended address byte to define the upper address byte, which is not included in the read program memory instruc- tion. the extended address byte is stored until the command is re-issued, i.e., the command needs only be issued for the first page, and when crossing the 64k w ord boundary. 7. at the end of the programming session, reset can be set high to commence normal operation. 8. power-off sequence (if needed): set reset to ?1?. tu r n v cc power off. table 164. minimum w ait delay before w riting the n ext flash or eeprom location symbol minimum wait delay t w d_flash 4.5 ms t w d_eeprom 9.0 ms t w d_erase 9.0 ms 359 atmega640/1280/1281/2560/2561 2549k?avr?01/07 serial programming instruction set table 165 on page 359 and figure 148 on page 360 describes the instruction set. n otes: 1. n ot all instructions are applicable for all parts. 2. a = address. 3. bits are programmed ?0?, unprogrammed ?1?. 4. to ensure future compatibility, unused fuses and lock bits should be unprogrammed (?1?) . 5. refer to the correspondig section for fuse and lock bits, calibration and signature bytes and page size. 6. see htt://www.atmel.com/avr for application n otes regarding programming and programmers. table 165. serial programmin g instruction set instruction/operation instruction format byte 1 byte 2 byte 3 byte4 programming enable $ac $53 $00 $00 chip erase (program memory/eeprom) $ac $80 $00 $00 poll rdy/bsy $f0 $00 $00 data byte out load instructions load extended address byte (1) $4d $00 extended adr $00 load program memory page, high byte $48 $00 adr lsb high data byte in load program memory page, low byte $40 $00 adr lsb low data byte in load eeprom memory page (page access) $c1 $00 0000 000aa data byte in read instructions read program memory, high byte $28 adr msb adr lsb high data byte out read program memory, low byte $20 adr msb adr lsb low data byte out read eeprom memory $a0 0000 aaaa aaaa aaaa data byte out read lock bits $58 $00 $00 data byte out read signature byte $30 $00 0000 000aa data byte out read fuse bits $50 $00 $00 data byte out read fuse high bits $58 $08 $00 data byte out read extended fuse bits $50 $08 $00 data byte out read calibration byte $38 $00 $00 data byte out write instructions w rite program memory page $4c adr msb adr lsb $00 w rite eeprom memory $c0 0000 aaaa aaaa aaaa data byte in w rite eeprom memory page (page access) $c2 0000 aaaa aaaa 00 $00 w rite lock bits $ac $e0 $00 data byte in w rite fuse bits $ac $a0 $00 data byte in w rite fuse high bits $ac $a8 $00 data byte in w rite extended fuse bits $ac $a4 $00 data byte in 360 atmega640/1280/1281/2560/2561 2549k?avr?01/07 if the lsb in rdy/bsy data byte out is ?1?, a programming operation is still pending. w ait until this bit returns ?0? before the next instruction is carried out. w ithin the same page, the low data byte must be loaded prior to the high data byte. after data is loaded to t he page buffer, program the eepr om page, see figure 148 on page 360. figure 148. serial programming instruction example serial programming characteristics for characteristics of the serial progra mming module see ?spi ti ming characteristics? on page 380. figure 149. serial programming w aveforms byte 1 byte 2 byte 3 byte 4 adr lsb bit 15 b 0 serial programming instruction program memory/ eeprom memory page 0 page 1 page 2 page n-1 page buffer write program memory page/ write eeprom memory page load program memory page (high/low byte)/ load eeprom memory page (page access) byte 1 byte 2 byte 3 byte 4 bit 15 b 0 adr msb page offset page number ad r m ms sb a a adr r l lsb b msb msb lsb lsb serial clock input (sck) serial data input (mosi) (miso) sample serial data output 361 atmega640/1280/1281/2560/2561 2549k?avr?01/07 programming via the jtag interface programming through the jtag interface requires control of the four jtag specific pins: tck, tms, tdi, and tdo. control of the reset and clock pins is not required. to be able to use the jtag interface, the jtage n fuse must be programmed. the device is default shipped with the fuse programmed. in addition, the jtd bit in mcucr must be cleared. alternatively, if the jtd bit is set, the external reset can be forced low. then, the jtd bit will be cleared after two chip clocks, and the jtag pins are available for programming. this provides a means of us ing the jtag pins as normal port pins in running mode while still allowing in-system programming via the jtag interface. n ote that this technique can not be used when us ing the jtag pins for boundary-scan or on- chip debug. in these cases the jtag pins must be dedicated for this purpose. during programming the clock frequency of the tck input must be less than the maxi- mum frequency of the chip. the system clock prescaler can not be used to divide the tck clock input into a sufficiently low frequency. as a definition in this datasheet, the lsb is shifted in and out first of all shift registers. programming specific jtag instructions the instruction register is 4-bit wide, supporting up to 16 instructions. the jtag instructions useful for programming are listed below. the opcode for each instruction is shown behind the instruction name in hex format. the text describes which data register is selected as path between tdi and tdo for each instruction. the run-test/idle state of the tap controller is used to generate internal clocks. it can also be used as an idle state between jtag sequences. the state machine sequence for changing the instruction word is shown in figure 150. 362 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 150. state machine sequence for changing the instruction w ord avr_reset (0xc) the avr specific public jtag instruction for setting the avr device in the reset mode or taking the device out from the reset mode. the tap controller is not reset by this instruction. the one bit reset register is selected as data register. n ote that the reset will be active as long as there is a logic ?o ne? in the reset chain. the output from this chain is not latched. the active states are: ? shift-dr: the reset register is shifted by the tck input. prog_enable (0x4) the avr specific public jtag instruction for enabling programming via the jtag port. the 16-bit programming enable register is selected as data register. the active states are the following: ? shift-dr: the programming enable signature is shifted into the data register. ? update-dr: the programming enable signature is compared to the correct value, and programming mode is entered if the signature is valid. test-logic-reset run-test/idle shift-dr exit1-dr pause-dr exit2-dr update-dr select-ir scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select-dr scan capture-dr 0 1 0 11 1 00 00 11 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 1 1 363 atmega640/1280/1281/2560/2561 2549k?avr?01/07 prog_commands (0x5) the avr specific public jtag instruction for entering programming commands via the jtag port. the 15-bit programming command register is selected as data register. the active states are the following: ? capture-dr: the result of the previous command is loaded into the data register. ? shift-dr: the data register is shifted by the tck input, shifting out the result of the previous command and shifting in the new command. ? update-dr: the programming command is applied to the flash inputs ? run-test/idle: one clock cycle is generated, executing the applied command prog_pageload (0x6) the avr specific public jtag instruction to directly load the flash data page via the jtag port. an 8-bit flash data byte register is selected as the data register. this is physically the 8 lsbs of the programming command register. the active states are the following: ? shift-dr: the flash data byte register is shifted by the tck input. ? update-dr: the content of the flash data byte register is copied into a temporary register. a write sequence is initiated that within 11 tck cycles loads the content of the temporary register into the flash page buffer. the avr automatically alternates between writing the low and the high byte for each new update-dr state, starting with the low byte for the first update-dr encountered after entering the prog_pageload command. the program counter is pre-incremented before writing the low byte, except for the first written byte. this ensures that the first data is written to the address set up by prog_comma n ds, and loading the last location in the page buffer does not make the program counter increment into the next page. prog_pageread (0x7) the avr specific public jtag instruction to directly capture the flash content via the jtag port. an 8-bit flash data byte register is selected as the data register. this is physically the 8 lsbs of the programming command register. the active states are the following: ? capture-dr: the content of the selected flash byte is captured into the flash data byte register. the avr automatically alternates between reading the low and the high byte for each new capture-dr state, starting with the low byte for the first capture-dr encountered after entering the prog_pageread command. the program counter is post-incremented after reading each high byte, including the first read byte. this ensures that the first data is captured from the first address set up by prog_comma n ds, and reading the last location in the page makes the program counter increment into the next page. ? shift-dr: the flash data byte register is shifted by the tck input. data registers the data registers are selected by the jtag instruction registers described in section ?programming specific jtag instructions? on page 361. the data registers relevant for programming operations are: ? reset register ? programming enable register ? programming command register ? flash data byte register 364 atmega640/1280/1281/2560/2561 2549k?avr?01/07 reset register the reset register is a test data register used to reset the part during programming. it is required to reset the part before entering programming mode. a high value in the reset register corresponds to pulling the external reset low. the part is reset as long as there is a high value present in the reset register. depending on the fuse settings for the clock options, the part will remain rese t for a reset time-out period (refer to ?clock sources? on page 39) after releasing the reset register. the out- put from this data register is not latched, so the reset will take place immediately, as shown in figure 131 on page 309. programming enable register the programming enable register is a 16-bit register. the contents of this register is compared to the programming enable signature, binary code 0b1010_0011_0111_0000. w hen the contents of the register is equal to the program- ming enable signature, programming via the jtag port is enabled. the register is reset to 0 on power-on reset, and should always be reset when leaving programming mode. figure 151. programming enable register programming command register the programming command register is a 15-bit register. this register is used to seri- ally shift in programming commands, and to serially shift out the result of the previous command, if any. the jtag programming instruction set is shown in table 166. the state sequence when shifting in the programming commands is illustrate d in figure 153. tdi tdo d a t a = dq clockdr & prog_enable programming enable 0xa370 365 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 152. programming command register tdi tdo s t r o b e s a d d r e s s / d a t a flash eeprom fuses lock bits 366 atmega640/1280/1281/2560/2561 2549k?avr?01/07 table 166. jtag programming instruction set a = address high bits, b = address low bits, c = address extended bits, h = 0 - low byte, 1 - high byte, o = data out, i = data in, x = don?t care instruction tdi sequence tdo sequence notes 1a. chip erase 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b. poll for chip erase complete 0110011_10000000 xxxxx o x_xxxxxxxx (2) 2a. enter flash w rite 0100011_00010000 xxxxxxx_xxxxxxxx 2b. load address extended high byte 0001011_ cccccccc xxxxxxx_xxxxxxxx (10) 2c. load address high byte 0000111_ aaaaaaaa xxxxxxx_xxxxxxxx 2d. load address low byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 2e. load data low byte 0010011_ iiiiiiii xxxxxxx_xxxxxxxx 2f. load data high byte 0010111_ iiiiiiii xxxxxxx_xxxxxxxx 2g. latch data 0110111_00000000 1110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 2h. w rite flash page 0110111_00000000 0110101_00000000 0110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 2i. poll for page w rite complete 0110111_00000000 xxxxx o x_xxxxxxxx (2) 3a. enter flash read 0100011_00000010 xxxxxxx_xxxxxxxx 3b. load address extended high byte 0001011_ cccccccc xxxxxxx_xxxxxxxx (10) 3c. load address high byte 0000111_ aaaaaaaa xxxxxxx_xxxxxxxx 3d. load address low byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 3e. read data low and high byte 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo xxxxxxx_ oooooooo low byte high byte 4a. enter eeprom w rite 0100011_00010001 xxxxxxx_xxxxxxxx 4b. load address high byte 0000111_ aaaaaaaa xxxxxxx_xxxxxxxx (10) 4c. load address low byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 4d. load data byte 0010011_ iiiiiiii xxxxxxx_xxxxxxxx 4e. latch data 0110111_00000000 1110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 4f. w rite eeprom page 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 367 atmega640/1280/1281/2560/2561 2549k?avr?01/07 4g. poll for page w rite complete 0110011_00000000 xxxxx o x_xxxxxxxx (2) 5a. enter eeprom read 0100011_00000011 xxxxxxx_xxxxxxxx 5b. load address high byte 0000111_ aaaaaaaa xxxxxxx_xxxxxxxx (10) 5c. load address low byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 5d. read data byte 0110011_ bbbbbbbb 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 6a. enter fuse w rite 0100011_01000000 xxxxxxx_xxxxxxxx 6b. load data low byte (6) 0010011_ iiiiiiii xxxxxxx_xxxxxxxx (3) 6c. w rite fuse extended byte 0111011_00000000 0111001_00000000 0111011_00000000 0111011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 6d. poll for fuse w rite complete 0110111_00000000 xxxxx o x_xxxxxxxx (2) 6e. load data low byte (7) 0010011_ iiiiiiii xxxxxxx_xxxxxxxx (3) 6f. w rite fuse high byte 0110111_00000000 0110101_00000000 0110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 6g. poll for fuse w rite complete 0110111_00000000 xxxxx o x_xxxxxxxx (2) 6h. load data low byte (7) 0010011_ iiiiiiii xxxxxxx_xxxxxxxx (3) 6i. w rite fuse low byte 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 6j. poll for fuse w rite complete 0110011_00000000 xxxxx o x_xxxxxxxx (2) 7a. enter lock bit w rite 0100011_00100000 xxxxxxx_xxxxxxxx 7b. load data byte (9) 0010011_11 iiiiii xxxxxxx_xxxxxxxx (4) 7c. w rite lock bits 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 7d. poll for lock bit w rite complete 0110011_00000000 xxxxx o x_xxxxxxxx (2) 8a. enter fuse/lock bit read 0100011_00000100 xxxxxxx_xxxxxxxx 8b. read extended fuse byte (6) 0111010_00000000 0111011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 8c. read fuse high byte (7) 0111110_00000000 0111111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo table 166. jtag programming instruction (continued) set (continued) a = address high bits, b = address low bits, c = address extended bits, h = 0 - low byte, 1 - high byte, o = data out, i = data in, x = don?t care instruction tdi sequence tdo sequence notes 368 atmega640/1280/1281/2560/2561 2549k?avr?01/07 n otes: 1. this command sequence is not requir ed if the seven msb are correctly set by the previous command sequence (which is normally the case). 2. repeat until o = ?1?. 3. set bits to ?0? to program the corresponding fuse, ?1? to unprogram the fuse. 4. set bits to ?0? to program the corresponding lock bit, ?1? to leave the lock bit unchanged. 5. ?0? = programmed, ?1? = unprogrammed. 6. the bit mapping for fuses extended byte is listed in table 151 on page 343 7. the bit mapping for fuses high byte is listed in table 152 on page 344 8. the bit mapping for fuses low byte is listed in table 153 on page 344 9. the bit mapping for lock bits byte is listed in table 149 on page 342 10. address bits exceeding pcmsb and eeamsb (table 155 and table 156) are don?t care 11. all tdi and tdo sequences are represented by binary digits (0b...). 8d. read fuse low byte (8) 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 8e. read lock bits (9) 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xx oooooo (5) 8f. read fuses and lock bits 0111010_00000000 0111110_00000000 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo xxxxxxx_ oooooooo xxxxxxx_ oooooooo xxxxxxx_ oooooooo (5) fuse ext. byte fuse high byte fuse low byte lock bits 9a. enter signature byte read 0100011_00001000 xxxxxxx_xxxxxxxx 9b. load address byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 9c. read signature byte 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 10a. enter calibration byte read 0100011_00001000 xxxxxxx_xxxxxxxx 10b. load address byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 10c. read calibration byte 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 11a. load n o operation command 0100011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx table 166. jtag programming instruction (continued) set (continued) a = address high bits, b = address low bits, c = address extended bits, h = 0 - low byte, 1 - high byte, o = data out, i = data in, x = don?t care instruction tdi sequence tdo sequence notes 369 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 153. state machine sequence for changing/reading the data w ord flash data byte register the flash data byte register provides an efficient way to load the entire flash page buffer before executing page w rite, or to read out/verify the content of the flash. a state machine sets up the control signals to the fl ash and senses the strobe signals from the flash, thus only the data words need to be shifted in/out. the flash data byte register actually consists of the 8-bi t scan chain and a 8-bit tempo- rary register. during page load, the update-dr state copies the content of the scan chain over to the temporary register and initiates a write sequence that within 11 tck cycles loads the content of the temporary register into the flash page buffer. the avr automatically alternates between writing the low and the high byte for each new update- dr state, starting with the low byte for the first update-dr encountered after entering the prog_pageload command. the program counter is pre-incremented before writing the low byte, except for the first written byte. this ensures that the first data is written to the address set up by prog_comma n ds, and loading the last location in the page buffer does not make the program counter increment into the next page. during page read, the content of the selected flash byte is captured into the flash data byte register during the capture-dr state. the avr automatically alternates between reading the low and the high byte for each new capture-dr state, starting with the low byte for the first capture-dr encountered after entering the prog_pageread command. the program counter is post-incremented after reading each high byte, test-logic-reset run-test/idle shift-dr exit1-dr pause-dr exit2-dr update-dr select-ir scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select-dr scan capture-dr 0 1 0 11 1 00 00 11 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 1 1 370 atmega640/1280/1281/2560/2561 2549k?avr?01/07 including the first read byte. this ensures that the first data is captured from the first address set up by prog_comma n ds, and reading the last location in the page makes the program counter increment into the next page. figure 154. flash data byte register the state machine controlling th e flash data byte register is clocked by tck. during normal operation in wh ich eight bits are shifted for each flash byte, the clock cycles needed to navigate through the tap controller automatically feeds the state machine for the flash data byte register with sufficient number of clock pulses to complete its oper- ation transparently for the user. however, if too few bits are shifted between each update-dr state during page load, the tap controller should stay in the run-test/idle state for some tck cycles to en sure that there are at least 11 tck cycles between each update-dr state. programming algorithm all references below of type ?1a?, ?1b?, and so on, refer to table 166. entering programming mode 1. enter jtag instruction avr_reset and shift 1 in the reset register. 2. enter instruction prog_e n able and shift 0b1010_0011_0111_0000 in the programming enable register. leaving programming mode 1. enter jtag instruction prog_comma n ds. 2. disable all programming instructions by using no operation instruction 11a. 3. enter instruction prog_e n able and shift 0b0000_0000_0000_0000 in the programming enable register. 4. enter jtag instruction avr_reset and shift 0 in the reset register. performing chip erase 1. enter jtag instruction prog_comma n ds. 2. start chip erase using pr ogramming instruction 1a. 3. poll for chip erase complete using pr ogramming instruction 1b, or wait for t w lrh_ce (refer to table 162 on page 355). tdi tdo d a t a flash eeprom fuses lock bits strobes address state machine 371 atmega640/1280/1281/2560/2561 2549k?avr?01/07 programming the flash before programming the flash a chip erase must be performed, see ?performing chip erase? on page 370. 1. enter jtag instruction prog_comma n ds. 2. enable flash write using programming instruction 2a. 3. load address extended high byte using programming instruction 2b. 4. load address high byte using programming instruction 2c. 5. load address low byte using programming instruction 2d. 6. load data using programming instructions 2e, 2f and 2g. 7. repeat steps 5 and 6 for all instruction words in the page. 8. w rite the page using programming instruction 2h. 9. poll for flash write complete using programming instruction 2i, or wait for t w lrh (refer to table 162 on page 355). 10. repeat steps 3 to 9 until all data have been programmed. a more efficient data transfer can be achieved using the prog_pageload instruction: 1. enter jtag instruction prog_comma n ds. 2. enable flash write using programming instruction 2a. 3. load the page address using programming instructions 2b, 2c and 2d. pc w ord (refer to table 155 on page 345) is used to address within one page and must be written as 0. 4. enter jtag instruction prog_pageload. 5. load the entire page by shifting in all instruction words in the page byte-by-byte, starting with the lsb of the first instruction in the page and ending with the msb of the last instruction in the page. use update-dr to copy the contents of the flash data byte register into the flash page location and to auto-increment the program counter before each new word. 6. enter jtag instruction prog_comma n ds. 7. w rite the page using programming instruction 2h. 8. poll for flash write complete using programming instruction 2i, or wait for t w lrh (refer to table 162 on page 355). 9. repeat steps 3 to 8 until all data have been programmed. reading the flash 1. enter jtag instruction prog_comma n ds. 2. enable flash read using programming instruction 3a. 3. load address using programming instructions 3b, 3c and 3d. 4. read data using programming instruction 3e. 5. repeat steps 3 and 4 until all data have been read. a more efficient data transfer can be achieved using the prog_pageread instruction: 1. enter jtag instruction prog_comma n ds. 2. enable flash read using programming instruction 3a. 3. load the page address using programming instructions 3b, 3c and 3d. pc w ord (refer to table 155 on page 345) is used to address within one page and must be written as 0. 4. enter jtag instruction prog_pageread. 372 atmega640/1280/1281/2560/2561 2549k?avr?01/07 5. read the entire page (or flash) by shifting out all instruction words in the page (or flash), starting with the lsb of the first instruction in the page (flash) and ending with the msb of the last instruct ion in the page (flash). the capture-dr state both captures the data from the flash, and also auto-increments the pro- gram counter after each word is read. n ote that capture-dr comes before the shift-dr state. hence, the first byte which is shifted out contains valid data. 6. enter jtag instruction prog_comma n ds. 7. repeat steps 3 to 6 until all data have been read. programming the eeprom before programming the eeprom a chip erase must be performed, see ?performing chip erase? on page 370. 1. enter jtag instruction prog_comma n ds. 2. enable eeprom write using programming instruction 4a. 3. load address high byte using programming instruction 4b. 4. load address low byte using programming instruction 4c. 5. load data using programming instructions 4d and 4e. 6. repeat steps 4 and 5 for all data bytes in the page. 7. w rite the data using programming instruction 4f. 8. poll for eeprom write complete using pr ogramming instruction 4g, or wait for t w lrh (refer to table 162 on page 355). 9. repeat steps 3 to 8 until all data have been programmed. n ote that the prog_pageload instruction can not be used when programming the eeprom. reading the eeprom 1. enter jtag instruction prog_comma n ds. 2. enable eeprom read using programming instruction 5a. 3. load address using programming instructions 5b and 5c. 4. read data using programming instruction 5d. 5. repeat steps 3 and 4 until all data have been read. n ote that the prog_pageread instru ction can not be used when reading the eeprom. programming the fuses 1. enter jtag instruction prog_comma n ds. 2. enable fuse write using programming instruction 6a. 3. load data high byte using programming instructions 6b. a bit value of ?0? will pro- gram the corresponding fuse, a ?1? will unprogram the fuse. 4. w rite fuse high byte using programming instruction 6c. 5. poll for fuse write complete using prog ramming instruction 6d, or wait for t w lrh (refer to table 162 on page 355). 6. load data low byte using programming instructions 6e. a ?0? will program the fuse, a ?1? will unprogram the fuse. 7. w rite fuse low byte using programming instruction 6f. 8. poll for fuse write complete using prog ramming instruction 6g, or wait for t w lrh (refer to table 162 on page 355). 373 atmega640/1280/1281/2560/2561 2549k?avr?01/07 programming the lock bits 1. enter jtag instruction prog_comma n ds. 2. enable lock bit write using programming instruction 7a. 3. load data using programmin g instructions 7b. a bit value of ?0? will program the corresponding lock bit, a ?1? w ill leave the lock bit unchanged. 4. w rite lock bits using programming instruction 7c. 5. poll for lock bit write complete using programming instruction 7d, or wait for t w lrh (refer to table 162 on page 355). reading the fuses and lock bits 1. enter jtag instruction prog_comma n ds. 2. enable fuse/lock bit read using programming instruction 8a. 3. to read all fuses and lock bits, use programming instruction 8e. to only read fuse high byte, use programming instruction 8b. to only read fuse low byte, use programming instruction 8c. to only read lock bits, use programming instruction 8d. reading the signature bytes 1. enter jtag instruction prog_comma n ds. 2. enable signature byte read using programming instruction 9a. 3. load address 0x00 using programming instruction 9b. 4. read first signature byte using programming instruction 9c. 5. repeat steps 3 and 4 with address 0x01 and address 0x02 to read the second and third signature bytes, respectively. reading the calibration byte 1. enter jtag instruction prog_comma n ds. 2. enable calibration byte read using programming instruction 10a. 3. load address 0x00 using programming instruction 10b. 4. read the calibration byte using programming instruction 10c. 374 atmega640/1280/1281/2560/2561 2549k?avr?01/07 electrical characteristics absolute maximum ratings* dc characteristics operating temperature.................................. -55 c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of th is specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65c to +150c voltage on any pin except reset with respect to ground ................................-0.5v to v cc +0.5v voltage on reset with respect to ground......-0.5v to +13.0v maximum operating voltage ............................................ 6.0v dc current per i/o pin ............................................... 40.0 ma dc current v cc and g n d pins................................ 200.0 ma t a = -40 c to 85 c, v cc = 1.8v to 5.5v (unless otherwise noted) symbol parameter condition min. (5) typ. max. (5) units v il input low voltage,except xtal1 and reset pin v cc = 1.8v - 2.4v v cc = 2.4v - 5.5v -0.5 -0.5 0.2v cc (1) 0.3v cc (1) v v il1 input low voltage, xtal1 pin v cc = 1.8v - 5.5v -0.5 0.1v cc (1) v v il2 input low voltage, reset pin v cc = 1.8v - 5.5v -0.5 0.1v cc (1) v v ih input high voltage, except xtal1 and reset pins v cc = 1.8v - 2.4v v cc = 2.4v - 5.5v 0.7v cc (2) 0.6v cc (2) v cc + 0.5 v cc + 0.5 v v ih1 input high voltage, xtal1 pin v cc = 1.8v - 2.4v v cc = 2.4v - 5.5v 0.8v cc (2) 0.7v cc (2) v cc + 0.5 v cc + 0.5 v v ih2 input high voltage, reset pin v cc = 1.8v - 5.5v 0.9v cc (2) v cc + 0.5 v v ol output low voltage (3) , except reset pin i ol = 20 ma, v cc = 5v i ol = 10 ma, v cc = 3v 0.9 0.6 v v oh output high voltage (4) , except reset pin i oh = -20 ma, v cc = 5v i oh = -10 ma, v cc = 3v 4.2 2.3 v i il input leakage current i/o pin v cc = 5.5v, pin low (absolute value) 1a i ih input leakage current i/o pin v cc = 5.5v, pin high (absolute value) 1a r rst reset pull-up resistor 30 60 k r pu i/o pin pull-up resistor 20 50 k 375 atmega640/1280/1281/2560/2561 2549k?avr?01/07 n ote: 1. "max" means the highest value where the pin is guaranteed to be read as low 2. "min" means the lowest value where the pin is guaranteed to be read as high 3. although each i/o port can sink more than the test conditi ons (20ma at vcc = 5v, 10ma at vcc = 3v) under steady state conditions (non-transient), th e following must be observed: atmega1281/2561: 1.)the sum of all iol, for ports a0-a7, g2, c4-c7 should not exceed 100 ma. 2.)the sum of all iol, for ports c0-c3, g0-g1, d0-d7 should not exceed 100 ma. 3.)the sum of all iol, for ports g3-g5, b0-b7, e0-e7 should not exceed 100 ma. 4.)the sum of all iol, for ports f0-f7 should not exceed 100 ma. atmega640/1280/2560: 1.)the sum of all iol, for ports j0-j7, a0-a7, g2 should not exceed 200 ma. 2.)the sum of all iol, for ports c0-c7, g0 -g1, d0-d7, l0-l7 should not exceed 200 ma. 3.)the sum of all iol, for ports g3-g4, b0-b7, h0-b7 should not exceed 200 ma. 4.)the sum of all iol, for ports e0-e7, g5 should not exceed 100 ma. 5.)the sum of all iol, for ports f0-f7, k0-k7 should not exceed 100 ma. if iol exceeds the test condition, vol may exceed the related specification. pins are not guar anteed to sink current greater than the listed test condition. 4. although each i/o port can source more than the test conditions (20ma at vcc = 5v, 10ma at vcc = 3v) under steady state conditions (non-transient), the following must be observed: atmega1281/2561: 1)the sum of all ioh, for ports a0-a7, g2, c4-c7 should not exceed 100 ma. 2)the sum of all ioh, for ports c0-c3, g0-g1, d0-d7 should not exceed 100 ma. 3)the sum of all ioh, for ports g3-g5, b0-b7, e0-e7 should not exceed 100 ma. 4)the sum of all ioh, for ports f0-f7 should not exceed 100 ma. atmega640/1280/2560: 1)the sum of all ioh, for ports j0-j7, g2, a0-a7 should not exceed 200 ma. 2)the sum of all ioh, for ports c0-c7, g0-g 1, d0-d7, l0-l7 should not exceed 200 ma. 3)the sum of all ioh, for ports g3-g4, b0-b7, h0-h7 should not exceed 200 ma. i cc power supply current (6) active 1mhz, v cc = 2v ( atmega640/1280/2560 /1v) 0.5 0.8 ma active 4mhz, v cc = 3v ( atmega640/1280/2560 /1l) 3.2 5 ma active 8mhz, v cc = 5v ( atmega640/1280/1281/2560/2561 ) 10 14 ma idle 1mhz, v cc = 2v ( atmega640/1280/2560 /1v) 0.14 0.22 ma idle 4mhz, v cc = 3v ( atmega640/1280/2560 /1l) 0.7 1.1 ma idle 8mhz, v cc = 5v ( atmega640/1280/1281/2560/2561 ) 2.7 4 ma power-down mode w dt enabled, v cc = 3v <5 15 a w dt disabled, v cc = 3v <1 5 a v acio analog comparator input offset voltage v cc = 5v v in = v cc /2 <10 40 mv i aclk analog comparator input leakage current v cc = 5v v in = v cc /2 -50 50 na t acid analog comparator propagation delay v cc = 2.7v v cc = 4.0v 750 500 ns t a = -40 c to 85 c, v cc = 1.8v to 5.5v (unless otherwise noted) (continued) symbol parameter condition min. (5) typ. max. (5) units 376 atmega640/1280/1281/2560/2561 2549k?avr?01/07 4)the sum of all ioh, for ports e0-e7, g5 should not exceed 100 ma. 5)the sum of all ioh, for ports f0-f7, k0-k7 should not exceed 100 ma. if ioh exceeds the test condition, voh may exceed the rela ted specification. pins are not guaranteed to source current greater than the listed test condition. 5. all dc characteristics contained in this datasheet are based on simulation and characterization of other avr microcontrol- lers manufactured in the same process technology. these valu es are preliminary values repr esenting design targets, and will be updated after characterization of actual silicon 6. values with ?prr1 ? power reduction register 1? enabled (0xff). external clock drive waveforms figure 155. external clock drive w aveforms external clock drive n ote: all dc characteristics contained in this datasheet are based on simulation and charac- terization of other avr microcontrollers ma nufactured in the same process technology. these values are preliminary values repres enting design targets, and will be updated after characterization of actual silicon. v il1 v ih1 table 167. external clock drive symbol parameter v cc =1.8-5.5v v cc =2.7-5.5v v cc =4.5-5.5v units min. max. min. max. min. max. 1/t clcl oscillator frequency 0208016mhz t clcl clock period 500 125 62.5 ns t chcx high time 200 50 25 ns t clcx low time 200 50 25 ns t clch rise time 2.0 1.6 0.5 s t chcl fall time 2.0 1.6 0.5 s t clcl change in period from one clock cycle to the next 22 2% 377 atmega640/1280/1281/2560/2561 2549k?avr?01/07 maximum speed vs. v cc maximum frequency is depending on v cc. as shown in figure 156 trough figure 159, the maximum fr equency vs. v cc curve is linear between 1.8v < v cc < 2.7v and between 2.7v < v cc < 4.5v. 8 mhz figure 156. maximum frequency vs. v cc , atmega640v/1280v/1281v/2560v/2561v figure 157. maximum frequency vs. v cc when only using n o-read- w hile- w rite sec- tion (1) , atmega2560v/atmega2561v n ote: 1. w hen only using the read- w hile- w rite section of the program memory, a higher speed can be achieved at low voltage, see ?read- w hile- w rite and n o read- w hile- w rite flash sections? on page 323 for addresses. 8 mhz 4 mhz 1.8v 2.7v 5.5v safe operating area 8 mhz 2 mhz 1.8v 2.7v 5.5v safe operating area 378 atmega640/1280/1281/2560/2561 2549k?avr?01/07 16 mhz figure 158. maximum frequency vs. v cc , atmega640/atmega1280/atmega1281 figure 159. maximum frequency vs. v cc , atmega2560/atmega2561 16 mhz 8 mhz 2.7v 4.5v 5.5v safe operating area 16 mhz 4.5v 5.5v safe operating area 379 atmega640/1280/1281/2560/2561 2549k?avr?01/07 2-wire serial inte rface characteristics table 168 describes the requirements for devices connected to the 2-wire serial bus. the atmega640/1280/1281/2560/2561 2-wire serial interface meets or exceeds these requirements under the noted conditions. timing symbols refer to figure 160. n otes: 1. in atmega640/1280/1281/2560/2561 , this parameter is characterized and not 100% tested. 2. required only for f scl > 100 khz. 3. c b = capacitance of one bus line in pf. table 168. 2-wire serial bus requirements symbol parameter condition min max units v il input low-voltage -0.5 0.3 v cc v v ih input high-voltage 0.7 v cc v cc + 0.5 v v hys (1) hysteresis of schmitt trigger inputs 0.05 v cc (2) ?v v ol (1) output low-voltage 3 ma sink current 0 0.4 v t r (1) rise time for both sda and scl 20 + 0.1c b (3)(2) 300 ns t of (1) output fall time from v ihmin to v ilmax 10 pf < c b < 400 pf (3) 20 + 0.1c b (3)(2) 250 ns t sp (1) spikes suppressed by input filter 0 50 (2) ns i i input current each i/o pin 0.1v cc < v i < 0.9v cc -10 10 a c i (1) capacitance for each i/o pin ? 10 pf f scl scl clock frequency f ck (4) > max(16f scl , 250khz) (5) 0 400 khz rp value of pull-up resistor f scl 100 khz f scl > 100 khz t hd;sta hold time (repeated) start condition f scl 100 khz 4.0 ? s f scl > 100 khz 0.6 ? s t lo w low period of the scl clock f scl 100 khz (6) 4.7 ? s f scl > 100 khz (7) 1.3 ? s t high high period of the scl clock f scl 100 khz 4.0 ? s f scl > 100 khz 0.6 ? s t su;sta set-up time for a repeated start condition f scl 100 khz 4.7 ? s f scl > 100 khz 0.6 ? s t hd;dat data hold time f scl 100 khz 0 3.45 s f scl > 100 khz 0 0.9 s t su;dat data setup time f scl 100 khz 250 ? ns f scl > 100 khz 100 ? ns t su;sto setup time for stop condition f scl 100 khz 4.0 ? s f scl > 100 khz 0.6 ? s t buf bus free time between a stop and start condition f scl 100 khz 4.7 ? s f scl > 100 khz 1.3 ? s v cc 0,4v ? 3ma ---------------------------- 1000ns c b ------------------- v cc 0,4v ? 3ma ---------------------------- 300ns c b --------------- - 380 atmega640/1280/1281/2560/2561 2549k?avr?01/07 4. f ck = cpu clock frequency 5. this requirement applies to all atmega640/1280/1281/2560/2561 2-wire serial interface oper ation. other devices con- nected to the 2-wire serial bus need only obey the general f scl requirement. 6. the actual low period generated by the atmega640/1280/1281/2560/2561 2-wire serial interface is (1/f scl - 2/f ck ), thus f ck must be greater than 6 mhz for the low time requirement to be strictly met at f scl = 100 khz. 7. the actual low period generated by the atmega640/1280/1281/2560/2561 2-wire serial interface is (1/f scl - 2/f ck ), thus the low time requirement will not be strictly met for f scl > 308 khz when f ck = 8 mhz. still, atmega640/1280/1281/2560/2561 devices connected to the bus may communicate at full speed (400 khz) with other atmega640/1280/1281/2560/2561 devices, as well as any other device with a proper t lo w acceptance margin. figure 160. 2-wire serial bus timing spi timing characteristics see figure 161 and figure 162 for details. n ote: 1. in spi programming mode the minimum sck high/low period is: - 2 t clcl for f ck < 12 mhz - 3 t clcl for f ck > 12 mhz t su;sta t low t high t low t of t hd;sta t hd;dat t su;dat t su;sto t buf scl sda t r table 169. spi timing parameters description mode min typ max 1 sck period master see table 100 ns 2 sck high/low master 50% duty cycle 3 rise/fall time master tbd 4 setup master 10 5holdmaster 10 6 out to sck master 0.5 ? t sck 7 sck to out master 10 8 sck to out high master 10 9ss low to out slave 15 10 sck period slave 4 ? t ck 11 sck high/low (1) slave 2 ? t ck 12 rise/fall time slave tbd 13 setup slave 10 14 hold slave t ck 15 sck to out slave 15 16 sck to ss high slave 20 17 ss high to tri-state slave 10 18 ss low to sck slave 20 381 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 161. spi interface timing requirements (master mode) figure 162. spi interface timing requirements (slave mode) mo si (data output) sck (cpol = 1) mi so (data input) sck (cpol = 0) ss msb lsb lsb msb ... ... 61 22 3 45 8 7 mi so (data output) sck (cpol = 1) mo si (data input) sck (cpol = 0) ss msb lsb lsb msb ... ... 10 11 11 12 13 14 17 15 9 x 16 382 atmega640/1280/1281/2560/2561 2549k?avr?01/07 adc characteristics ? preliminary data n otes: 1. values are guidelines only. table 170. adc characteristics, singel ended channels symbol parameter condition min (1) typ (1) max (1) units resolution single ended conversion 10 bits absolute accuracy (including i n l, d n l, quantization error, gain and offset error) single ended conversion v ref = 4v, v cc = 4v, clk adc = 200 khz 2.25 (2) 2.5 lsb single ended conversion v ref = 4v, v cc = 4v, clk adc = 1 mhz 3lsb single ended conversion v ref = 4v, v cc = 4v, clk adc = 200 khz n oise reduction mode 2lsb single ended conversion v ref = 4v, v cc = 4v, clk adc = 1 mhz n oise reduction mode 3 (2.75) lsb integral n on-linearity (i n l) single ended conversion v ref = 4v, v cc = 4v, clk adc = 200 khz 1.25 (1.0) lsb differential n on-linearity (d n l) single ended conversion v ref = 4v, v cc = 4v, clk adc = 200 khz 0.5 (0.25) lsb gain error single ended conversion v ref = 4v, v cc = 4v, clk adc = 200 khz 2 (1.75) lsb offset error single ended conversion v ref = 4v, v cc = 4v, clk adc = 200 khz -2 (-1.75) lsb conversion time free running conversion 13 260 s clock frequency single ended conversion 50 1000 khz avcc analog supply voltage v cc - 0.3 v cc + 0.3 v v ref reference voltage 1.0 avcc v v i n input voltage g n dv ref v input bandwidth 38,5 khz v i n t1 internal voltage reference 1.1v 1.0 1.1 1.2 v v i n t2 internal voltage reference 2.56v 2.4 2.56 2.8 v r ref reference input resistance 32 k r ai n analog input resistance 100 m 383 atmega640/1280/1281/2560/2561 2549k?avr?01/07 table 171. adc characteristics, differential channels symbol parameter condition min (1) typ (1) max (1) units resolution gain = 1x 8 bits gain = 10x 8 bits gain = 200x 7 bits absolute accuracy(including i n l, d n l, quantization error, gain and offset error) gain = 1x v ref = 4v, v cc = 5v clk adc = 50 - 200 khz 18 (17) lsb gain = 10x v ref = 4v, v cc = 5v clk adc = 50 - 200 khz 17 lsb gain = 200x v ref = 4v, v cc = 5v clk adc = 50 - 200 khz 9lsb integral n on-linearity (i n l) gain = 1x v ref = 4v, v cc = 5v clk adc = 50 - 200 khz 2.5 (2.0) lsb gain = 10x v ref = 4v, v cc = 5v clk adc = 50 - 200 khz 5 (4) lsb gain = 200x v ref = 4v, v cc = 5v clk adc = 50 - 200 khz 9lsb differential n on-linearity (d n l) gain = 1x v ref = 4v, v cc = 5v clk adc = 50 - 200 khz 0.75 (0.5) lsb gain = 10x v ref = 4v, v cc = 5v clk adc = 50 - 200 khz 1.5 (1.0) lsb gain = 200x v ref = 4v, v cc = 5v clk adc = 50 - 200 khz 10 (9) lsb gain error gain = 1x 1.7 % gain = 10x 1.7 % gain = 200x 0.5 (0.2) % offset error gain = 1x v ref = 4v, v cc = 5v clk adc = 50 - 200 khz 2 (1) lsb gain = 10x v ref = 4v, v cc = 5v clk adc = 50 - 200 khz 2 (19 lsb gain = 200x v ref = 4v, v cc = 5v clk adc = 50 - 200 khz 3lsb clock frequency 50 200 khz conversion time 65 260 s 384 atmega640/1280/1281/2560/2561 2549k?avr?01/07 n ote: 1. values are guidelines only. calibrated internal rc oscillator accuracy n otes: 1. voltage range for atmega64 0v/1281v/1280v/2561v/2560v. 2. voltage range for atmega640/1281/1280/2561/2560. avcc analog supply voltage v cc - 0.3 v cc + 0.3 v v ref reference voltage 2.7(2.0) avcc - 0.5 v v i n input voltage g n dv cc v v diff input differential voltage -v ref /gain v ref /gain v adc conversion output -511 511 lsb input bandwidth 4khz v i n t internal voltage reference 2.3 2.56 2.8 v r ref reference input resistance 32 k r ai n analog input resistance 100 m table 171. adc characteristics, differential channels (continued) symbol parameter condition min (1) typ (1) max (1) units table 172. calibration accuracy of internal rc oscillator frequency v cc temperature calibration accuracy factory calibration 8.0 mhz 3v 25 c10% user calibration 7.3 - 8.1 mhz 1.8v - 5.5v (1) 2.7v - 5.5v (2) -40 c - 85 c1% 385 atmega640/1280/1281/2560/2561 2549k?avr?01/07 external data memory timing n otes: 1. this assumes 50% clock duty cycle. the half period is actually the high time of the external clock, xtal1. 2. this assumes 50% clock duty cycle. the half period is actually the low time of the external clock, xtal1. table 173. external data memory characteristics, 4.5 - 5.5 volts, n o w ait-state symbol parameter 8 mhz oscillator variable oscillator unit min max min max 01/t clcl oscillator frequency 0.0 16 mhz 1t lhll ale pulse w idth 115 1.0t clcl -10 ns 2t avll address valid a to ale low 57.5 0.5t clcl -5 (1) ns 3a t llax_st address hold after ale low, write access 55 ns 3b t llax_ld address hold after ale low, read access 55 ns 4t avllc address valid c to ale low 57.5 0.5t clcl -5 (1) ns 5t avrl address valid to rd low 115 1.0t clcl -10 ns 6t av w l address valid to w r low 115 1.0t clcl -10 ns 7t ll w l ale low to w r low 47.5 67.5 0.5t clcl -15 (2) 0.5t clcl +5 (2) ns 8t llrl ale low to rd low 47.5 67.5 0.5t clcl -15 (2) 0.5t clcl +5 (2) ns 9t dvrh data setup to rd high 40 40 ns 10 t rldv read low to data valid 75 1.0t clcl -50 ns 11 t rhdx data hold after rd high 0 0 ns 12 t rlrh rd pulse w idth 115 1.0t clcl -10 ns 13 t dv w l data setup to w r low 42.5 0.5t clcl -20 (1) ns 14 t w hdx data hold after w r high 115 1.0t clcl -10 ns 15 t dv w h data valid to w r high 125 1.0t clcl ns 16 t w l w h w r pulse w idth 115 1.0t clcl -10 ns table 174. external data memory characteristics, 4.5 - 5.5 volts, 1 cycle w ait-state symbol parameter 8 mhz oscillator variable oscillator unit min max min max 01/t clcl oscillator frequency 0.0 16 mhz 10 t rldv read low to data valid 200 2.0t clcl -50 ns 12 t rlrh rd pulse w idth 240 2.0t clcl -10 ns 15 t dv w h data valid to w r high 240 2.0t clcl ns 16 t w l w h w r pulse w idth 240 2.0t clcl -10 ns 386 atmega640/1280/1281/2560/2561 2549k?avr?01/07 table 175. external data memory characteristics, 4.5 - 5.5 volts, sr w n1 = 1, sr w n0 = 0 symbol parameter 4 mhz oscillator variable oscillator unit min max min max 01/t clcl oscillator frequency 0.0 16 mhz 10 t rldv read low to data valid 325 3.0t clcl -50 ns 12 t rlrh rd pulse w idth 365 3.0t clcl -10 ns 15 t dv w h data valid to w r high 375 3.0t clcl ns 16 t w l w h w r pulse w idth 365 3.0t clcl -10 ns table 176. external data memory characteristics, 4.5 - 5.5 volts, sr w n1 = 1, sr w n0 = 1 symbol parameter 4 mhz oscillator variable oscillator unit min max min max 01/t clcl oscillator frequency 0.0 16 mhz 10 t rldv read low to data valid 325 3.0t clcl -50 ns 12 t rlrh rd pulse w idth 365 3.0t clcl -10 ns 14 t w hdx data hold after w r high 240 2.0t clcl -10 ns 15 t dv w h data valid to w r high 375 3.0t clcl ns 16 t w l w h w r pulse w idth 365 3.0t clcl -10 ns table 177. external data memory characteristics, 2.7 - 5.5 volts, n o w ait-state symbol parameter 4 mhz oscillator variable oscillator unit min max min max 01/t clcl oscillator frequency 0.0 8 mhz 1t lhll ale pulse w idth 235 t clcl -15 ns 2t avll address valid a to ale low 115 0.5t clcl -10 (1) ns 3a t llax_st address hold after ale low, write access 55 ns 3b t llax_ld address hold after ale low, read access 55 ns 4t avllc address valid c to ale low 115 0.5t clcl -10 (1) ns 5t avrl address valid to rd low 235 1.0t clcl -15 ns 6t av w l address valid to w r low 235 1.0t clcl -15 ns 7t ll w l ale low to w r low 115 130 0.5t clcl -10 (2) 0.5t clcl +5 (2) ns 8t llrl ale low to rd low 115 130 0.5t clcl -10 (2) 0.5t clcl +5 (2) ns 9t dvrh data setup to rd high 45 45 ns 10 t rldv read low to data valid 190 1.0t clcl -60 ns 11 t rhdx data hold after rd high 0 0 ns 387 atmega640/1280/1281/2560/2561 2549k?avr?01/07 n otes: 1. this assumes 50% clock duty cycle. the half period is actually the high time of the external clock, xtal1. 2. this assumes 50% clock duty cycle. the half period is actually the low time of the external clock, xtal1. 12 t rlrh rd pulse w idth 235 1.0t clcl -15 ns 13 t dv w l data setup to w r low 105 0.5t clcl -20 (1) ns 14 t w hdx data hold after w r high 235 1.0t clcl -15 ns 15 t dv w h data valid to w r high 250 1.0t clcl ns 16 t w l w h w r pulse w idth 235 1.0t clcl -15 ns table 177. external data memory characteristics, 2.7 - 5.5 volts, n o w ait-state (continued) symbol parameter 4 mhz oscillator variable oscillator unit min max min max table 178. external data memory characteristics, 2.7 - 5.5 volts, sr w n1 = 0, sr w n0 = 1 symbol parameter 4 mhz oscillator variable oscillator unit min max min max 01/t clcl oscillator frequency 0.0 8 mhz 10 t rldv read low to data valid 440 2.0t clcl -60 ns 12 t rlrh rd pulse w idth 485 2.0t clcl -15 ns 15 t dv w h data valid to w r high 500 2.0t clcl ns 16 t w l w h w r pulse w idth 485 2.0t clcl -15 ns table 179. external data memory characteristics, 2.7 - 5.5 volts, sr w n1 = 1, sr w n0 = 0 symbol parameter 4 mhz oscillator variable oscillator unit min max min max 01/t clcl oscillator frequency 0.0 8 mhz 10 t rldv read low to data valid 690 3.0t clcl -60 ns 12 t rlrh rd pulse w idth 735 3.0t clcl -15 ns 15 t dv w h data valid to w r high 750 3.0t clcl ns 16 t w l w h w r pulse w idth 735 3.0t clcl -15 ns table 180. external data memory characteristics, 2.7 - 5.5 volts, sr w n1 = 1, sr w n0 = 1 symbol parameter 4 mhz oscillator variable oscillator unit min max min max 01/t clcl oscillator frequency 0.0 8 mhz 10 t rldv read low to data valid 690 3.0t clcl -60 ns 12 t rlrh rd pulse w idth 735 3.0t clcl -15 ns 14 t w hdx data hold after w r high 485 2.0t clcl -15 ns 15 t dv w h data valid to w r high 750 3.0t clcl ns 16 t w l w h w r pulse w idth 735 3.0t clcl -15 ns 388 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 163. external memory timing (sr w n1 = 0, sr w n0 = 0 figure 164. external memory timing (sr w n1 = 0, sr w n0 = 1) ale t1 t2 t3 write read wr t4 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data address system clock (clk cpu ) 1 4 2 7 6 3a 3b 5 8 12 16 13 10 11 14 15 9 ale t1 t2 t3 write read wr t5 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data address system clock (clk cpu ) 1 4 2 7 6 3a 3b 5 8 12 16 13 10 11 14 15 9 t4 389 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 165. external memory timing (sr w n1 = 1, sr w n0 = 0) figure 166. external memory timing (sr w n1 = 1, sr w n0 = 1) () the ale pulse in the last period (t4-t7) is only present if the next inst ruction accesses the ram (internal or external). ale t1 t2 t3 write read wr t6 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data address system clock (clk cpu ) 1 4 2 7 6 3a 3b 5 8 12 16 13 10 11 14 15 9 t4 t5 ale t1 t2 t3 write read wr t7 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data address system clock (clk cpu ) 1 4 2 7 6 3a 3b 5 8 12 16 13 10 11 14 15 9 t4 t5 t6 390 atmega640/1280/1281/2560/2561 2549k?avr?01/07 typical characteristics the following charts show typical behavior. these figures are not tested during manu- facturing. all current consumption measurements are performed with all i/o pins configured as inputs and with internal pull-ups enabled. a sine wave generator with rail- to-rail output is used as clock source. all active- and idle current consumption measurements are done with all bits in the prr registers set and thus, the corresponding i/o modules are turned off. also the analog comparator is disabled during these measurements. table 181 on page 395 and table 182 on page 396 show the additional current consumption compared to i cc active and i cc idle for every i/o module controlled by the power reduction register. see ? w hen the sm2:0 bits are 111 and an external crystal/resonator clock option is selected, the sleep instruction makes the m cu enter extended standby mode. this mode is identi- cal to power-save mode with the exception that the oscillator is kept running. from extended standby mode, the device wakes up in six clock cycles.power reduction register? on page 52 for details. the power consumption in power-down mode is independent of clock selection. the current consumption is a function of several factors such as: operating voltage, operating frequency, loading of i/o pins, switching rate of i/o pins, code executed and ambient temperature. the dominating factors are operating voltage and frequency. the current drawn from capacitive loaded pins may be estimated (for one pin) as c l * v cc *f where c l = load capacitance, v cc = operating voltage and f = average switch- ing frequency of i/o pin. the parts are characterized at frequencies higher than test limits. parts are not guaran- teed to function properly at frequencies higher than the ordering code indicates. the difference between current consumption in power-down mode with w atchdog timer enabled and power-down mode with w atchdog timer disabled represents the dif- ferential current drawn by the w atchdog timer. active supply current figure 167. active supply current vs. frequency (0.1 - 1.0 mhz) active supply current vs. frequency 0.1 - 1.0 mhz 5.5v 5.0v 4.5v 4.0v 3.3v 2.7v 1.8v 0 0,5 1 1,5 2 2,5 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 frequency (mhz) i cc (m a ) 391 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 168. active supply current vs. frequency (1 - 16 mhz) figure 169. active supply current vs. v cc (internal rc oscillator, 8 mhz) active supply current vs. frequency 1 - 16 mhz 5.5v 5.0v 4.5v 0 5 10 15 20 25 0246810121416 frequency (mhz) i cc (m a) 4.0v 3.3v 2.7v 1.8v active supply current vs. v cc internal rc oscillator, 8 mhz 85?c 25?c -40?c 0 2 4 6 8 10 12 14 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) i cc (ma) 392 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 170. active supply current vs. v cc (internal rc oscillator, 1 mhz) figure 171. active supply current vs. v cc (internal rc oscillator, 128 khz) active supply current vs. v cc internal rc oscillator, 1 mhz 85?c 25?c -40?c 0 0,5 1 1,5 2 2,5 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) i cc (ma) active supply current vs. v cc internal rc oscillator, 128 khz 85?c 25?c -40?c 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) i cc (ma) 393 atmega640/1280/1281/2560/2561 2549k?avr?01/07 idle supply current figure 172. idle supply current vs. low frequency (0.1 - 1.0 mhz) figure 173. idle supply current vs. frequency (1 - 16 mhz) idle supply current vs. low frequency 0.1 - 1.0 mhz 5.5v 5.0v 4.5v 4.0v 3.3v 2.7v 1.8v 0 0,1 0,2 0,3 0,4 0,5 0,6 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 frequency (mhz) i cc (ma) idle supply current vs. frequency 1 - 16 mhz 5.5v 5.0v 4.5v 0 1 2 3 4 5 6 7 8 0246810121416 frequency (mhz) i cc (m a) 4.0v 3.3v 2.7v 1.8v 394 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 174. idle supply current vs. v cc (internal rc oscillator, 8 mhz) figure 175. idle supply current vs. v cc (internal rc oscillator, 1 mhz) idle supply current vs. v cc internal rc oscillator, 8 mhz 85?c 25?c -40?c 0 0,5 1 1,5 2 2,5 3 3,5 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) i cc (ma) idle supply current vs. v cc internal rc oscillator, 1 mhz 85?c 25?c -40?c 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) i cc (ma) 395 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 176. idle supply current vs. v cc (internal rc osc illator, 128 khz)i supply current of io modules the tables and formulas below can be used to calculate the additional current consump- tion for the different i/o modules in active and idle mode. the enabling or disabling of the i/o modules are controlled by the power reduction register. see ? w hen the sm2:0 bits are 111 and an external crystal/resonator clock option is selected, the sleep instruction makes the mcu enter extended standby mode. this mode is identical to power-save mode with the exc eption that the oscillator is kept running. from extended standby mode, the device wakes up in six clock cycles.power reduction register? on page 52 for details. idle supply current vs. v cc internal rc oscillator, 128 khz 85?c 25?c -40?c 0 0,05 0,1 0,15 0,2 0,25 0,3 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) i cc (m a ) table 181. additional current consumption for the different i/o modules (absolute values) prr bit typical numbers v cc = 2v, f = 1mhz v cc = 3v, f = 4mhz v cc = 5v, f = 8mhz prusart3 8.0 ua 51 ua 220 ua prusart2 8.0 ua 51 ua 220 ua prusart1 8.0 ua 51 ua 220 ua prusart0 8.0 ua 51 ua 220 ua prt w i 12 ua 75 ua 315 ua prtim5 6.0 ua 39 ua 150 ua prtim4 6.0 ua 39 ua 150 ua prtim3 6.0 ua 39 ua 150 ua prtim2 11 ua 72 ua 300 ua prtim1 6.0 ua 39 ua 150 ua 396 atmega640/1280/1281/2560/2561 2549k?avr?01/07 it is possible to calculate the typical current consumption based on the numbers from table 181 for other v cc and frequency settings than listed in table 182. example 1 calculate the expected current consumption in idle mode with usart0, timer1, and t w i enabled at v cc = 2.0v and f = 1mhz. from table 182 on page 396, third column, we see that we need to add 17% for the usart0, 24% for the t w i, and 10% for the timer1 module. reading from figure 172 on page 393, we find that the idle current consumption is ~0,15ma at v cc = 2.0v and f = 1mhz. the total current consumption in idle mode with usart0, timer1, and t w i enabled, gives: prtim0 4.0 ua 24 ua 100 ua prspi 15 ua 95 ua 400 ua pradc 12 ua 75 ua 315 ua table 182. additional current consumption (percentage) in active and idle mode prr bit additional current consumption compared to active with external clock additional current consumption compared to idle with external clock prusart3 3.0% 17% prusart2 3.0% 17% prusart1 3.0% 17% prusart0 3.0% 17% prt w i4.4% 24% prtim5 1.8% 10% prtim4 1.8% 10% prtim3 1.8% 10% prtim2 4.3% 23% prtim1 1.8% 10% prtim0 1.5% 8.0% prspi 3.3% 18% pradc 4.5% 24% table 181. additional current consumption for the different i/o modules (absolute values) prr bit typical numbers v cc = 2v, f = 1mhz v cc = 3v, f = 4mhz v cc = 5v, f = 8mhz i cc total 0,15 ma 10,170,240,10 +++ () ? 0,227 ma ? 397 atmega640/1280/1281/2560/2561 2549k?avr?01/07 power-down supply current figure 177. power-down supply current vs. v cc ( w atchdog timer disabled) figure 178. power-down supply current vs. v cc ( w atchdog timer enabled) power-down supply current vs. v cc watchdog timer disabled 85?c 25?c -40?c 0 0,5 1 1,5 2 2,5 3 3,5 4 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) i cc (ua ) power-down supply current vs. v cc watchdog timer enabled 85?c 25?c -40?c 0 2 4 6 8 10 12 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) i cc (ua) 398 atmega640/1280/1281/2560/2561 2549k?avr?01/07 power-save supply current figure 179. power-save supply current vs. v cc ( w atchdog timer disabled) figure 180. power-save supply current vs. v cc ( w atchdog timer enabled) power-save supply current vs. v cc watchdog timer disabled 0 0,5 1 1,5 2 2,5 3 3,5 4 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) i cc (ua ) 25 ?c power-save supply current vs. v cc watchdog timer enabled 0 1 2 3 4 5 6 7 8 9 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) i cc (ua) 25 ?c 399 atmega640/1280/1281/2560/2561 2549k?avr?01/07 standby supply current figure 181. standby supply current vs. v cc ( w atchdog timer disabled) pin pull-up figure 182. i/o pin pull-up resistor current vs. input voltage (v cc = 1.8 v) standby supply current vs. v cc watchdog timer disabled 6 mhz xtal 6 mhz res 4 mhz xtal 4 mhz res 455 khz res 32 khz xtal 2 mhz xtal 2 mhz res 1 mhz res 0 0,02 0,04 0,06 0,08 0,1 0,12 0,14 0,16 0,18 0,2 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) i cc (m a ) i/o pin pull-up resistor current vs. input voltage v cc = 1.8v 85?c 25?c -40?c 0 10 20 30 40 50 60 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 v op (v) i op (ua ) 400 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 183. i/o pin pull-up resistor current vs. input voltage (v cc = 2.7 v) figure 184. i/o pin pull-up resistor current vs. input voltage (v cc = 5v) i/o pin pull-up resistor current vs. input voltage v cc = 2.7v 85?c 25?c -40?c 0 10 20 30 40 50 60 70 80 90 0 0,5 1 1,5 2 2,5 3 v op (v) i op (ua) i/o pin pull-up resistor current vs. input voltage v cc = 5v 85?c 25?c -40?c 0 20 40 60 80 100 120 140 160 0123456 v op (v) i op (ua ) 401 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 185. reset pull-up resistor current vs. reset pin voltage (v cc = 1.8 v) figure 186. reset pull-up resist or current vs. reset pin voltage (v cc = 2.7 v) reset pull-up resistor current vs. reset pin voltage v cc = 1.8v 85?c 25?c -40?c 0 5 10 15 20 25 30 35 40 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 v reset (v) i reset (ua) reset pull-up resistor current vs. reset pin voltage v cc = 2.7v 85?c 25?c -40?c 0 10 20 30 40 50 60 70 0 0,5 1 1,5 2 2,5 3 v reset (v) i reset (ua) 402 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 187. reset pull-up resistor current vs. reset pin voltage (v cc = 5 v) pin driver strength figure 188. i/o pin output voltage vs.sink current (v cc = 3 v) reset pull-up resistor current vs. reset pin voltage v cc = 5v 85?c 25?c -40?c 0 20 40 60 80 100 120 0123456 v reset (v) i reset (ua) i/o pin output voltage vs. sink current v cc = 3v 85?c 25?c -40?c 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 0 5 10 15 20 25 i ol (ma) v ol (v) 403 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 189. i/o pin output voltage vs. sink current (v cc = 5 v) figure 190. i/o pin output voltage vs. source current (v cc = 3 v) i/o pin output voltage vs. sink current v cc = 5v 85?c 25?c -40?c 0 0,1 0,2 0,3 0,4 0,5 0,6 0 5 10 15 20 25 i ol (ma) v ol (v) i/o pin output voltage vs. source current v cc = 3v 85?c 25?c -40?c 0 0,5 1 1,5 2 2,5 3 3,5 0 5 10 15 20 25 i oh (ma) v oh (v) 404 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 191. i/o pin output voltage vs. source current (v cc = 5 v) pin threshold and hysteresis figure 192. i/o pin input threshold voltage vs. v cc (v ih , io pin read as ?1?) i/o pin output voltage vs. source current v cc = 5v 85?c 25?c -40?c 4,3 4,4 4,5 4,6 4,7 4,8 4,9 5 5,1 0 5 10 15 20 25 i oh (ma) v oh (v) i/o pin input threshold voltage vs. v cc vih, io pin read as '1' 85?c 25?c -40?c 0 0,5 1 1,5 2 2,5 3 3,5 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) threshold (v) 405 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 193. i/o pin input threshold voltage vs. v cc (v il , io pin read as ?0?) figure 194. i/o pin input hysteresis i/o pin input threshold voltage vs. v cc vil, io pin read as '0' 85?c 25?c -40?c 0 0,5 1 1,5 2 2,5 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) threshold (v) i/o pin input hysteresis vs. v cc 85?c 25?c -40?c 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) input hyst eres is (mv) 406 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 195. reset input thresh old voltage vs. v cc (v ih , io pin read as ?1?) figure 196. reset input thresh old voltage vs. v cc (v il , io pin read as ?0?) reset input threshold voltage vs. v cc vih, io pin read as '1' 85?c 25?c -40?c 0 0,5 1 1,5 2 2,5 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) thres hold (v ) reset input threshold voltage vs. v cc vil, io pin read as '0' 85 ?c 25 ?c -40 ?c 0 0,5 1 1,5 2 2,5 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) threshold (v) 407 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 197. reset pin input hysteresis vs. v cc bod threshold and analog comparator offset figure 198. bod threshold vs. temperature (bod level is 4.3 v) reset pin input hysteresis vs. v cc 85?c 25?c -40?c 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) input hy steresis (mv) rising vcc falling vcc bod thresholds vs. temperature bodlevels is 4.3v 4.2 4.25 4.3 4.35 4.4 -60 -40 -20 0 20 40 60 80 100 temperature (c) threshold (v) 408 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 199. bod threshold vs. temperature (bod level is 2.7 v) figure 200. bod threshold vs. temperature (bod level is 1.8 v) bod thresholds vs. temperature bodlevel is 2.7v rising vcc falling vcc 2.6 2.65 2.7 2.75 2.8 -60 -40 -20 0 20 40 60 80 100 temperature (c) threshold (v) bod thresholds vs. temperature bodlevel is 1.8v rising vcc fallling vcc 1.7 1.75 1.8 1.85 1.9 -60 -40 -20 0 20 40 60 80 100 temperature (c) threshol d ( v) 409 atmega640/1280/1281/2560/2561 2549k?avr?01/07 internal osci llator speed figure 201. w atchdog oscillator frequency vs. v cc figure 202. w atchdog oscillator freq uency vs. temperature watchdog oscillator frequency vs. v cc 85?c 25 ?c -40?c 114 116 118 120 122 124 126 128 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) f rc (khz) watchdog oscillator frequency vs. temperature 5.5v 4.0v 3.3v 2.7v 2.1v 114 116 118 120 122 124 126 128 -60 -40 -20 0 20 40 60 80 100 temperature f rc (k hz ) 410 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 203. calibrated 8 mhz rc osc illator frequency vs. v cc figure 204. calibrated 8 mhz rc oscillator frequen cy vs. temperature calibrated 8 mhz rc oscillator frequency vs. v cc 85?c 25?c -40?c 7,6 7,7 7,8 7,9 8 8,1 8,2 8,3 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) f rc (mhz) calibrated 8 mhz rc oscillator frequency vs. temperature 5.0v 3.0v 7,9 8 8,1 8,2 8,3 8,4 8,5 -60 -40 -20 0 20 40 60 80 100 temperature f rc (mhz) 411 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 205. calibrated 8 mhz rc oscillator frequen cy vs. osccal value current consumption of peripheral units figure 206. brownout detector current vs. v cc calibrated 8 mhz rc oscillator frequency vs. osccal value 85?c 25?c -40?c 0 2 4 6 8 10 12 14 16 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 osccal (x1) f rc (mhz) brownout detector current vs. v cc 85?c 25?c -40?c 0 5 10 15 20 25 30 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) i cc (ua) 412 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 207. adc current vs. v cc (aref = av cc ) figure 208. aref external reference current vs. v cc adc current vs. v cc aref = av cc 85?c 25?c -40?c 0 50 100 150 200 250 300 350 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) i cc (ua) aref external reference current vs. v cc 85?c 25?c -40?c 0 50 100 150 200 250 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) i cc (ua) 413 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 209. w atchdog timer current vs. v cc figure 210. analog comparator current vs. v cc watchdog timer current vs. v cc 85?c 25?c -40?c 0 1 2 3 4 5 6 7 8 9 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) i cc (ua) analog comparator current vs. v cc 85?c 25?c -40?c 0 10 20 30 40 50 60 70 80 90 100 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) i cc (ua ) 414 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 211. programming current vs. v cc current consumption in reset and reset pulsewidth figure 212. reset supply current vs v cc (0.1 - 1.0 mhz, excluding current through the reset pull-up) programming current vs. v cc 85 ?c 25 ?c -40 ?c 0 2 4 6 8 10 12 14 16 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) i cc (ma) reset supply current vs. v cc 0.1 - 1.0 mhz, excluding current through the reset pullup 5.5v 5.0v 4.5v 4.0v 3.3v 2.7v 1.8v 0 0,05 0,1 0,15 0,2 0,25 0,3 0,35 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 frequency (mhz) i cc (m a ) 415 atmega640/1280/1281/2560/2561 2549k?avr?01/07 figure 213. reset supply current vs. v cc (1 - 16 mhz, excluding current through the reset pull-up) figure 214. minimum reset pulse w idth vs. v cc reset supply current vs. v cc 1 - 16 mhz, excluding current through the reset pullup 5.5v 5.0v 4.5v 0 0,5 1 1,5 2 2,5 3 3,5 4 0 2 4 6 8 10 12 14 16 frequency (mhz) i cc (ma) 4.0v 3.3v 2.7v 1.8v minimum reset pulse width vs. v cc 85?c 25?c -40?c 0 500 1000 1500 2000 2500 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) pulsewidth (n s) 416 atmega640/1280/1281/2560/2561 2549k?avr?01/07 register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page (0x1ff) reserved - - - - - - - - ... reserved - - - - - - - - (0x13f) reserved (0x13e) reserved (0x13d) reserved (0x13c) reserved (0x13b) reserved (0x13a) reserved (0x139) reserved (0x138) reserved (0x137) reserved (0x136) udr3 usart3 i/o data register page 227 (0x135) ubrr3h - - - - usart3 baud rate register high byte page 231 (0x134) ubrr3l usart3 baud rate register low byte page 231 (0x133) reserved - - - - - - - - (0x132) ucsr3c umsel31 umsel30 upm 31 upm30 usbs3 ucsz31 ucsz30 ucpol3 page 244 (0x131) ucsr3b rxcie3 txcie3 udrie3 rxe n 3txe n 3 ucsz32 rxb83 txb83 page 243 (0x130) ucsr3a rxc3 txc3 udre3 fe3 dor3 upe3 u2x3 mpcm3 page 242 (0x12f) reserved - - - - - - - - (0x12e) reserved - - - - - - - - (0x12d) ocr5ch timer/counter5 - output compare register c high byte page 167 (0x12c) ocr5cl timer/counter5 - output compare register c low byte page 167 (0x12b) ocr5bh timer/counter5 - output compare register b high byte page 167 (0x12a) ocr5bl timer/counter5 - output compare register b low byte page 167 (0x129) ocr5ah timer/counter5 - output compare register a high byte page 167 (0x128) ocr5al timer/counter5 - output compare register a low byte page 167 (0x127) icr5h timer/counter5 - input capture register high byte page 168 (0x126) icr5l timer/counter5 - input capture register low byte page 168 (0x125) tc n t5h timer/counter5 - counter register high byte page 165 (0x124) tc n t5l timer/counter5 - counter register low byte page 165 (0x123) reserved - - - - - - - - (0x122) tccr5c foc5a foc5b foc5c - - - - - page 164 (0x121) tccr5b ic n c5 ices5 - w gm53 w gm52 cs52 cs51 cs50 page 162 (0x120) tccr5a com5a1 com5a0 com5b1 com5b0 com5c1 com5c0 w gm51 w gm50 page 160 (0x11f) reserved - - - - - - - - (0x11e) reserved - - - - - - - - (0x11d) reserved - - - - - - - - (0x11c) reserved - - - - - - - - (0x11b) reserved - - - - - - - - (0x11a) reserved - - - - - - - - (0x119) reserved - - - - - - - - (0x118) reserved - - - - - - - - (0x117) reserved - - - - - - - - (0x116) reserved - - - - - - - - (0x115) reserved - - - - - - - - (0x114) reserved - - - - - - - - (0x113) reserved - - - - - - - - (0x112) reserved - - - - - - - - (0x111) reserved - - - - - - - - (0x110) reserved - - - - - - - - (0x10f) reserved - - - - - - - - (0x10e) reserved - - - - - - - - (0x10d) reserved - - - - - - - - (0x10c) reserved - - - - - - - - (0x10b) portl portl7 portl6 portl5 portl4 portl3 portl2 portl1 portl0 page 118 (0x10a) ddrl ddl7 ddl6 ddl5 ddl4 ddl3 ddl2 ddl1 ddl0 page 118 (0x109) pi n lpi n l7 pi n l6 pi n l5 pi n l4 pi n l3 pi n l2 pi n l1 pi n l0 page 118 (0x108) portk portk7 portk6 portk5 portk4 portk3 portk2 portk1 portk0 page 118 (0x107) ddrk ddk7 ddk6 ddk5 ddk 4 ddk3 ddk2 ddk1 ddk0 page 118 (0x106) pi n kpi n k7 pi n k6 pi n k5 pi n k4 pi n k3 pi n k2 pi n k1 pi n k0 page 118 (0x105) portj portj7 portj6 portj5 portj4 portj3 portj2 portj1 portj0 page 118 (0x104) ddrj ddj7 ddj6 ddj5 ddj4 ddj3 ddj2 ddj1 ddj0 page 118 (0x103) pi n jpi n j7 pi n j6 pi n j5 pi n j4 pi n j3 pi n j2 pi n j1 pi n j0 page 118 (0x102) porth porth7 porth6 porth5 porth4 porth3 porth2 porth1 porth0 page 117 417 atmega640/1280/1281/2560/2561 2549k?avr?01/07 (0x101) ddrh ddh7 ddh6 ddh5 ddh4 ddh3 ddh2 ddh1 ddh0 page 117 (0x100) pi n hpi n h7 pi n h6 pi n h5 pi n h4 pi n h3 pi n h2 pi n h1 pi n h0 page 117 (0xff) reserved - - - - - - - - (0xfe) reserved - - - - - - - - (0xfd) reserved - - - - - - - - (0xfc) reserved - - - - - - - - (0xfb) reserved - - - - - - - - (0xfa) reserved - - - - - - - - (0xf9) reserved - - - - - - - - (0xf8) reserved - - - - - - - - (0xf7) reserved - - - - - - - - (0xf6) reserved - - - - - - - - (0xf5) reserved - - - - - - - - (0xf4) reserved - - - - - - - - (0xf3) reserved - - - - - - - - (0xf2) reserved - - - - - - - - (0xf1) reserved - - - - - - - - (0xf0) reserved - - - - - - - - (0xef) reserved - - - - - - - - (0xee) reserved - - - - - - - - (0xed) reserved - - - - - - - - (0xec) reserved - - - - - - - - (0xeb) reserved - - - - - - - (0xea) reserved - - - - - - - - (0xe9) reserved - - - - - - - - (0xe8) reserved - - - - - - - - (0xe7) reserved - - - - - - - (0xe6) reserved - - - - - - - - (0xe5) reserved - - - - - - - - (0xe4) reserved - - - - - - - - (0xe3) reserved - - - - - - - (0xe2) reserved - - - - - - - - (0xe1) reserved - - - - - - - (0xe0) reserved - - - - - - - (0xdf) reserved - - - - - - - - (0xde) reserved - - - - - - - - (0xdd) reserved - - - - - - - (0xdc) reserved - - - - - - - - (0xdb) reserved - - - - - - - - (0xda) reserved - - - - - - - - (0xd9) reserved - - - - - - - (0xd8) reserved - - - - - - - - (0xd7) reserved - - - - - - - - (0xd6) udr2 usart2 i/o data register page 227 (0xd5) ubrr2h - - - - usart2 baud rate register high byte page 231 (0xd4) ubrr2l usart2 baud rate register low byte page 231 (0xd3) reserved - - - - - - - - (0xd2) ucsr2c umsel21 umsel20 upm21 upm 20 usbs2 ucsz21 ucsz20 ucpol2 page 244 (0xd1) ucsr2b rxcie2 txcie2 udrie2 rxe n 2txe n 2 ucsz22 rxb82 txb82 page 243 (0xd0) ucsr2a rxc2 txc2 udre2 fe2 dor2 upe2 u2x2 mpcm2 page 242 (0xcf) reserved - - - - - - - - (0xce) udr1 usart1 i/o data register page 227 (0xcd) ubrr1h - - - - usart1 baud rate register high byte page 231 (0xcc) ubrr1l usart1 baud rate register low byte page 231 (0xcb) reserved - - - - - - - - (0xca) ucsr1c umsel11 umsel10 upm11 upm 10 usbs1 ucsz11 ucsz10 ucpol1 page 244 (0xc9) ucsr1b rxcie1 txcie1 udrie1 rxe n 1txe n 1 ucsz12 rxb81 txb81 page 243 (0xc8) ucsr1a rxc1 txc1 udre1 fe1 dor1 upe1 u2x1 mpcm1 page 242 (0xc7) reserved - - - - - - - - (0xc6) udr0 usart0 i/o data register page 227 (0xc5) ubrr0h - - - - usart0 baud rate register high byte page 231 (0xc4) ubrr0l usart0 baud rate register low byte page 231 (0xc3) reserved - - - - - - - - (0xc2) ucsr0c umsel01 umsel00 upm01 upm 00 usbs0 ucsz01 ucsz00 ucpol0 page 244 (0xc1) ucsr0b rxcie0 txcie0 udrie0 rxe n 0txe n 0 ucsz02 rxb80 txb80 page 243 (0xc0) ucsr0a rxc0 txc0 udre0 fe0 dor0 upe0 u2x0 mpcm0 page 243 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 418 atmega640/1280/1281/2560/2561 2549k?avr?01/07 (0xbf) reserved - - - - - - - - (0xbe) reserved - - - - - - - - (0xbd) t w amr t w am6 t w am5 t w am4 t w am3 t w am2 t w am1 t w am0 - page 274 (0xbc) t w cr t w i n tt w ea t w sta t w sto t ww ct w e n -t w ie page 271 (0xbb) t w dr 2-wire serial interface data register page 273 (0xba) t w ar t w a6 t w a5 t w a4 t w a3 t w a2 t w a1 t w a0 t w gce page 273 (0xb9) t w sr t w s7 t w s6 t w s5 t w s4 t w s3 -t w ps1 t w ps0 page 272 (0xb8) t w br 2-wire serial interface bit rate register page 271 (0xb7) reserved - - - - - - - - (0xb6) assr -exclkas2tc n 2ub ocr2aub ocr2bub tcr2aub tcr2bub page 188 (0xb5) reserved - - - - - - - - (0xb4) ocr2b timer/counter2 output compare register b page 195 (0xb3) ocr2a timer/counter2 output compare register a page 195 (0xb2) tc n t2 timer/counter2 (8 bit) page 195 (0xb1) tccr2b foc2a foc2b - - w gm22 cs22 cs21 cs20 page 194 (0xb0) tccr2a com2a1 com2a0 com2b1 com2b0 - - w gm21 w gm20 page 195 (0xaf) reserved - - - - - - - - (0xae) reserved - - - - - - - - (0xad) ocr4ch timer/counter4 - output compare register c high byte page 167 (0xac) ocr4cl timer/counter4 - output compare register c low byte page 167 (0xab) ocr4bh timer/counter4 - output compare register b high byte page 166 (0xaa) ocr4bl timer/counter4 - output compare register b low byte page 166 (0xa9) ocr4ah timer/counter4 - output compare register a high byte page 166 (0xa8) ocr4al timer/counter4 - output compare register a low byte page 166 (0xa7) icr4h timer/counter4 - input capture register high byte page 168 (0xa6) icr4l timer/counter4 - input capture register low byte page 168 (0xa5) tc n t4h timer/counter4 - counter register high byte page 165 (0xa4) tc n t4l timer/counter4 - counter register low byte page 165 (0xa3) reserved - - - - - - - - (0xa2) tccr4c foc4a foc4b foc4c - - - - - page 164 (0xa1) tccr4b ic n c4 ices4 - w gm43 w gm42 cs42 cs41 cs40 page 162 (0xa0) tccr4a com4a1 com4a0 com4b1 com4b0 com4c1 com4c0 w gm41 w gm40 page 160 (0x9f) reserved - - - - - - - - (0x9e) reserved - - - - - - - - (0x9d) ocr3ch timer/counter3 - output compare register c high byte page 166 (0x9c) ocr3cl timer/counter3 - output compare register c low byte page 166 (0x9b) ocr3bh timer/counter3 - output compare register b high byte page 166 (0x9a) ocr3bl timer/counter3 - output compare register b low byte page 166 (0x99) ocr3ah timer/counter3 - output compare register a high byte page 166 (0x98) ocr3al timer/counter3 - output compare register a low byte page 166 (0x97) icr3h timer/counter3 - input capture register high byte page 168 (0x96) icr3l timer/counter3 - input capture register low byte page 168 (0x95) tc n t3h timer/counter3 - counter register high byte page 165 (0x94) tc n t3l timer/counter3 - counter register low byte page 165 (0x93) reserved - - - - - - - - (0x92) tccr3c foc3a foc3b foc3c - - - - - page 164 (0x91) tccr3b ic n c3 ices3 - w gm33 w gm32 cs32 cs31 cs30 page 162 (0x90) tccr3a com3a1 com3a0 com3b1 com3b0 com3c1 com3c0 w gm31 w gm30 page 160 (0x8f) reserved - - - - - - - - (0x8e) reserved - - - - - - - - (0x8d) ocr1ch timer/counter1 - output compare register c high byte page 166 (0x8c) ocr1cl timer/counter1 - output compare register c low byte page 166 (0x8b) ocr1bh timer/counter1 - output compare register b high byte page 166 (0x8a) ocr1bl timer/counter1 - output compare register b low byte page 166 (0x89) ocr1ah timer/counter1 - output compare register a high byte page 166 (0x88) ocr1al timer/counter1 - output compare register a low byte page 166 (0x87) icr1h timer/counter1 - input capture register high byte page 168 (0x86) icr1l timer/counter1 - input capture register low byte page 168 (0x85) tc n t1h timer/counter1 - counter register high byte page 165 (0x84) tc n t1l timer/counter1 - counter register low byte page 165 (0x83) reserved - - - - - - - - (0x82) tccr1c foc1a foc1b foc1c - - - - - page 164 (0x81) tccr1b ic n c1 ices1 - w gm13 w gm12 cs12 cs11 cs10 page 162 (0x80) tccr1a com1a1 com1a0 com1b1 com1b0 com1c1 com1c0 w gm11 w gm10 page 160 (0x7f) didr1 - - - - - -ai n 1d ai n 0d page 278 (0x7e) didr0 adc7d adc6d adc5d adc4d adc3d adc2d adc1d adc0d page 300 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 419 atmega640/1280/1281/2560/2561 2549k?avr?01/07 (0x7d) didr2 adc15d adc14d adc13d adc12d adc11d adc10d adc9d adc8d page 300 (0x7c) admux refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 page 294 (0x7b) adcsrb -acme - - mux5 adts2 adts1 adts0 page 277,295,,299 (0x7a) adcsra ade n adsc adate adif adie adps2 adps1 adps0 page 297 (0x79) adch adc data register high byte page 298 (0x78) adcl adc data register low byte page 298 (0x77) reserved - - - - - - - - (0x76) reserved - - - - - - - - (0x75) xmcrb xmbk - - - - xmm2 xmm1 xmm0 page 36 (0x74) xmcra sre srl2 srl1 srl0 sr w 11 sr w 10 sr w 01 sr w 00 page 34 (0x73) timsk5 - -icie5 - ocie5c ocie5b ocie5a toie5 page 169 (0x72) timsk4 - -icie4 - ocie4c ocie4b ocie4a toie4 page 169 (0x71) timsk3 - -icie3 - ocie3c ocie3b ocie3a toie3 page 169 (0x70) timsk2 - - - - - ocie2b ocie2a toie2 page 197 (0x6f) timsk1 - -icie1 - ocie1c ocie1b ocie1a toie1 page 169 (0x6e) timsk0 - - - - - ocie0b ocie0a toie0 page 135 (0x6d) pcmsk2 pci n t23 pci n t22 pci n t21 pci n t20 pci n t19 pci n t18 pci n t17 pci n t16 page 81 (0x6c) pcmsk1 pci n t15 pci n t14 pci n t13 pci n t12 pci n t11 pci n t10 pci n t9 pci n t8 page 81 (0x6b) pcmsk0 pci n t7 pci n t6 pci n t5 pci n t4 pci n t3 pci n t2 pci n t1 pci n t0 page 82 (0x6a) eicrb isc71 isc70 isc61 isc60 isc51 isc50 isc41 isc40 page 79 (0x69) eicra isc31 isc30 isc21 isc20 isc11 isc10 isc01 isc00 page 78 (0x68) pcicr - - - - - pcie2 pcie1 pcie0 page 80 (0x67) reserved - - - - - - - - (0x66) osccal oscillator calibration register page 48 (0x65) prr1 - - prtim5 prtim4 prtim3 prusart3 prusart2 prusart1 page 56 (0x64) prr0 prt w i prtim2 prtim0 - prtim1 prspi prusart0 pradc page 55 (0x63) reserved - - - - - - - - (0x62) reserved - - - - - - - - (0x61) clkpr clkpce - - - clkps3 clkps2 clkps1 clkps0 page 48 (0x60) w dtcsr w dif w die w dp3 w dce w de w dp2 w dp1 w dp0 page 66 0x3f (0x5f) sreg i t h s v n z c page 12 0x3e (0x5e) sph sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 page 14 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 page 14 0x3c (0x5c) ei n d - - - - - - -ei n d0 page 15 0x3b (0x5b) rampz - - - - - - rampz1 rampz0 page 15 0x3a (0x5a) reserved - - - - - - - - 0x39 (0x59) reserved - - - - - - - - 0x38 (0x58) reserved - - - - - - - - 0x37 (0x57) spmcsr spmie r ww sb sigrd r ww sre blbset pg w rt pgers spme n page 340 0x36 (0x56) reserved - - - - - - - - 0x35 (0x55) mcucr jtd - -pud - - ivsel ivce page 66,76,115,314 0x34 (0x54) mcusr - - -jtrf w drf borf extrf porf page 314 0x33 (0x53) smcr - - - - sm2 sm1 sm0 se page 51 0x32 (0x52) reserved - - - - - - - - 0x31 (0x51) ocdr ocdr7 ocdr6 ocdr5 ocdr4 ocdr3 ocdr2 ocdr1 ocdr0 page 307 0x30 (0x50) acsr acd acbg aco aci acie acic acis1 acis0 page 277 0x2f (0x4f) reserved - - - - - - - - 0x2e (0x4e) spdr spi data register page 208 0x2d (0x4d) spsr spif w col - - - - - spi2x page 207 0x2c (0x4c) spcr spie spe dord mstr cpol cpha spr1 spr0 page 206 0x2b (0x4b) gpior2 general purpose i/o register 2 page 34 0x2a (0x4a) gpior1 general purpose i/o register 1 page 34 0x29 (0x49) reserved - - - - - - - - 0x28 (0x48) ocr0b timer/counter0 output compare register b page 134 0x27 (0x47) ocr0a timer/counter0 output compare register a page 134 0x26 (0x46) tc n t0 timer/counter0 (8 bit) page 134 0x25 (0x45) tccr0b foc0a foc0b - - w gm02 cs02 cs01 cs00 page 133 0x24 (0x44) tccr0a com0a1 com0a0 com0b1 com0b0 - - w gm01 w gm00 page 130 0x23 (0x43) gtccr tsm - - - - - psrasy psrsy n c page 173, 198 0x22 (0x42) eearh - - - - eeprom address register high byte page 32 0x21 (0x41) eearl eeprom address register low byte page 32 0x20 (0x40) eedr eeprom data register page 32 0x1f (0x3f) eecr - - eepm1 eepm0 eerie eempe eepe eere page 32 0x1e (0x3e) gpior0 general purpose i/o register 0 page 34 0x1d (0x3d) eimsk i n t7 i n t6 i n t5 i n t4 i n t3 i n t2 i n t1 i n t0 page 79 0x1c (0x3c) eifr i n tf7 i n tf6 i n tf5 i n tf4 i n tf3 i n tf2 i n tf1 i n tf0 page 80 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 420 atmega640/1280/1281/2560/2561 2549k?avr?01/07 n ote: 1. for compatibility with future devices, reserved bits should be written to zero if accessed. reserved i/o memory addresses should never be written. 2. i/o registers within the address range $00 - $1f are directly bit-accessible using th e sbi and cbi instructions. in these reg - isters, the value of single bits can be checked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical one to them. n ote that the cbi and sbi in structions will operate on all bits in the i/o register, writing a one back into any flag read as set, thus clearing the flag. the cbi and sbi instruction s work with registers 0x00 to 0x1f only. 4. w hen using the i/o specific commands i n and out, the i/o addresses $00 - $3f must be used. w hen addressing i/o regis- ters as data space using ld and st instructio ns, $20 must be added to these addresses. the atmega640/1280/1281/2560/2561 is a complex microcontroller with more peri pheral units than can be supported within the 64 location reserved in opcode for the i n and out instructions. for the extended i/o space from $60 - $1ff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. 0x1b (0x3b) pcifr - - - - - pcif2 pcif1 pcif0 page 81 0x1a (0x3a) tifr5 - -icf5 - ocf5c ocf5b ocf5a tov5 page 169 0x19 (0x39) tifr4 - -icf4 - ocf4c ocf4b ocf4a tov4 page 170 0x18 (0x38) tifr3 - -icf3 - ocf3c ocf3b ocf3a tov3 page 170 0x17 (0x37) tifr2 - - - - - ocf2b ocf2a tov2 page 197 0x16 (0x36) tifr1 - -icf1 - ocf1c ocf1b ocf1a tov1 page 170 0x15 (0x35) tifr0 - - - - - ocf0b ocf0a tov0 page 135 0x14 (0x34) portg - - portg5 portg4 portg3 portg2 portg1 portg0 page 117 0x13 (0x33) ddrg - - ddg5 ddg4 ddg3 ddg2 ddg1 ddg0 page 117 0x12 (0x32) pi n g - -pi n g5 pi n g4 pi n g3 pi n g2 pi n g1 pi n g0 page 117 0x11 (0x31) portf portf7 portf6 portf5 por tf4 portf3 portf2 portf1 portf0 page 116 0x10 (0x30) ddrf ddf7 ddf6 ddf5 ddf4 ddf3 ddf2 ddf1 ddf0 page 117 0x0f (0x2f) pi n fpi n f7 pi n f6 pi n f5 pi n f4 pi n f3 pi n f2 pi n f1 pi n f0 page 117 0x0e (0x2e) porte porte7 porte6 porte5 por te4 porte3 porte2 porte1 porte0 page 116 0x0d (0x2d) ddre dde7 dde6 dde5 dde4 dde3 dde2 dde1 dde0 page 116 0x0c (0x2c) pi n epi n e7 pi n e6 pi n e5 pi n e4 pi n e3 pi n e2 pi n e1 pi n e0 page 116 0x0b (0x2b) portd portd7 portd6 portd5 por td4 portd3 portd2 portd1 portd0 page 116 0x0a (0x2a) ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 page 116 0x09 (0x29) pi n dpi n d7 pi n d6 pi n d5 pi n d4 pi n d3 pi n d2 pi n d1 pi n d0 page 116 0x08 (0x28) portc portc7 portc6 portc5 por tc4 portc3 portc2 portc1 portc0 page 116 0x07 (0x27) ddrc ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 page 116 0x06 (0x26) pi n cpi n c7 pi n c6 pi n c5 pi n c4 pi n c3 pi n c2 pi n c1 pi n c0 page 116 0x05 (0x25) portb portb7 portb6 portb5 por tb4 portb3 portb2 portb1 portb0 page 115 0x04 (0x24) ddrb ddb7 ddb6 ddb5 d db4 ddb3 ddb2 ddb1 ddb0 page 115 0x03 (0x23) pi n bpi n b7 pi n b6 pi n b5 pi n b4 pi n b3 pi n b2 pi n b1 pi n b0 page 115 0x02 (0x22) porta porta7 porta6 porta5 por ta4 porta3 porta2 porta1 porta0 page 115 0x01 (0x21) ddra dda7 dda6 dda5 d da4 dda3 dda2 dda1 dda0 page 115 0x00 (0x20) pi n api n a7 pi n a6 pi n a5 pi n a4 pi n a3 pi n a2 pi n a1 pi n a0 page 115 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 421 atmega640/1280/1281/2560/2561 2549k?avr?01/07 instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c, n ,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c, n ,v,h 1 adi w rdl,k add immediate to w ord rdh:rdl rdh:rdl + k z,c, n ,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c, n ,v,h 1 subi rd, k subtract constant from register rd rd - k z,c, n ,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c, n ,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c, n ,v,h 1 sbi w rdl,k subtract immediate from w ord rdh:rdl rdh:rdl - k z,c, n ,v,s 2 a n d rd, rr logical a n d registers rd rd ? rr z, n ,v 1 a n di rd, k logical a n d register and constant rd rd ? kz, n ,v 1 or rd, rr logical or registers rd rd v rr z, n ,v 1 ori rd, k logical or register and constant rd rd v k z, n ,v 1 eor rd, rr exclusive or registers rd rd rr z, n ,v 1 com rd one?s complement rd 0xff ? rd z,c, n ,v 1 n eg rd two?s complement rd 0x00 ? rd z,c, n ,v,h 1 sbr rd,k set bit(s) in register rd rd v k z, n ,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z, n ,v 1 i n c rd increment rd rd + 1 z, n ,v 1 dec rd decrement rd rd ? 1 z, n ,v 1 tst rd test for zero or minus rd rd ? rd z, n ,v 1 clr rd clear register rd rd rd z, n ,v 1 ser rd set register rd 0xff n one 1 mul rd, rr multiply unsigned r1:r0 rd x rr z,c 2 muls rd, rr multiply signed r1:r0 rd x rr z,c 2 mulsu rd, rr multiply signed with unsigned r1:r0 rd x rr z,c 2 fmul rd, rr fractional multiply unsigned r1:r0 (rd x rr) << 1 z,c 2 fmuls rd, rr fractional multiply signed r1:r0 (rd x rr) << 1 z,c 2 fmulsu rd, rr fractional multiply signed with unsigned r1:r0 (rd x rr) << 1 z,c 2 branch instructions rjmp k relative jump pc pc + k + 1 n one 2 ijmp indirect jump to (z) pc z n one 2 eijmp extended indirect jump to (z) pc (ei n d:z) n one 2 jmp k direct jump pc k n one 3 rcall k relative subroutine call pc pc + k + 1 n one 4 icall indirect call to (z) pc z n one 4 eicall extended indirect call to (z) pc (ei n d:z) n one 4 call k direct subroutine call pc k n one 5 ret subroutine return pc stack n one 5 reti interrupt return pc stack i 5 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 n one 1/2/3 cp rd,rr compare rd ? rr z, n ,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n ,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n ,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 n one 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 n one 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 n one 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 n one 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 n one 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 n one 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 n one 1/2 br n e k branch if n ot equal if (z = 0) then pc pc + k + 1 n one 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 n one 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 n one 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 n one 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 n one 1/2 brmi k branch if minus if ( n = 1) then pc pc + k + 1 n one 1/2 brpl k branch if plus if ( n = 0) then pc pc + k + 1 n one 1/2 brge k branch if greater or equal, signed if ( n v= 0) then pc pc + k + 1 n one 1/2 brlt k branch if less than zero, signed if ( n v= 1) then pc pc + k + 1 n one 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 n one 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 n one 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 n one 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 n one 1/2 422 atmega640/1280/1281/2560/2561 2549k?avr?01/07 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 n one 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 n one 1/2 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 n one 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 n one 1/2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1 n one 2 cbi p,b clear bit in i/o register i/o(p,b) 0 n one 2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c, n ,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c, n ,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c, n ,v 1 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c, n ,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c, n ,v 1 s w ap rd swap n ibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) n one 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) t n one 1 sec set carry c 1c1 clc clear carry c 0 c 1 se n set n egative flag n 1 n 1 cl n clear n egative flag n 0 n 1 sez set zero flag z 1z1 clz clear ze ro flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr move between registers rd rr n one 1 mov w rd, rr copy register w ord rd+1:rd rr+1:rr n one 1 ldi rd, k load immediate rd k n one 1 ld rd, x load indirect rd (x) n one 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 n one 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) n one 2 ld rd, y load indirect rd (y) n one 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 n one 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) n one 2 ldd rd,y+q load indirect with displacement rd (y + q) n one 2 ld rd, z load indirect rd (z) n one 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 n one 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) n one 2 ldd rd, z+q load indirect with displacement rd (z + q) n one 2 lds rd, k load direct from sram rd (k) n one 2 st x, rr store indirect (x) rr n one 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 n one 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr n one 2 st y, rr store indirect (y) rr n one 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 n one 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr n one 2 std y+q,rr store indirect with displacement (y + q) rr n one 2 st z, rr store indirect (z) rr n one 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 n one 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr n one 2 std z+q,rr store indirect with displacement (z + q) rr n one 2 sts k, rr store direct to sram (k) rr n one 2 lpm load program memory r0 (z) n one 3 lpm rd, z load program memory rd (z) n one 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 n one 3 elpm extended load program memory r0 (rampz:z) n one 3 elpm rd, z extended load program memory rd (rampz:z) n one 3 mnemonics operands description operation flags #clocks 423 atmega640/1280/1281/2560/2561 2549k?avr?01/07 n ote: eicall and eijmp do not exist in atmega640/1280/1281. elpm does not exist in atmega640. elpm rd, z+ extended load program memory rd (rampz:z), rampz:z rampz:z+1 n one 3 spm store program memory (z) r1:r0 n one - i n rd, p in port rd p n one 1 out p, rr out port p rr n one 1 push rr push register on stack stack rr n one 2 pop rd pop register from stack rd stack n one 2 mcu control instructions n op n o operation n one 1 sleep sleep (see specific descr. for sleep function) n one 1 w dr w atchdog reset (see specific descr. for w dr/timer) n one 1 break break for on-chip debug only n one n /a mnemonics operands description operation flags #clocks 424 atmega640/1280/1281/2560/2561 2549k?avr?01/07 ordering information n otes: 1. this device can also be supplied in wafer form. please c ontact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. see ?maximum speed vs. vcc? on page 377. 3. pb-free packaging, complies to the european directive for re striction of hazardous substances (rohs directive). also halide free and fully green. atmega640 speed (mhz) (2) power supply ordering code package (1)(3) operation range 8 1.8 - 5.5v atmega640v-8au atmega640v-8cu 100a 100c1 industrial ( -40 c to 85 c) 16 2.7 - 5.5v atmega640-16au atmega640-16cu 100a 100c1 industrial ( -40 c to 85 c) package type 64a 64-lead, thin (1.0 mm) plastic gull w ing quad flat package (tqfp) 64m2 64-pad, 9 x 9 x 1.0 mm body, quad flat n o-lead/micro lead frame package (qf n /mlf) 100a 100-lead, thin (1.0 mm) plastic gull w ing quad flat package (tqfp) 100c1 100-ball, chip ball grid array (cbga) 425 atmega640/1280/1281/2560/2561 2549k?avr?01/07 n otes: 1. this device can also be supplied in wafer form. please c ontact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. see ?maximum speed vs. vcc? on page 377. 3. pb-free packaging, complies to the european directive for re striction of hazardous substances (rohs directive). also halide free and fully green. atmega1281 speed (mhz) (2) power supply ordering code package (1)(3) operation range 8 1.8 - 5.5v atmega1281v-8au atmega1281v-8mu 64a 64m2 industrial ( -40 c to 85 c) 16 2.7 - 5.5v atmega1281-16au atmega1281-16mu 64a 64m2 industrial ( -40 c to 85 c) package type 64a 64-lead, thin (1.0 mm) plastic gull w ing quad flat package (tqfp) 64m2 64-pad, 9 x 9 x 1.0 mm body, quad flat n o-lead/micro lead frame package (qf n /mlf) 100a 100-lead, thin (1.0 mm) plastic gull w ing quad flat package (tqfp) 100c1 100-ball, chip ball grid array (cbga) 426 atmega640/1280/1281/2560/2561 2549k?avr?01/07 n otes: 1. this device can also be supplied in wafer form. please c ontact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. see ?maximum speed vs. vcc? on page 377. 3. pb-free packaging, complies to the european directive for re striction of hazardous substances (rohs directive). also halide free and fully green. atmega1280 speed (mhz) (2) power supply ordering code package (1)(3) operation range 8 1.8 - 5.5v atmega1280v-8au atmega1280v-8cu 100a 100c1 industrial ( -40 c to 85 c) 16 2.7 - 5.5v atmega1280-16au atmega1280-16au 100a 100c1 industrial ( -40 c to 85 c) package type 64a 64-lead, thin (1.0 mm) plastic gull w ing quad flat package (tqfp) 64m2 64-pad, 9 x 9 x 1.0 mm body, quad flat n o-lead/micro lead frame package (qf n /mlf) 100a 100-lead, thin (1.0 mm) plastic gull w ing quad flat package (tqfp) 100c1 100-ball, chip ball grid array (cbga) 427 atmega640/1280/1281/2560/2561 2549k?avr?01/07 n otes: 1. this device can also be supplied in wafer form. please c ontact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. see ?maximum speed vs. vcc? on page 377. 3. pb-free packaging, complies to the european directive for re striction of hazardous substances (rohs directive). also halide free and fully green. atmega2561 speed (mhz) (2) power supply ordering code package (1)(3) operation range 8 1.8 - 5.5v atmega2561v-8au atmega2561v-8mu 64a 64m2 industrial ( -40 c to 85 c) 16 4.5 - 5.5v atmega2561-16au atmega2561-16mu 64a 64m2 industrial ( -40 c to 85 c) package type 64a 64-lead, thin (1.0 mm) plastic gull w ing quad flat package (tqfp) 64m2 64-pad, 9 x 9 x 1.0 mm body, quad flat n o-lead/micro lead frame package (qf n /mlf) 100a 100-lead, thin (1.0 mm) plastic gull w ing quad flat package (tqfp) 100c1 100-ball, chip ball grid array (cbga) 428 atmega640/1280/1281/2560/2561 2549k?avr?01/07 n otes: 1. this device can also be supplied in wafer form. please c ontact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. see ?maximum speed vs. vcc? on page 377. 3. pb-free packaging, complies to the european directive for re striction of hazardous substances (rohs directive). also halide free and fully green. atmega2560 speed (mhz) (2) power supply ordering code package (1)(3) operation range 8 1.8 - 5.5v atmega2560v-8au atmega2560v-8cu 100a 100c1 industrial ( -40 c to 85 c) 16 4.5 - 5.5v atmega2560-16au atmega2560-16cu 100a 100c1 industrial ( -40 c to 85 c) package type 64a 64-lead, thin (1.0 mm) plastic gull w ing quad flat package (tqfp) 64m2 64-pad, 9 x 9 x 1.0 mm body, quad flat n o-lead/micro lead frame package (qf n /mlf) 100a 100-lead, thin (1.0 mm) plastic gull w ing quad flat package (tqfp) 100c1 100-ball, chip ball grid array (cbga) 429 atmega640/1280/1281/2560/2561 2549k?avr?01/07 packaging information 100a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 100a, 100-lead, 14 x 14 mm body size, 1.0 mm body thickness, 0.5 mm lead pitch, thin profile plastic quad flat package (tqfp) c 100a 10/5/2001 pi n 1 ide n tifier 0?~7? pi n 1 l c a1 a2 a d1 d e e1 e b a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 15.75 16.00 16.25 d1 13.90 14.00 14.10 n ote 2 e 15.75 16.00 16.25 e1 13.90 14.00 14.10 n ote 2 b 0.17 ? 0.27 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.50 typ n otes: 1. this package conforms to jedec reference ms-026, variation aed. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.08 mm maximum. common dimensions (unit of measure = mm) symbol min nom max note 430 atmega640/1280/1281/2560/2561 2549k?avr?01/07 100c1 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 100c1 , 100-ball, 9 x 9 x 1.2 mm body, ball pitch 0.80 mm chip array bga package (cbga) a 100c1 5/25/06 top view side view bottom view common dimensions (unit of measure = mm) symbol min nom max note a 1.10 ? 1.20 a1 0.30 0.35 0.40 d 8.90 9.00 9.10 e 8.90 9.00 9.10 d1 7.10 7.20 7.30 e1 7.10 7.20 7.30 ? b 0.35 0.40 0.45 e 0.80 typ marked a1 identifier 1 2 3 4 5 6 7 8 a b c d e 9 f g h i j 10 0.90 typ 0.90 typ a1 corner 0.12 z e d e e ?b a a1 e1 d1 431 atmega640/1280/1281/2560/2561 2549k?avr?01/07 64a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 64a, 64-lead, 14 x 14 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) b 64a 10/5/2001 pi n 1 ide n tifier 0?~7? pi n 1 l c a1 a2 a d1 d e e1 e b common dimensions (unit of measure = mm) symbol min nom max note n otes: 1. this package conforms to jedec reference ms-026, variation aeb. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 15.75 16.00 16.25 d1 13.90 14.00 14.10 n ote 2 e 15.75 16.00 16.25 e1 13.90 14.00 14.10 n ote 2 b 0.30 ? 0.45 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.80 typ 432 atmega640/1280/1281/2560/2561 2549k?avr?01/07 64m2 2325 orchard park w ay san jose, ca 95131 title drawing no. r rev. 64m2 , 64-pad, 9 x 9 x 1.0 mm body, lead pitch 0.50 mm, d 64m2 5/25/06 common dimen s ion s (unit of meas u re = mm) s ymbol min nom max note a 0. 8 0 0.90 1.00 a1 ? 0.02 0.05 b 0.1 8 0.25 0.30 d d2 7.50 7.65 7. 8 0 8 .90 9.00 9.10 8 .90 9.00 9.10 e e2 7.50 7.65 7. 8 0 e 0.50 bsc l 0.35 0.40 0.45 top view s ide view bottom view d e marked pin# 1 id seating plane a1 c a c 0.0 8 1 2 3 k 0.20 0.27 0.40 2. dimension and tolerance conform to asmey14.5m-1994. e2 d2 b e pin #1 corner l pin #1 triangle pin #1 chamfer (c 0.30) option a option b pin #1 notch (0.20 r) option c k k note: 1. jedec standard mo-220, (saw sing u lation) fig. 1, v mmd. 7.65 mm exposed pad, micro lead frame package (mlf) 433 atmega640/1280/1281/2560/2561 2549k?avr?01/07 errata atmega640 rev. a ? inaccurate adc conversion in diff erential mode with 200x gain ? high current consum ption in sleep mode 1. inaccurate adc conversion in differential mode with 200x gain w ith avcc < 3.6v, random conversions will be inaccurate. typical absolute accu- racy may reach 64 lsb. problem fix/workaround n one 2. high current consumption in sleep mode. if a pending interrupt cannot wake the part up from the selected sleep mode, the current consumption will increase during sleep when executing the sleep instruc- tion directly after a sei instruction. problem fix/workaround before entering sleep, interrupts not used to wake the part from the sleep mode should be disabled. atmega1280 rev. a ? inaccurate adc conversion in diff erential mode with 200x gain ? high current consum ption in sleep mode 1. inaccurate adc conversion in differential mode with 200x gain w ith avcc < 3.6v, random conversions will be inaccurate. typical absolute accu- racy may reach 64 lsb. problem fix/workaround n one 2. high current consumption in sleep mode. if a pending interrupt cannot wake the part up from the selected sleep mode, the current consumption will increase during sleep when executing the sleep instruc- tion directly after a sei instruction. problem fix/workaround before entering sleep, interrupts not used to wake the part from the sleep mode should be disabled. 434 atmega640/1280/1281/2560/2561 2549k?avr?01/07 atmega1281 rev. a ? inaccurate adc conversion in diff erential mode with 200x gain ? high current consum ption in sleep mode 1. inaccurate adc conversion in differential mode with 200x gain w ith avcc < 3.6v, random conversions will be inaccurate. typical absolute accu- racy may reach 64 lsb. problem fix/workaround n one 2. high current consumption in sleep mode. if a pending interrupt cannot wake the part up from the selected sleep mode, the current consumption will increase during sleep when executing the sleep instruc- tion directly after a sei instruction. problem fix/workaround before entering sleep, interrupts not used to wake the part from the sleep mode should be disabled. atmega2560 rev. e n o known errata. atmega2560 rev. d n ot sampled. atmega2560 rev. c ? high current consum ption in sleep mode 1. high current consumption in sleep mode. if a pending interrupt cannot wake the part up from the selected sleep mode, the current consumption will increase during sleep when executing the sleep instruc- tion directly after a sei instruction. problem fix/workaround before entering sleep, interrupts not used to wake the part from the sleep mode should be disabled. atmega2560 rev. b n ot sampled. 435 atmega640/1280/1281/2560/2561 2549k?avr?01/07 atmega2560 rev. a ? non-read-while-write area of flash not functional ? part does not work under 2.4 volts ? incorrect adc reading in differential mode ? internal adc reference has too low value ? in/out instructions may be executed twice when stack is in external ram ? eeprom read from application code does not work in lock bit mode 3 1. non-read-while-write area of flash not functional the n on-read- w hile- w rite area of the flash is not working as expected. the prob- lem is related to the speed of the part when reading the flash of this area. problem fix/workaround - only use the first 248k of the flash. - if boot functionality is needed, run the code in the n on-read- w hile- w rite area at maximum 1/4th of the maximum frequency of the device at any given voltage. this is done by writing the clkpr register before entering the boot section of the code 2. part does not work under 2.4 volts the part does not execute code correctly below 2.4 volts problem fix/workaround do not use the part at voltages below 2.4 volts. 3. incorrect adc reading in differential mode the adc has high noise in differential mode. it can give up to 7 lsb error. problem fix/workaround use only the 7 msb of the result when using the adc in differential mode. 4. internal adc reference has too low value the internal adc reference has a value lower than specified problem fix/workaround - use avcc or external reference - the actual value of the reference can be measured by applying a known voltage to the adc when using the internal reference. the result when doing later conversions can then be calibrated. 5. in/out instructions may be executed twice when stack is in external ram if either an i n or an out instruction is executed directly before an interrupt occurs and the stack pointer is located in external ram, the instruction will be executed twice. in some cases this will cause a problem, for example: - if reading sreg it will appear that the i-flag is cleared. - if writing to the pi n registers, the po rt will toggle twice. - if reading registers with interrupt flags, the flags will appea r to be cleared. problem fix/workaround there are two application work-arounds, where selecting one of them, will be omit- ting the issue: - replace i n and out with ld/lds/ldd and st/sts/std instructions - use internal ram for stack pointer. 436 atmega640/1280/1281/2560/2561 2549k?avr?01/07 6. eeprom read from applic ation code does not work in lock bit mode 3 w hen the memory lock bits lb2 and lb1 are programmed to mode 3, eeprom read does not work from the application code. problem fix/workaround do not set lock bit protection mode 3 when the application code needs to read from eeprom. atmega2561 rev. e n o known errata. atmega2561 rev. d n ot sampled. atmega2561 rev. c ? high current consum ption in sleep mode 1. high current consumption in sleep mode. if a pending interrupt cannot wake the part up from the selected sleep mode, the current consumption will increase during sleep when executing the sleep instruc- tion directly after a sei instruction. problem fix/workaround before entering sleep, interrupts not used to wake the part from the sleep mode should be disabled. atmega2561 rev. b n ot sampled. atmega2561 rev. a ? non-read-while-write area of flash not functional ? part does not work under 2.4 volts ? incorrect adc reading in differential mode ? internal adc reference has too low value ? in/out instructions may be executed twice when stack is in external ram ? eeprom read from application code does not work in lock bit mode 3 1. non-read-while-write area of flash not functional the n on-read- w hile- w rite area of the flash is not working as expected. the prob- lem is related to the speed of the part when reading the flash of this area. problem fix/workaround - only use the first 248k of the flash. - if boot functionality is needed, run the code in the n on-read- w hile- w rite area at maximum 1/4th of the maximum frequency of the device at any given voltage. this is done by writing the clkpr register before entering the boot section of the code. 437 atmega640/1280/1281/2560/2561 2549k?avr?01/07 2. part does not work under 2.4 volts the part does not execute code correctly below 2.4 volts problem fix/workaround do not use the part at voltages below 2.4 volts. 3. incorrect adc reading in differential mode the adc has high noise in differential mode. it can give up to 7 lsb error. problem fix/workaround use only the 7 msb of the result when using the adc in differential mode 4. internal adc reference has too low value the internal adc reference has a value lower than specified problem fix/workaround - use avcc or external reference - the actual value of the reference can be measured by applying a known voltage to the adc when using the internal reference. the result when doing later conversions can then be calibrated. 5. in/out instructions may be executed twice when stack is in external ram if either an i n or an out instruction is executed directly before an interrupt occurs and the stack pointer is located in external ram, the instruction will be executed twice. in some cases this will cause a problem, for example: - if reading sreg it will appear that the i-flag is cleared. - if writing to the pi n registers, the po rt will toggle twice. - if reading registers with interrupt flags, the flags will appea r to be cleared. problem fix/workaround there are two app lication workarounds, where sele cting one of them, will be omit- ting the issue: - replace i n and out with ld/lds/ldd and st/sts/std instructions - use internal ram for stack pointer. 6. eeprom read from applic ation code does not work in lock bit mode 3 w hen the memory lock bits lb2 and lb1 are programmed to mode 3, eeprom read does not work from the application code. problem fix/workaround do not set lock bit protection mode 3 when the application code needs to read from eeprom. 438 atmega640/1280/1281/2560/2561 2549k?avr?01/07 datasheet revision history please note that the referring page numbers in this section are referring to this docu- ment.the referring revision in this section are referring to the document revision. rev. 2549k-01/07 rev. 2549j-09/06 rev. 2549i-07/06 rev. 2549h-06/06 rev. 2549g-06/06 1. updated table 1 on page 3. 2. updated ?pin descriptions? on page 7. 3. updated ?stack pointer? on page 14. 4. updated ?bit 1 ? eepe: eeprom programming enable ? on page 33. 5. updated assembly code example in ?watchdog timer? on page 62. 6: updated ?eimsk ? external interrupt mask register? on page 79. 7. updated bit description in ?pcifr ? pin change interrupt flag register? on page 81. 8. updated code example in ?usart initialization? on page 215. 9. updated figure 120 on page 288. 10. updated ?dc characteristics? on page 374. 1. updated ?calibrated internal rc oscillator? on page 44. 2. updated code example in ?moving interrupts between application and boot section? on page 74. 3. updated ?timer/counter prescaler? on page 190. 4. updated ?device identification register? on page 309. 5. updated ?signature bytes? on page 345. 6. updated ?instruction set summary? on page 421. 1. updated table 74 on page 130, table 77 on page 131, table 79 on page 132, table 82 on page 149, table 84 on page 161, table 85 on page 161, table 89 on page 191, table 92 on page 192 and table 94 on page 193. 2. updated ?fast pwm mode? on page 151. 1. updated ?calibrated internal rc oscillator? on page 44. 2. updated ?osccal ? oscillator ca libration register? on page 48. 3. added table 172 on page 384. 1. updated ?features? on page 1. 2. added figure 2 on page 3, table 1 on page 3. 3. updated ?calibrated internal rc oscillator? on page 44. 4. updated ?power management and sleep modes? on page 50. 5. updated note for table 30 on page 67. 6. updated figure 121 on page 289 and figure 122 on page 289. 7. updated ?setting the boot loader lock bits by spm? on page 330. 439 atmega640/1280/1281/2560/2561 2549k?avr?01/07 rev. 2549f-04/06 rev. 2549e-04/06 rev. 2549d-12/05 rev. 2549c-09/05 8. updated ?ordering information? on page 424. 9. added package information ?100c1? on page 430. 10. updated ?errata? on page 433. 1. updated figure 15 on page 28, figure 16 on page 29 and figure 17 on page 29. 2. updated table 88 on page 191 and table 89 on page 191. 3. updated features in ?adc ? analog to digital converter? on page 279. 4. updated ?fuse bits? on page 343. 1. updated ?features? on page 1. 2. updated table 27 on page 60. 3. updated note for table 27 on page 60. 4. updated ?bit 6 ? acbg: analog comparator bandgap select? on page 277. 5. updated ?prescaling and conversion timing? on page 282. 5. updated ?maximum speed vs. vcc? on page 377. 6. updated ?ordering information? on page 424. 1. advanced information status changed to preliminary. 2. changed number of i/o ports from 51 to 54. 3. updatet typos in ?tccr0 a ? timer/counter contro l register a? on page 130. 4. updated features in ?adc ? analog to digital converter? on page 279. 5. updated operation in?adc ? analog to digital converter? on page 279 6. updated stabilizing time in ?changi ng channel or reference selection? on page 286. 7. updated figure 113 on page 280, figure 121 on page 289, figure 122 on page 289. 8. updated text in ?adcsrb ? adc cont rol and status register b? on page 295. 9. updated note for table 4 on page 41, table 51 on page 99, table 128 on page 294 and table 131 on page 299. 10. updated table 170 on page 382 and table 171 on page 383. 11. updated ?filling the temporary buffer (page loading)? on page 329. 12. updated ?typical characteristics? on page 390. 13. updated ?packaging information? on page 429. 14. updated ?errata? on page 433. 1. updated speed grade in section ?features? on page 1. 2. added ?resources? on page 9. 3. updated ?spi ? serial peripheral interface? on page 199. in slave mode, low and high period spi clock must be larger than 2 cpu cycles. 440 atmega640/1280/1281/2560/2561 2549k?avr?01/07 rev. 2549b-05/05 rev. 2549a-03/05 4. updated ?bit rate generator unit? on page 251. 5. updated ?maximum speed vs. vcc? on page 377. 6. updated ?ordering information? on page 424. 7. updated ?packaging information? on page 429. package 64m1 replaced by 64m2. 8. updated ?errata? on page 433. 1. jtag id/signature for atmega640 updated: 0x9608. 2. updated table 43 on page 94. 3. updated ?serial programming instruction set? on page 359. 4. updated ?errata? on page 433. 1. initial version. i atmega640/1280/1281/2560/2561 2549k?avr?01/07 table of contents features............... .............. .............. ............... .............. .............. .......... 1 pin configurations............ .............. ............... .............. .............. .......... 2 disclaimer ............................................................................................................. 4 overview.............. .............. .............. ............... .............. .............. .......... 5 block diagram ...................................................................................................... 5 comparison between atmega1281/2561 and atmega640/1280/2560 .............. 7 pin descriptions.................................................................................................... 7 resources ........... .............. .............. ............... .............. .............. .......... 9 about code examples........... ................ ................. ................ ............. 9 avr cpu core ................ .............. .............. .............. .............. ........... 10 introduction ......................................................................................................... 10 architectural overview........................................................................................ 10 alu ? arithmetic logic unit................................................................................ 11 status register ................................................................................................... 11 general purpose register file ........................................................................... 13 stack pointer ...................................................................................................... 14 instruction execution timing............................................................................... 16 reset and interrupt handling.............................................................................. 17 avr memories ........... ................. ................ .............. .............. ........... 19 in-system reprogrammable flash program memory ........................................ 19 sram data memory........................................................................................... 20 eeprom data memory............ ................ ................ ................ ................ .......... 22 i/o memory ......................................................................................................... 25 external memory interface.................................................................................. 26 register description ........................................................................................... 32 system clock and clock options ............. .............. .............. ........... 37 overview............................................................................................................. 37 clock systems and their distribution .................................................................. 38 clock sources..................................................................................................... 39 low power crystal oscillator.............................................................................. 40 full swing crystal oscillator ..................... .......................................................... 42 low frequency crystal oscillator ....................................................................... 44 calibrated internal rc oscillator .............. .......................................................... 44 128 khz internal oscillator.................................................................................. 45 external clock..................................................................................................... 45 clock output buffer ............................................................................................ 46 timer/counter oscillator........................... .......................................................... 46 system clock prescaler...................................................................................... 47 register description ........................................................................................... 48 ii atmega640/1280/1281/2560/2561 2549k?avr?01/07 power management and sleep modes......... .............. .............. ........ 50 sleep modes....................................................................................................... 50 idle mode ............................................................................................................ 51 adc n oise reduction mode............................................................................... 51 power-down mode.............................................................................................. 51 power-save mode............................................................................................... 51 standby mode..................................................................................................... 52 extended standby mode .................................................................................... 52 minimizing power consumption ......................................................................... 52 register description ........................................................................................... 54 system control and reset.................. ................ ................. ................ .............. ........... 57 internal voltage reference ................................................................................. 61 w atchdog timer ................................................................................................. 62 register description ........................................................................................... 66 interrupts ................ ................ ................ ................. ................ ........... 69 interrupt vectors in atmega640/1280/1281/2560/2561..................................... 69 reset and interrupt vector placement ................................................................ 71 moving interrupts between application and boot section .................................. 74 register description ........................................................................................... 76 external interrupts.......... .............. .............. .............. .............. ........... 77 pin change interrupt timing............................................................................... 77 register description ........................................................................................... 78 i/o-ports........ ................. ................ .............. .............. .............. ........... 83 introduction ......................................................................................................... 83 ports as general digital i/o ................................................................................ 84 alternate port functions ..................................................................................... 89 register description for i/o-ports..................................................................... 115 8-bit timer/counter0 with pw m............... ................ .............. ......... 119 overview........................................................................................................... 119 timer/counter clock sources........................................................................... 120 counter unit...................................................................................................... 120 output compare unit........................................................................................ 121 compare match output unit ............................................................................. 123 modes of operation .......................................................................................... 124 timer/counter timing diagrams....................................................................... 128 register description ......................................................................................... 130 16-bit timer/counter (timer /counter 1, 3, 4, and 5) ..................... 137 overview........................................................................................................... 137 accessing 16-bit registers ............................................................................... 139 iii atmega640/1280/1281/2560/2561 2549k?avr?01/07 timer/counter clock sources........................................................................... 143 counter unit...................................................................................................... 143 input capture unit............................................................................................. 144 output compare units ...................................................................................... 146 compare match output unit ............................................................................. 148 modes of operation .......................................................................................... 149 timer/counter timing diagrams....................................................................... 157 register description ......................................................................................... 160 timer/counter 0, 1, 3, 4, and 5 prescaler.............. ................ ......... 172 register description ......................................................................................... 173 output compare modulator (ocm1c0a) .. .............. .............. ......... 174 overview........................................................................................................... 174 description........................................................................................................ 174 8-bit timer/counter2 with pw m and asynchronous operation .. 176 overview........................................................................................................... 176 timer/counter clock sources........................................................................... 177 counter unit...................................................................................................... 177 modes of operation .......................................................................................... 179 output compare unit........................................................................................ 184 compare match output unit ............................................................................. 185 timer/counter timing diagrams....................................................................... 186 asynchronous operation of timer/counter2 .................................................... 188 timer/counter prescaler................................................................................... 190 register description ......................................................................................... 191 spi ? serial peripheral interface......... ................. ................ ........... 199 ss pin functionality.......................................................................................... 204 data modes ...................................................................................................... 204 register description ......................................................................................... 206 usart ............... .............. .............. .............. .............. .............. ......... 209 overview........................................................................................................... 209 clock generation .............................................................................................. 211 frame formats ................................................................................................. 214 usart initialization.......................................................................................... 215 data transmission ? the usart transmitter ................................................. 216 data reception ? the usart receiver .......................................................... 219 asynchronous data reception ......................................................................... 223 multi-processor communication mode ............................................................. 226 register description ......................................................................................... 227 examples of baud rate setting........................................................................ 232 usart in spi mode ............. ................ ................. ................ ........... 236 iv atmega640/1280/1281/2560/2561 2549k?avr?01/07 overview........................................................................................................... 236 usart mspim vs. spi .................................................................................... 236 clock generation .............................................................................................. 236 spi data modes and timing............................................................................. 237 frame formats ................................................................................................. 238 data transfer.................................................................................................... 240 usart mspim register description ............................................................... 242 2-wire serial interface....... .............. ............... .............. .............. ...... 245 features............................................................................................................ 245 2-wire serial interface bus definition................................................................ 245 data transfer and frame format ..................................................................... 246 multi-master bus systems, arbitration and synchronization ............................ 249 overview of the t w i module ............................................................................ 251 using the t w i ................................................................................................... 253 transmission modes......................................................................................... 256 multi-master systems and arbitration............................................................... 269 register description ......................................................................................... 271 ac ? analog comparator ...... ................ ................. ................ ......... 275 analog comparator multiplexed input .............................................................. 276 register description ......................................................................................... 277 adc ? analog to digital co nverter ....................... ................ ......... 279 features............................................................................................................ 279 operation .......................................................................................................... 281 starting a conversion ....................................................................................... 281 prescaling and conversion timing ................................................................... 282 changing channel or reference selection ...................................................... 286 adc n oise canceler......................................................................................... 287 adc conversion result.................................................................................... 292 register description ......................................................................................... 294 jtag interface and on-chi p debug system ............. .............. ...... 301 overview........................................................................................................... 301 tap - test access port .................................................................................... 303 using the boundary-scan chain ....................................................................... 305 using the on-chip debug system .................................................................... 305 on-chip debug specific jtag instructions ...................................................... 306 using the jtag programming capabilities . ..................................................... 306 bibliography ...................................................................................................... 306 on-chip debug related register in i/o memory .............................................. 307 ieee 1149.1 (jtag) boundary-scan ......... .............. .............. ......... 308 features............................................................................................................ 308 system overview.............................................................................................. 308 v atmega640/1280/1281/2560/2561 2549k?avr?01/07 data registers .................................................................................................. 308 boundary-scan specific jtag instructions ...................................................... 310 boundary-scan chain ....................................................................................... 311 boundary-scan related register in i/o memory .............................................. 314 atmega640/1280/1281/2560/2561 boundary-scan order............................... 315 boundary-scan description language files ..................................................... 315 boot loader support ? read-while- write self-programming ..... 323 boot loader features ....................................................................................... 323 application and boot loader flash sections .................................................... 323 read- w hile- w rite and n o read- w hile- w rite flash sections........................... 323 boot loader lock bits....................................................................................... 326 entering the boot loader program ................................................................... 327 addressing the flash during self-programming .............................................. 328 self-programming the flash ............................................................................. 328 register description ......................................................................................... 340 memory programming........... ................ ................. ................ ......... 342 program and data memory lock bits .............................................................. 342 fuse bits........................................................................................................... 343 signature bytes ................................................................................................ 345 calibration byte ................................................................................................ 345 page size ......................................................................................................... 345 parallel programming parameters, pin mapping, and commands .................. 345 parallel programming ....................................................................................... 348 serial downloading........................................................................................... 356 programming via the jtag interface ............................................................... 361 electrical characteristics...... ................ ................. ................ ......... 374 absolute maximum ratings*............................................................................. 374 dc characteristics............................................................................................ 374 external clock drive w aveforms ...................................................................... 376 external clock drive ......................................................................................... 376 maximum speed vs. v cc ......................................................................................................................... 377 2-wire serial interface characteristics .............................................................. 379 spi timing characteristics ............................................................................... 380 adc characteristics ? preliminary data........................................................... 382 calibrated internal rc osc illator accuracy ...................................................... 384 external data memory timing .......................................................................... 385 typical characteristics ......... ................ ................. ................ ......... 390 active supply current ....................................................................................... 390 idle supply current ........................................................................................... 393 supply current of io modules .......................................................................... 395 power-down supply current............................................................................. 397 power-save supply current.............................................................................. 398 vi atmega640/1280/1281/2560/2561 2549k?avr?01/07 standby supply current.................................................................................... 399 pin pull-up ........................................................................................................ 399 pin driver strength ........................................................................................... 402 pin threshold and hysteresis........................................................................... 404 bod threshold and analog comparator offset ............................................... 407 internal oscillator speed ....................... ........................................................... 409 current consumption of peripheral units ......................................................... 411 current consumption in reset and reset pulsewidth...................................... 414 register summary ..... ................. ................ .............. .............. ......... 416 instruction set summary ...... ................ ................. ................ ......... 421 ordering information........... ................ ................. ................ ........... 424 atmega640 ...................................................................................................... 424 atmega1281 .................................................................................................... 425 atmega1280 .................................................................................................... 426 atmega2561 .................................................................................................... 427 atmega2560 .................................................................................................... 428 packaging information .......... ................ ................. ................ ......... 429 100a ................................................................................................................. 429 100c1 ............................................................................................................... 430 .......................................................................................................................... 430 64a ................................................................................................................... 431 64m2................................................................................................................. 432 errata ............... ................ .............. .............. .............. .............. ......... 433 atmega640 rev. a............................................................................................ 433 atmega1280 rev. a.......................................................................................... 433 atmega1281 rev. a.......................................................................................... 434 atmega2560 rev. e.......................................................................................... 434 atmega2560 rev. d.......................................................................................... 434 atmega2560 rev. c.......................................................................................... 434 atmega2560 rev. b.......................................................................................... 434 atmega2560 rev. a.......................................................................................... 435 atmega2561 rev. e.......................................................................................... 436 atmega2561 rev. d.......................................................................................... 436 atmega2561 rev. c.......................................................................................... 436 atmega2561 rev. b.......................................................................................... 436 atmega2561 rev. a.......................................................................................... 436 datasheet revision history ... ............... ................. ................ ......... 438 rev. 2549k-01/07............................................................................................. 438 rev. 2549j-09/06 ............................................................................................. 438 rev. 2549i-07/06 .............................................................................................. 438 vii atmega640/1280/1281/2560/2561 2549k?avr?01/07 rev. 2549h-06/06............................................................................................. 438 rev. 2549g-06/06 ............................................................................................ 438 rev. 2549f-04/06 ............................................................................................. 439 rev. 2549e-04/06............................................................................................. 439 rev. 2549d-12/05............................................................................................. 439 rev. 2549c-09/05............................................................................................. 439 rev. 2549b-05/05............................................................................................. 440 rev. 2549a-03/05............................................................................................. 440 table of contents ................ .............. .............. .............. .............. ......... i viii atmega640/1280/1281/2560/2561 2549k?avr?01/07 2549k?avr?01/07 ? 2007 atmel corporation . all rights reserved. at m e l ? , logo and combinations thereof, everywhere you are ? , avr ? , avr studio ? and oth- ers, are registered trademarks or trademarks of atmel corporati on or its subsidiaries. other terms and product names may be tra demarks of oth- ers. disclaimer: the information in this document is pr ovided in connection with atmel products. n o license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel? s web site, atmel assumes no liability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to , the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, conseque ntial, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if at mel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or co mpleteness of the contents of this document and reserves the rig ht to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications in tended to support or sustain life. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 n antes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imagin g/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 literature requests www.atmel.com/literature |
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